GB1006498A - Improvements in or relating to circuit connector assemblies - Google Patents

Improvements in or relating to circuit connector assemblies

Info

Publication number
GB1006498A
GB1006498A GB3366163A GB3366163A GB1006498A GB 1006498 A GB1006498 A GB 1006498A GB 3366163 A GB3366163 A GB 3366163A GB 3366163 A GB3366163 A GB 3366163A GB 1006498 A GB1006498 A GB 1006498A
Authority
GB
United Kingdom
Prior art keywords
board
wiring
holes
terminals
electro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3366163A
Inventor
Louis Edward Quintrell Walker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Co Ltd filed Critical Marconi Co Ltd
Priority to GB3366163A priority Critical patent/GB1006498A/en
Publication of GB1006498A publication Critical patent/GB1006498A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

1,006,498. Printed circuits. MARCONI CO. Ltd. June 10, 1964 [Aug. 26, 1968], No. 33661/63. Heading H1R A multilayer printed circuit, Fig. 1, having wiring 5, 6, 7 at different levels interconnected where required by interlayer terminals 8, is built up layer by layer, using insulating boards 1 . . . 4 of epoxy-glass with preformed holes to accommodate the terminals 8. In Fig. 3, board 1 is placed on a film of conductive paste on a glass plate 12, and copper 13 is electro-deposited in the holes in the board. Wiring pattern 5 is silk-screened on to board 1 and built up by electro-deposition of copper; then an uncured epoxy resin 15 is applied to board 1 to a level flush with wiring 5, board 2 is laid in place with its holes 16 in register with those of board 1 and resin 15 is cured. Holes 16 are filled with copper by electro-deposition and wiring 6 formed in the same way as wiring 5. These steps are repeated until the multilayer circuit is completed, when the assembly is stripped from plate 12. Terminals 8, Fig. 1, may be drilled to provide axial holes to accommodate component leads, which are soldered to the terminals at the face of the assembly remote from the component.
GB3366163A 1963-08-26 1963-08-26 Improvements in or relating to circuit connector assemblies Expired GB1006498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB3366163A GB1006498A (en) 1963-08-26 1963-08-26 Improvements in or relating to circuit connector assemblies

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3366163A GB1006498A (en) 1963-08-26 1963-08-26 Improvements in or relating to circuit connector assemblies

Publications (1)

Publication Number Publication Date
GB1006498A true GB1006498A (en) 1965-10-06

Family

ID=10355794

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3366163A Expired GB1006498A (en) 1963-08-26 1963-08-26 Improvements in or relating to circuit connector assemblies

Country Status (1)

Country Link
GB (1) GB1006498A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5082718A (en) * 1989-07-27 1992-01-21 Bull S.A. Method for depositing an insulating layer on a conductive layer of a multi-layer connection board of one very large scale integrated circuit
US5231757A (en) * 1989-07-27 1993-08-03 Bull, S.A. Method for forming the multi-layer structure of a connection board of at least one very large scale integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5082718A (en) * 1989-07-27 1992-01-21 Bull S.A. Method for depositing an insulating layer on a conductive layer of a multi-layer connection board of one very large scale integrated circuit
US5231757A (en) * 1989-07-27 1993-08-03 Bull, S.A. Method for forming the multi-layer structure of a connection board of at least one very large scale integrated circuit

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