FR3109227B1 - Contrôleur d’interruption et procédé de gestion d’un tel contrôleur - Google Patents
Contrôleur d’interruption et procédé de gestion d’un tel contrôleur Download PDFInfo
- Publication number
- FR3109227B1 FR3109227B1 FR2003733A FR2003733A FR3109227B1 FR 3109227 B1 FR3109227 B1 FR 3109227B1 FR 2003733 A FR2003733 A FR 2003733A FR 2003733 A FR2003733 A FR 2003733A FR 3109227 B1 FR3109227 B1 FR 3109227B1
- Authority
- FR
- France
- Prior art keywords
- controller
- clk
- interrupt
- clock signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/82—Protecting input, output or interconnection devices
- G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Bus Control (AREA)
Abstract
Dispositif électronique, comportant un contrôleur d’interruption (CI) possédant une entrée (EC) pour recevoir un signal d’horloge contrôleur (CLK-CI), une sortie (SC) et configuré pour délivrer un signal d’interruption de sortie (ILACout) sur ladite sortie (SC) en présence dudit signal d’horloge contrôleur (CLK-CI), et un circuit de commande (CC). Le circuit de commande possède, une interface d’entrée pour recevoir au moins un signal d’interruption (ILACin) susceptible d’émaner d’au moins un équipement externe (EQ1, EQ2, EQ3) au dispositif, une entrée d’horloge (ECK) pour recevoir un signal d’horloge externe (CLK), et des moyens de commande connectés à l’interface d’entrée et à l’entrée d’horloge (ECK). Les moyens de commandes sont configurés pour générer automatiquement le signal d’horloge contrôleur (CLK-CI) à partir du signal d’horloge externe (CLK) en présence dudit au moins un signal d’interruption (ILACin) et jusqu’à une délivrance du signal d’interruption de sortie (ILACout) correspondant. Figure pour l’abrégé : Fig 1
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2003733A FR3109227B1 (fr) | 2020-04-14 | 2020-04-14 | Contrôleur d’interruption et procédé de gestion d’un tel contrôleur |
US17/229,307 US11550744B2 (en) | 2020-04-14 | 2021-04-13 | Interrupt controller and method of managing an interrupt controller |
CN202110402330.3A CN113535613B (zh) | 2020-04-14 | 2021-04-14 | 中断控制器和管理中断控制器的方法 |
US18/065,475 US11853241B2 (en) | 2020-04-14 | 2022-12-13 | Interrupt controller and method of managing an interrupt controller |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2003733 | 2020-04-14 | ||
FR2003733A FR3109227B1 (fr) | 2020-04-14 | 2020-04-14 | Contrôleur d’interruption et procédé de gestion d’un tel contrôleur |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3109227A1 FR3109227A1 (fr) | 2021-10-15 |
FR3109227B1 true FR3109227B1 (fr) | 2022-05-06 |
Family
ID=72266392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR2003733A Active FR3109227B1 (fr) | 2020-04-14 | 2020-04-14 | Contrôleur d’interruption et procédé de gestion d’un tel contrôleur |
Country Status (2)
Country | Link |
---|---|
US (2) | US11550744B2 (fr) |
FR (1) | FR3109227B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3109227B1 (fr) * | 2020-04-14 | 2022-05-06 | St Microelectronics Alps Sas | Contrôleur d’interruption et procédé de gestion d’un tel contrôleur |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000020265A (ko) * | 1998-09-18 | 2000-04-15 | 윤종용 | 인터럽트 컨트롤러 |
JP2001350738A (ja) * | 2000-06-08 | 2001-12-21 | Mitsubishi Electric Corp | フラッシュメモリ内蔵マイクロコンピュータ |
GB2368671B (en) * | 2000-11-03 | 2004-08-18 | Advanced Risc Mach Ltd | A logic unit and integrated circuit for clearing interrupts |
GB2396445B (en) * | 2002-12-19 | 2005-12-21 | Advanced Risc Mach Ltd | An interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources |
GB2433794B (en) * | 2005-12-21 | 2010-08-18 | Advanced Risc Mach Ltd | Interrupt controller utiilising programmable priority values |
CN102566739B (zh) * | 2012-01-06 | 2014-11-26 | 威盛电子股份有限公司 | 多核处理器***及其动态电源管理方法与控制装置 |
US9323312B2 (en) * | 2012-09-21 | 2016-04-26 | Atmel Corporation | System and methods for delaying interrupts in a microcontroller system |
JP6048507B2 (ja) * | 2012-09-27 | 2016-12-21 | 富士通株式会社 | 変換装置、変換方法、および情報処理システム |
US9304571B2 (en) * | 2013-04-12 | 2016-04-05 | Apple Inc. | Interrupt based power state management |
US10788853B2 (en) * | 2017-01-31 | 2020-09-29 | Texas Instruments Incorporated | Interrupt handling method and apparatus for slow peripherals |
CN111316234B (zh) * | 2017-09-12 | 2024-03-12 | 恩倍科微公司 | 极低功率微控制器*** |
FR3109227B1 (fr) * | 2020-04-14 | 2022-05-06 | St Microelectronics Alps Sas | Contrôleur d’interruption et procédé de gestion d’un tel contrôleur |
-
2020
- 2020-04-14 FR FR2003733A patent/FR3109227B1/fr active Active
-
2021
- 2021-04-13 US US17/229,307 patent/US11550744B2/en active Active
-
2022
- 2022-12-13 US US18/065,475 patent/US11853241B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR3109227A1 (fr) | 2021-10-15 |
CN113535613A (zh) | 2021-10-22 |
US20230113667A1 (en) | 2023-04-13 |
US11853241B2 (en) | 2023-12-26 |
US20210318972A1 (en) | 2021-10-14 |
US11550744B2 (en) | 2023-01-10 |
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