FR3064384B1 - Bloc refractaire pour dispositif integre de neurone artificiel - Google Patents
Bloc refractaire pour dispositif integre de neurone artificiel Download PDFInfo
- Publication number
- FR3064384B1 FR3064384B1 FR1752384A FR1752384A FR3064384B1 FR 3064384 B1 FR3064384 B1 FR 3064384B1 FR 1752384 A FR1752384 A FR 1752384A FR 1752384 A FR1752384 A FR 1752384A FR 3064384 B1 FR3064384 B1 FR 3064384B1
- Authority
- FR
- France
- Prior art keywords
- refractory block
- terminal
- coupled
- block
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Molecular Biology (AREA)
- General Health & Medical Sciences (AREA)
- Evolutionary Computation (AREA)
- Mathematical Physics (AREA)
- Computational Linguistics (AREA)
- Artificial Intelligence (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Dispositif intégré de neurone artificiel comportant un bloc réfractaire (3) configuré pour inhiber le bloc intégrateur (1) durant une durée d'inhibition après ladite délivrance d'au moins un signal de sortie (Si) par le bloc générateur (2), le bloc réfractaire (3) comportant un premier transistor MOS (Ts1) couplé entre la borne d'entrée (BE) et la borne de référence (BR) et dont la grille (Gs1) est connectée à ladite borne de sortie (BS) par l'intermédiaire d'un deuxième transistor MOS (Ts2) dont une première électrode (Ds2) est couplée à ladite borne d'alimentation (BV) et dont la grille (Gs2) est couplée à la borne de sortie (BS), le bloc réfractaire (3) comportant en outre un circuit résistif-capacitif couplé entre la borne d'alimentation (BV), la borne de référence (BR) et la grille du deuxième transistor MOS (Ts2), ladite durée d'inhibition dépendant de la constante de temps dudit circuit résistif-capacitif.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1752384A FR3064384B1 (fr) | 2017-03-23 | 2017-03-23 | Bloc refractaire pour dispositif integre de neurone artificiel |
CN201721105807.7U CN207319273U (zh) | 2017-03-23 | 2017-08-31 | 集成人工神经元器件和集成电路 |
CN201710770721.4A CN108629404B (zh) | 2017-03-23 | 2017-08-31 | 用于集成人工神经元器件的不应电路 |
US15/697,598 US20180276536A1 (en) | 2017-03-23 | 2017-09-07 | Refractory circuit for integrated artificial neuron device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1752384A FR3064384B1 (fr) | 2017-03-23 | 2017-03-23 | Bloc refractaire pour dispositif integre de neurone artificiel |
FR1752384 | 2017-03-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3064384A1 FR3064384A1 (fr) | 2018-09-28 |
FR3064384B1 true FR3064384B1 (fr) | 2019-05-03 |
Family
ID=59520991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1752384A Expired - Fee Related FR3064384B1 (fr) | 2017-03-23 | 2017-03-23 | Bloc refractaire pour dispositif integre de neurone artificiel |
Country Status (3)
Country | Link |
---|---|
US (1) | US20180276536A1 (fr) |
CN (2) | CN108629404B (fr) |
FR (1) | FR3064384B1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20180112458A (ko) * | 2017-04-04 | 2018-10-12 | 에스케이하이닉스 주식회사 | 두 개의 트랜지스터들 및 하나의 가변 저항 소자를 가진 시냅스 및 상기 시냅스를 포함하는 시냅스 어레이 |
CN109376853B (zh) * | 2018-10-26 | 2021-09-24 | 电子科技大学 | 回声状态神经网络输出轴突电路 |
US11443177B2 (en) * | 2019-11-15 | 2022-09-13 | Jiangsu Advanced Memory Technology Co., Ltd. | Artificial neuromorphic circuit and operation method |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242988B1 (en) * | 1999-09-29 | 2001-06-05 | Lucent Technologies Inc. | Spiking neuron circuit |
CN101997538B (zh) * | 2009-08-19 | 2013-06-05 | 中国科学院半导体研究所 | 基于脉冲耦合的硅纳米线cmos神经元电路 |
US8473439B2 (en) * | 2010-12-08 | 2013-06-25 | International Business Machines Corporation | Integrate and fire electronic neurons |
CN102610274B (zh) * | 2012-04-06 | 2014-10-15 | 电子科技大学 | 一种阻变突触权值调整电路 |
EP2877958B1 (fr) * | 2012-07-25 | 2019-09-04 | HRL Laboratories, LLC | Circuit neuronal et procédé |
CN107733405A (zh) * | 2012-12-31 | 2018-02-23 | 意法半导体研发(上海)有限公司 | 传输门电路 |
US9542643B2 (en) * | 2013-05-21 | 2017-01-10 | Qualcomm Incorporated | Efficient hardware implementation of spiking networks |
CN105160401B (zh) * | 2015-08-27 | 2017-08-11 | 电子科技大学 | 一种基于忆阻器阵列的wta神经网络及其应用 |
CN105787291B (zh) * | 2016-01-29 | 2018-04-17 | 西安交通大学 | 一种模拟实现Morris‑Lecar神经元模型的电路 |
-
2017
- 2017-03-23 FR FR1752384A patent/FR3064384B1/fr not_active Expired - Fee Related
- 2017-08-31 CN CN201710770721.4A patent/CN108629404B/zh active Active
- 2017-08-31 CN CN201721105807.7U patent/CN207319273U/zh active Active
- 2017-09-07 US US15/697,598 patent/US20180276536A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20180276536A1 (en) | 2018-09-27 |
CN207319273U (zh) | 2018-05-04 |
CN108629404A (zh) | 2018-10-09 |
CN108629404B (zh) | 2022-07-15 |
FR3064384A1 (fr) | 2018-09-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20180928 |
|
PLFP | Fee payment |
Year of fee payment: 3 |
|
PLFP | Fee payment |
Year of fee payment: 4 |
|
ST | Notification of lapse |
Effective date: 20211105 |