FR2968833B1 - Procédé d'amincissement et de découpe de plaquettes de circuits électroniques - Google Patents
Procédé d'amincissement et de découpe de plaquettes de circuits électroniquesInfo
- Publication number
- FR2968833B1 FR2968833B1 FR1060375A FR1060375A FR2968833B1 FR 2968833 B1 FR2968833 B1 FR 2968833B1 FR 1060375 A FR1060375 A FR 1060375A FR 1060375 A FR1060375 A FR 1060375A FR 2968833 B1 FR2968833 B1 FR 2968833B1
- Authority
- FR
- France
- Prior art keywords
- slimming
- electronic circuit
- circuit boards
- wafer
- cutting electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T83/00—Cutting
- Y10T83/929—Tool or tool with support
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1060375A FR2968833B1 (fr) | 2010-12-10 | 2010-12-10 | Procédé d'amincissement et de découpe de plaquettes de circuits électroniques |
US13/313,282 US8486763B2 (en) | 2010-12-10 | 2011-12-07 | Method for thinning and dicing electronic circuit wafers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1060375A FR2968833B1 (fr) | 2010-12-10 | 2010-12-10 | Procédé d'amincissement et de découpe de plaquettes de circuits électroniques |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2968833A1 FR2968833A1 (fr) | 2012-06-15 |
FR2968833B1 true FR2968833B1 (fr) | 2013-11-15 |
Family
ID=44279714
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1060375A Expired - Fee Related FR2968833B1 (fr) | 2010-12-10 | 2010-12-10 | Procédé d'amincissement et de découpe de plaquettes de circuits électroniques |
Country Status (2)
Country | Link |
---|---|
US (1) | US8486763B2 (fr) |
FR (1) | FR2968833B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6479532B2 (ja) | 2015-03-30 | 2019-03-06 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5731222A (en) * | 1995-08-01 | 1998-03-24 | Hughes Aircraft Company | Externally connected thin electronic circuit having recessed bonding pads |
JP2004119718A (ja) * | 2002-09-26 | 2004-04-15 | Shinko Electric Ind Co Ltd | 薄型半導体チップの製造方法 |
JP4860113B2 (ja) * | 2003-12-26 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
WO2008157722A1 (fr) * | 2007-06-19 | 2008-12-24 | Vertical Circuits, Inc. | Passivation de surface sur galette de puces de circuits intégrés empilables |
-
2010
- 2010-12-10 FR FR1060375A patent/FR2968833B1/fr not_active Expired - Fee Related
-
2011
- 2011-12-07 US US13/313,282 patent/US8486763B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20120149174A1 (en) | 2012-06-14 |
US8486763B2 (en) | 2013-07-16 |
FR2968833A1 (fr) | 2012-06-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150831 |