FR2959868A1 - Dispositif semi-conducteur a plots de connexion munis d'inserts - Google Patents

Dispositif semi-conducteur a plots de connexion munis d'inserts Download PDF

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Publication number
FR2959868A1
FR2959868A1 FR1053552A FR1053552A FR2959868A1 FR 2959868 A1 FR2959868 A1 FR 2959868A1 FR 1053552 A FR1053552 A FR 1053552A FR 1053552 A FR1053552 A FR 1053552A FR 2959868 A1 FR2959868 A1 FR 2959868A1
Authority
FR
France
Prior art keywords
semiconductor device
inserts
connecting plates
pads
recesses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR1053552A
Other languages
English (en)
Inventor
Vincent Fiori
Philippe Delpech
Eric Sabouret
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA, STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics SA
Priority to FR1053552A priority Critical patent/FR2959868A1/fr
Priority to US13/100,860 priority patent/US20110272801A1/en
Publication of FR2959868A1 publication Critical patent/FR2959868A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2224/04073—Bonding areas specifically adapted for connectors of different types
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    • H01L2224/0554—External layer
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    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Dispositif semi-conducteur comprenant un circuit intégré et des plots de connexion électrique extérieure, dans lequel les plots (3) présentent des évidements (E) au moins partiellement remplis par une matière différente de celle les constituant, de façon à former des inserts (I).
FR1053552A 2010-05-06 2010-05-06 Dispositif semi-conducteur a plots de connexion munis d'inserts Withdrawn FR2959868A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1053552A FR2959868A1 (fr) 2010-05-06 2010-05-06 Dispositif semi-conducteur a plots de connexion munis d'inserts
US13/100,860 US20110272801A1 (en) 2010-05-06 2011-05-04 Semiconductor device with connection pads provided with inserts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1053552A FR2959868A1 (fr) 2010-05-06 2010-05-06 Dispositif semi-conducteur a plots de connexion munis d'inserts

Publications (1)

Publication Number Publication Date
FR2959868A1 true FR2959868A1 (fr) 2011-11-11

Family

ID=42561188

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1053552A Withdrawn FR2959868A1 (fr) 2010-05-06 2010-05-06 Dispositif semi-conducteur a plots de connexion munis d'inserts

Country Status (2)

Country Link
US (1) US20110272801A1 (fr)
FR (1) FR2959868A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780051B2 (en) 2013-12-18 2017-10-03 Nxp Usa, Inc. Methods for forming semiconductor devices with stepped bond pads
EP2908337A1 (fr) * 2014-02-12 2015-08-19 ams AG Dispositif à semi-conducteur avec plot de contact thermiquement stable sur un TSV et procédé de production d'un tel dispositif à semi-conducteur
US10002840B1 (en) * 2017-08-08 2018-06-19 Micron Technology, Inc. Semiconductor devices having discretely located passivation material, and associated systems and methods

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61172362A (ja) * 1985-01-28 1986-08-04 Seiko Epson Corp ボンデイング電極構造
US6084301A (en) * 1995-02-13 2000-07-04 Industrial Technology Industrial Research Composite bump structures
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
GB2364170A (en) * 1999-12-16 2002-01-16 Lucent Technologies Inc Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
EP1548815A1 (fr) * 2002-08-30 2005-06-29 Fujitsu Limited Dispositif a semi-conducteur et son procede de fabrication
JP2006019497A (ja) * 2004-07-01 2006-01-19 Seiko Epson Corp 半導体装置及びその製造方法
US20060175711A1 (en) * 2005-02-08 2006-08-10 Hannstar Display Corporation Structure and method for bonding an IC chip
US20100032832A1 (en) * 2007-05-11 2010-02-11 Panasonic Corporation Semiconductor chip and semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8492263B2 (en) * 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61172362A (ja) * 1985-01-28 1986-08-04 Seiko Epson Corp ボンデイング電極構造
US6084301A (en) * 1995-02-13 2000-07-04 Industrial Technology Industrial Research Composite bump structures
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
GB2364170A (en) * 1999-12-16 2002-01-16 Lucent Technologies Inc Dual damascene bond pad structure for lowering stress and allowing circuitry under pads
EP1548815A1 (fr) * 2002-08-30 2005-06-29 Fujitsu Limited Dispositif a semi-conducteur et son procede de fabrication
JP2006019497A (ja) * 2004-07-01 2006-01-19 Seiko Epson Corp 半導体装置及びその製造方法
US20060175711A1 (en) * 2005-02-08 2006-08-10 Hannstar Display Corporation Structure and method for bonding an IC chip
US20100032832A1 (en) * 2007-05-11 2010-02-11 Panasonic Corporation Semiconductor chip and semiconductor device

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