FR2921200B1 - Heterostructures semi-conductrices monolithiques epitaxiees et leur procede de fabrication - Google Patents

Heterostructures semi-conductrices monolithiques epitaxiees et leur procede de fabrication

Info

Publication number
FR2921200B1
FR2921200B1 FR0757652A FR0757652A FR2921200B1 FR 2921200 B1 FR2921200 B1 FR 2921200B1 FR 0757652 A FR0757652 A FR 0757652A FR 0757652 A FR0757652 A FR 0757652A FR 2921200 B1 FR2921200 B1 FR 2921200B1
Authority
FR
France
Prior art keywords
epitaxic
manufacture
monolithic semiconductor
semiconductor heterostructures
heterostructures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0757652A
Other languages
English (en)
Other versions
FR2921200A1 (fr
Inventor
Girons Guillaume Saint
Ludovic Largeau
Gilles Patriarche
Philippe Regreny
Guy Hollinger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Original Assignee
Centre National de la Recherche Scientifique CNRS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0757652A priority Critical patent/FR2921200B1/fr
Application filed by Centre National de la Recherche Scientifique CNRS filed Critical Centre National de la Recherche Scientifique CNRS
Priority to US12/678,548 priority patent/US8389995B2/en
Priority to PCT/FR2008/051669 priority patent/WO2009047448A1/fr
Priority to EP08837575A priority patent/EP2188830A1/fr
Priority to JP2010525404A priority patent/JP2010539723A/ja
Publication of FR2921200A1 publication Critical patent/FR2921200A1/fr
Application granted granted Critical
Publication of FR2921200B1 publication Critical patent/FR2921200B1/fr
Priority to JP2014138772A priority patent/JP6062887B2/ja
Priority to JP2016205042A priority patent/JP2017028318A/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Physical Vapour Deposition (AREA)
FR0757652A 2007-09-18 2007-09-18 Heterostructures semi-conductrices monolithiques epitaxiees et leur procede de fabrication Expired - Fee Related FR2921200B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0757652A FR2921200B1 (fr) 2007-09-18 2007-09-18 Heterostructures semi-conductrices monolithiques epitaxiees et leur procede de fabrication
PCT/FR2008/051669 WO2009047448A1 (fr) 2007-09-18 2008-09-17 Hétérostructures semi-conductrices monolithiques épitaxiées et leur procédé de fabrication
EP08837575A EP2188830A1 (fr) 2007-09-18 2008-09-17 Hétérostructures semi-conductrices monolithiques épitaxiées et leur procédé de fabrication
JP2010525404A JP2010539723A (ja) 2007-09-18 2008-09-17 エピタキシャル固体半導体ヘテロ構造及びその製造方法
US12/678,548 US8389995B2 (en) 2007-09-18 2008-09-17 Epitaxial solid-state semiconducting heterostructures and method for making same
JP2014138772A JP6062887B2 (ja) 2007-09-18 2014-07-04 エピタキシャル固体半導体ヘテロ構造及びその製造方法
JP2016205042A JP2017028318A (ja) 2007-09-18 2016-10-19 エピタキシャル固体半導体ヘテロ構造及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0757652A FR2921200B1 (fr) 2007-09-18 2007-09-18 Heterostructures semi-conductrices monolithiques epitaxiees et leur procede de fabrication

Publications (2)

Publication Number Publication Date
FR2921200A1 FR2921200A1 (fr) 2009-03-20
FR2921200B1 true FR2921200B1 (fr) 2009-12-18

Family

ID=39434296

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0757652A Expired - Fee Related FR2921200B1 (fr) 2007-09-18 2007-09-18 Heterostructures semi-conductrices monolithiques epitaxiees et leur procede de fabrication

Country Status (5)

Country Link
US (1) US8389995B2 (fr)
EP (1) EP2188830A1 (fr)
JP (3) JP2010539723A (fr)
FR (1) FR2921200B1 (fr)
WO (1) WO2009047448A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5585137B2 (ja) * 2010-03-17 2014-09-10 行男 渡部 金属酸化物を含むへテロ構造の作製法及び該金属酸化物の製造法
US8846506B2 (en) * 2012-04-26 2014-09-30 The University Of North Carolina At Charlotte Enhanced electron mobility at the interface between Gd2O3(100)/N-Si(100)
GB2517697A (en) 2013-08-27 2015-03-04 Ibm Compound semiconductor structure
FR3069705A1 (fr) 2017-07-28 2019-02-01 Centre National De La Recherche Scientifique Cellule photovoltaique tandem
CN113284839A (zh) * 2021-05-21 2021-08-20 中国科学院上海微***与信息技术研究所 一种钻石晶体的异质键合方法及异质结构

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* Cited by examiner, † Cited by third party
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JP2649928B2 (ja) * 1988-01-11 1997-09-03 富士通株式会社 半導体ウエハの製造方法
US5323023A (en) * 1992-12-02 1994-06-21 Xerox Corporation Epitaxial magnesium oxide as a buffer layer on (111) tetrahedral semiconductors
US6608327B1 (en) * 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
US6427066B1 (en) * 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
US6410941B1 (en) * 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
WO2002045140A2 (fr) * 2000-11-22 2002-06-06 Motorola, Inc. Structures semi-conductrices a substrat flexible
US20020096683A1 (en) * 2001-01-19 2002-07-25 Motorola, Inc. Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate
US20020153524A1 (en) * 2001-04-19 2002-10-24 Motorola Inc. Structure and method for fabricating semiconductor structures and devices utilizing perovskite stacks
US20020158265A1 (en) * 2001-04-26 2002-10-31 Motorola, Inc. Structure and method for fabricating high contrast reflective mirrors
US20020163024A1 (en) * 2001-05-04 2002-11-07 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices ultilizing lateral epitaxial overgrowth of a monocrystallaline material layer on a compliant substrate
US7160388B2 (en) * 2001-06-06 2007-01-09 Nichia Corporation Process and apparatus for obtaining bulk monocrystalline gallium-containing nitride
US20030015134A1 (en) * 2001-07-18 2003-01-23 Motorola, Inc. Semiconductor structure for edge mounting applications and process for fabrication
US6472276B1 (en) * 2001-07-20 2002-10-29 Motorola, Inc. Using silicate layers for composite semiconductor
US6472694B1 (en) * 2001-07-23 2002-10-29 Motorola, Inc. Microprocessor structure having a compound semiconductor layer
CN1555570A (zh) * 2001-07-31 2004-12-15 ����ŵ˹�ݴ�ѧ����ίԱ�� 量子点与量子阱耦合的半导体器件及其制造方法
US20030024471A1 (en) * 2001-08-06 2003-02-06 Motorola, Inc. Fabrication of semiconductor structures and devices forms by utilizing laser assisted deposition
US6462360B1 (en) * 2001-08-06 2002-10-08 Motorola, Inc. Integrated gallium arsenide communications systems
JP4041877B2 (ja) * 2001-12-27 2008-02-06 国立大学法人 筑波大学 半導体装置
US6872252B2 (en) * 2002-03-06 2005-03-29 Agilent Technologies, Inc. Lead-based perovskite buffer for forming indium phosphide on silicon
JP2003282439A (ja) * 2002-03-27 2003-10-03 Seiko Epson Corp デバイス用基板およびデバイス用基板の製造方法
US6916717B2 (en) * 2002-05-03 2005-07-12 Motorola, Inc. Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate
JP2003332242A (ja) * 2002-05-10 2003-11-21 Makoto Ishida 半導体基板およびその製造方法
JP2003327497A (ja) * 2002-05-13 2003-11-19 Sumitomo Electric Ind Ltd ＧａＮ単結晶基板、窒化物系半導体エピタキシャル基板、窒化物系半導体素子及びその製造方法
WO2004051725A1 (fr) * 2002-12-03 2004-06-17 Nikko Materials Co., Ltd. Procede de croissance epitaxiale et substrat destine a la croissance epitaxiale
JP2004317886A (ja) * 2003-04-17 2004-11-11 Matsushita Electric Ind Co Ltd 光スイッチとそれを用いた光磁気回路、ならびに光磁気回路の製造方法
US7968273B2 (en) * 2004-06-08 2011-06-28 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
JP4707475B2 (ja) * 2005-06-17 2011-06-22 国立大学法人 東京大学 化合物半導体結晶の成長方法、その成長方法を用いて成長した化合物半導体結晶の層を備えた半導体装置及び半導体基板
KR100753152B1 (ko) * 2005-08-12 2007-08-30 삼성전자주식회사 질화물계 발광소자 및 그 제조방법
JP4809684B2 (ja) * 2006-01-31 2011-11-09 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
US20100289063A1 (en) 2010-11-18
US8389995B2 (en) 2013-03-05
FR2921200A1 (fr) 2009-03-20
JP2015008293A (ja) 2015-01-15
JP2010539723A (ja) 2010-12-16
JP2017028318A (ja) 2017-02-02
EP2188830A1 (fr) 2010-05-26
JP6062887B2 (ja) 2017-01-18
WO2009047448A1 (fr) 2009-04-16

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