FR2842649B1 - Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support - Google Patents
Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un supportInfo
- Publication number
- FR2842649B1 FR2842649B1 FR0209020A FR0209020A FR2842649B1 FR 2842649 B1 FR2842649 B1 FR 2842649B1 FR 0209020 A FR0209020 A FR 0209020A FR 0209020 A FR0209020 A FR 0209020A FR 2842649 B1 FR2842649 B1 FR 2842649B1
- Authority
- FR
- France
- Prior art keywords
- increasing
- support
- area
- useful layer
- material reflected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/21—Circular sheet or circular blank
- Y10T428/219—Edge structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0209020A FR2842649B1 (fr) | 2002-07-17 | 2002-07-17 | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
AT03794837T ATE465513T1 (de) | 2002-07-17 | 2003-07-16 | Verfahren zur vergrösserung der fläche einer nutzschicht eines auf eine stütze übertragenen materials |
DE60332241T DE60332241D1 (de) | 2002-07-17 | 2003-07-16 | Verfahren zur vergrösserung der fläche einer nutzschicht eines auf eine stütze übertragenen materials |
US10/619,596 US7294557B2 (en) | 2002-07-17 | 2003-07-16 | Method of increasing the area of a useful layer of material transferred onto a support |
EP03794837A EP1522098B1 (fr) | 2002-07-17 | 2003-07-16 | Procede permettant d'augmenter la surface d'une couche utile d'un materiau apres transfert sur un support |
JP2004535050A JP4652053B2 (ja) | 2002-07-17 | 2003-07-16 | 支持基板へ転送される有用な材料層の面積を増加させる方法 |
PCT/EP2003/007856 WO2004025722A1 (fr) | 2002-07-17 | 2003-07-16 | Procede permettant d'augmenter la surface d'une couche utile d'un materiau apres transfert sur un support |
TW092119345A TWI266381B (en) | 2002-07-17 | 2003-07-16 | A method of increasing the area of a useful layer of material transferred onto a support |
AU2003246719A AU2003246719A1 (en) | 2002-07-17 | 2003-07-16 | A method of increasing the area of a useful layer of material transferred onto a support |
US11/858,164 US7956441B2 (en) | 2002-07-17 | 2007-09-20 | Method of increasing the area of a useful layer of material transferred onto a support |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0209020A FR2842649B1 (fr) | 2002-07-17 | 2002-07-17 | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2842649A1 FR2842649A1 (fr) | 2004-01-23 |
FR2842649B1 true FR2842649B1 (fr) | 2005-06-24 |
Family
ID=29797485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0209020A Expired - Fee Related FR2842649B1 (fr) | 2002-07-17 | 2002-07-17 | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
Country Status (2)
Country | Link |
---|---|
US (2) | US7294557B2 (fr) |
FR (1) | FR2842649B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4838504B2 (ja) * | 2004-09-08 | 2011-12-14 | キヤノン株式会社 | 半導体装置の製造方法 |
FR2920912B1 (fr) * | 2007-09-12 | 2010-08-27 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure par transfert de couche |
US7757200B2 (en) * | 2007-11-16 | 2010-07-13 | International Business Machines Corporation | Structure of an apparatus for programming an electronically programmable semiconductor fuse |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0636413B2 (ja) * | 1990-03-29 | 1994-05-11 | 信越半導体株式会社 | 半導体素子形成用基板の製造方法 |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP2825048B2 (ja) * | 1992-08-10 | 1998-11-18 | 信越半導体株式会社 | 半導体シリコン基板 |
US5597410A (en) * | 1994-09-15 | 1997-01-28 | Yen; Yung C. | Method to make a SOI wafer for IC manufacturing |
JPH1093122A (ja) | 1996-09-10 | 1998-04-10 | Nippon Telegr & Teleph Corp <Ntt> | 薄膜太陽電池の製造方法 |
FR2774510B1 (fr) * | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
US6664169B1 (en) * | 1999-06-08 | 2003-12-16 | Canon Kabushiki Kaisha | Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus |
EP1189266B1 (fr) * | 2000-03-29 | 2017-04-05 | Shin-Etsu Handotai Co., Ltd. | Procede d'obtention de tranches de silicium ou de soi et tranches ainsi obtenues |
JP4846915B2 (ja) * | 2000-03-29 | 2011-12-28 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP2001284622A (ja) * | 2000-03-31 | 2001-10-12 | Canon Inc | 半導体部材の製造方法及び太陽電池の製造方法 |
FR2842646B1 (fr) * | 2002-07-17 | 2005-06-24 | Soitec Silicon On Insulator | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
-
2002
- 2002-07-17 FR FR0209020A patent/FR2842649B1/fr not_active Expired - Fee Related
-
2003
- 2003-07-16 US US10/619,596 patent/US7294557B2/en not_active Expired - Lifetime
-
2007
- 2007-09-20 US US11/858,164 patent/US7956441B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20040082148A1 (en) | 2004-04-29 |
US20080006909A1 (en) | 2008-01-10 |
US7956441B2 (en) | 2011-06-07 |
US7294557B2 (en) | 2007-11-13 |
FR2842649A1 (fr) | 2004-01-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20120330 |