FR2842646B1 - Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support - Google Patents

Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support

Info

Publication number
FR2842646B1
FR2842646B1 FR0209017A FR0209017A FR2842646B1 FR 2842646 B1 FR2842646 B1 FR 2842646B1 FR 0209017 A FR0209017 A FR 0209017A FR 0209017 A FR0209017 A FR 0209017A FR 2842646 B1 FR2842646 B1 FR 2842646B1
Authority
FR
France
Prior art keywords
substrate
outline
support
useful layer
chamfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0209017A
Other languages
English (en)
Other versions
FR2842646A1 (fr
Inventor
Christophe Maleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0209017A priority Critical patent/FR2842646B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to EP03763892A priority patent/EP1540723B1/fr
Priority to DE60335388T priority patent/DE60335388D1/de
Priority to TW092119344A priority patent/TWI283911B/zh
Priority to PCT/EP2003/007855 priority patent/WO2004008527A1/fr
Priority to AU2003254543A priority patent/AU2003254543A1/en
Priority to AT03763892T priority patent/ATE492028T1/de
Priority to JP2005505074A priority patent/JP4531694B2/ja
Priority to US10/619,446 priority patent/US7048867B2/en
Publication of FR2842646A1 publication Critical patent/FR2842646A1/fr
Application granted granted Critical
Publication of FR2842646B1 publication Critical patent/FR2842646B1/fr
Priority to US11/348,299 priority patent/US7452584B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/15Sheet, web, or layer weakened to permit separation through thickness
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/21Circular sheet or circular blank
    • Y10T428/219Edge structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Silicon Compounds (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
FR0209017A 2002-07-17 2002-07-17 Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support Expired - Lifetime FR2842646B1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
FR0209017A FR2842646B1 (fr) 2002-07-17 2002-07-17 Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support
US10/619,446 US7048867B2 (en) 2002-07-17 2003-07-16 Method of increasing the area of a useful layer of material transferred onto a support
TW092119344A TWI283911B (en) 2002-07-17 2003-07-16 A method of increasing the area of a useful layer of material transferred onto a support
PCT/EP2003/007855 WO2004008527A1 (fr) 2002-07-17 2003-07-16 Procede permettant d'accroitre l'aire d'une couche utile d'un materiau transfere sur un support
AU2003254543A AU2003254543A1 (en) 2002-07-17 2003-07-16 A method of increasing the area of a useful layer of material transferred onto a support
AT03763892T ATE492028T1 (de) 2002-07-17 2003-07-16 Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird
EP03763892A EP1540723B1 (fr) 2002-07-17 2003-07-16 Procede permettant d'accroitre l'aire d'une couche utile d'un materiau transfere sur un support
DE60335388T DE60335388D1 (de) 2002-07-17 2003-07-16 Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird
JP2005505074A JP4531694B2 (ja) 2002-07-17 2003-07-16 支持体に転移する材料から成る有用な層の面積を拡大する方法
US11/348,299 US7452584B2 (en) 2002-07-17 2006-02-07 Method of increasing the area of a useful layer of material transferred onto a support

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0209017A FR2842646B1 (fr) 2002-07-17 2002-07-17 Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support

Publications (2)

Publication Number Publication Date
FR2842646A1 FR2842646A1 (fr) 2004-01-23
FR2842646B1 true FR2842646B1 (fr) 2005-06-24

Family

ID=29797482

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0209017A Expired - Lifetime FR2842646B1 (fr) 2002-07-17 2002-07-17 Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support

Country Status (4)

Country Link
US (2) US7048867B2 (fr)
AT (1) ATE492028T1 (fr)
DE (1) DE60335388D1 (fr)
FR (1) FR2842646B1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2842649B1 (fr) * 2002-07-17 2005-06-24 Soitec Silicon On Insulator Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
JP4525353B2 (ja) * 2005-01-07 2010-08-18 住友電気工業株式会社 Iii族窒化物基板の製造方法
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8330245B2 (en) * 2010-02-25 2012-12-11 Memc Electronic Materials, Inc. Semiconductor wafers with reduced roll-off and bonded and unbonded SOI structures produced from same
US9156705B2 (en) 2010-12-23 2015-10-13 Sunedison, Inc. Production of polycrystalline silicon by the thermal decomposition of dichlorosilane in a fluidized bed reactor

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0636413B2 (ja) * 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2825048B2 (ja) 1992-08-10 1998-11-18 信越半導体株式会社 半導体シリコン基板
US5597410A (en) * 1994-09-15 1997-01-28 Yen; Yung C. Method to make a SOI wafer for IC manufacturing
US6113721A (en) * 1995-01-03 2000-09-05 Motorola, Inc. Method of bonding a semiconductor wafer
JPH1093122A (ja) 1996-09-10 1998-04-10 Nippon Telegr & Teleph Corp <Ntt> 薄膜太陽電池の製造方法
FR2774510B1 (fr) * 1998-02-02 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats, notamment semi-conducteurs
US6664169B1 (en) * 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
EP1189266B1 (fr) * 2000-03-29 2017-04-05 Shin-Etsu Handotai Co., Ltd. Procede d'obtention de tranches de silicium ou de soi et tranches ainsi obtenues
JP4846915B2 (ja) 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法
JP2001284622A (ja) 2000-03-31 2001-10-12 Canon Inc 半導体部材の製造方法及び太陽電池の製造方法
JP4628580B2 (ja) * 2001-04-18 2011-02-09 信越半導体株式会社 貼り合せ基板の製造方法
US20040224482A1 (en) * 2001-12-20 2004-11-11 Kub Francis J. Method for transferring thin film layer material to a flexible substrate using a hydrogen ion splitting technique

Also Published As

Publication number Publication date
ATE492028T1 (de) 2011-01-15
US7452584B2 (en) 2008-11-18
US20040081790A1 (en) 2004-04-29
US7048867B2 (en) 2006-05-23
DE60335388D1 (de) 2011-01-27
US20060124584A1 (en) 2006-06-15
FR2842646A1 (fr) 2004-01-23

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