FR2814555B1 - Systeme et procede de gestion memoire de coherence de donnees et reseau multiprocesseur associe - Google Patents

Systeme et procede de gestion memoire de coherence de donnees et reseau multiprocesseur associe

Info

Publication number
FR2814555B1
FR2814555B1 FR0012152A FR0012152A FR2814555B1 FR 2814555 B1 FR2814555 B1 FR 2814555B1 FR 0012152 A FR0012152 A FR 0012152A FR 0012152 A FR0012152 A FR 0012152A FR 2814555 B1 FR2814555 B1 FR 2814555B1
Authority
FR
France
Prior art keywords
memory management
data coherence
multiprocessor network
multiprocessor
network
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0012152A
Other languages
English (en)
Other versions
FR2814555A1 (fr
Inventor
Jean Marie Steyer
Jean Jacques Metayer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technicolor SA
Original Assignee
Thomson Multimedia SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Multimedia SA filed Critical Thomson Multimedia SA
Priority to FR0012152A priority Critical patent/FR2814555B1/fr
Priority to US09/956,422 priority patent/US6757786B2/en
Priority to EP01122417A priority patent/EP1191447A1/fr
Priority to JP2001288606A priority patent/JP2002157164A/ja
Priority to CNB011422297A priority patent/CN1193296C/zh
Publication of FR2814555A1 publication Critical patent/FR2814555A1/fr
Application granted granted Critical
Publication of FR2814555B1 publication Critical patent/FR2814555B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
FR0012152A 2000-09-25 2000-09-25 Systeme et procede de gestion memoire de coherence de donnees et reseau multiprocesseur associe Expired - Fee Related FR2814555B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR0012152A FR2814555B1 (fr) 2000-09-25 2000-09-25 Systeme et procede de gestion memoire de coherence de donnees et reseau multiprocesseur associe
US09/956,422 US6757786B2 (en) 2000-09-25 2001-09-19 Data consistency memory management system and method and associated multiprocessor network
EP01122417A EP1191447A1 (fr) 2000-09-25 2001-09-20 Système et procédé de gestion mémoire de cohérence de données et réseau multiprocesseur associé
JP2001288606A JP2002157164A (ja) 2000-09-25 2001-09-21 データ一貫性メモリ管理システム及び方法及び関連するマルチプロセッサネットワーク
CNB011422297A CN1193296C (zh) 2000-09-25 2001-09-25 数据内存管理***和方法以及相关多处理器网络

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0012152A FR2814555B1 (fr) 2000-09-25 2000-09-25 Systeme et procede de gestion memoire de coherence de donnees et reseau multiprocesseur associe

Publications (2)

Publication Number Publication Date
FR2814555A1 FR2814555A1 (fr) 2002-03-29
FR2814555B1 true FR2814555B1 (fr) 2003-02-28

Family

ID=8854626

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0012152A Expired - Fee Related FR2814555B1 (fr) 2000-09-25 2000-09-25 Systeme et procede de gestion memoire de coherence de donnees et reseau multiprocesseur associe

Country Status (5)

Country Link
US (1) US6757786B2 (fr)
EP (1) EP1191447A1 (fr)
JP (1) JP2002157164A (fr)
CN (1) CN1193296C (fr)
FR (1) FR2814555B1 (fr)

Families Citing this family (21)

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Publication number Priority date Publication date Assignee Title
US7133972B2 (en) * 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7272664B2 (en) * 2002-12-05 2007-09-18 International Business Machines Corporation Cross partition sharing of state information
CN100365593C (zh) * 2003-06-16 2008-01-30 华为技术有限公司 计算机***的内存管理方法
US20050041510A1 (en) * 2003-08-19 2005-02-24 Jean Khawand Method and apparatus for providing interprocessor communications using shared memory
KR20070019940A (ko) 2003-09-02 2007-02-16 서프 테크놀러지, 인코포레이티드 위성 위치결정 시스템 수신기에 대한 제어 및 특징들
US7822105B2 (en) * 2003-09-02 2010-10-26 Sirf Technology, Inc. Cross-correlation removal of carrier wave jamming signals
US7047364B2 (en) * 2003-12-29 2006-05-16 Intel Corporation Cache memory management
JP2006172142A (ja) * 2004-12-16 2006-06-29 Matsushita Electric Ind Co Ltd マルチプロセッサシステム
US8346740B2 (en) 2005-07-22 2013-01-01 Hewlett-Packard Development Company, L.P. File cache management system
JP4419943B2 (ja) 2005-11-11 2010-02-24 株式会社デンソー Ｃｐｕ間データ転送装置
CN100486178C (zh) * 2006-12-06 2009-05-06 中国科学院计算技术研究所 一种远程内存共享***及其实现方法
JP2009104300A (ja) * 2007-10-22 2009-05-14 Denso Corp データ処理装置及びプログラム
CN100489815C (zh) * 2007-10-25 2009-05-20 中国科学院计算技术研究所 一种内存共享的***和装置及方法
US7991963B2 (en) * 2007-12-31 2011-08-02 Intel Corporation In-memory, in-page directory cache coherency scheme
CN102722401B (zh) * 2012-04-25 2014-07-09 华中科技大学 一种硬件事务内存***中的伪相联多版本数据管理方法
US9135172B2 (en) * 2012-08-02 2015-09-15 Qualcomm Incorporated Cache data migration in a multicore processing system
US9116738B2 (en) 2012-11-13 2015-08-25 International Business Machines Corporation Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system
CN103136110B (zh) 2013-02-18 2016-03-30 华为技术有限公司 内存管理方法、内存管理装置及numa***
CN104778098A (zh) * 2015-04-09 2015-07-15 浪潮电子信息产业股份有限公司 一种内存镜像的方法及***、一种内存监控器
FR3078176B1 (fr) * 2018-02-19 2020-02-28 IFP Energies Nouvelles Systeme et procede de prediction d'un phenomene physique et/ou chimique au moyen d'un segment de memoire partage

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761727A (en) * 1996-04-02 1998-06-02 United Microelectronics Corporation Control apparatus for a memory architecture using dedicated and shared memory segments
US5901326A (en) * 1996-11-26 1999-05-04 International Business Machines Corporation Memory bus address snooper logic for determining memory activity without performing memory accesses
US6115761A (en) * 1997-05-30 2000-09-05 Lsi Logic Corporation First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment
US6542926B2 (en) * 1998-06-10 2003-04-01 Compaq Information Technologies Group, L.P. Software partitioned multi-processor system with flexible resource sharing levels
GB2331379A (en) * 1997-11-13 1999-05-19 Advanced Telecommunications Mo Controlling access to a shared memory by dual mapping
US6081783A (en) * 1997-11-14 2000-06-27 Cirrus Logic, Inc. Dual processor digital audio decoder with shared memory data transfer and task partitioning for decompressing compressed audio data, and systems and methods using the same
US6385704B1 (en) * 1997-11-14 2002-05-07 Cirrus Logic, Inc. Accessing shared memory using token bit held by default by a single processor
US6314501B1 (en) * 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6295571B1 (en) * 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems

Also Published As

Publication number Publication date
EP1191447A1 (fr) 2002-03-27
US6757786B2 (en) 2004-06-29
US20020038408A1 (en) 2002-03-28
CN1347034A (zh) 2002-05-01
JP2002157164A (ja) 2002-05-31
CN1193296C (zh) 2005-03-16
FR2814555A1 (fr) 2002-03-29

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Effective date: 20110531