FR2802318B1 - Procede d'acces a des donnees dans un systeme en reseau et systeme en reseau - Google Patents

Procede d'acces a des donnees dans un systeme en reseau et systeme en reseau

Info

Publication number
FR2802318B1
FR2802318B1 FR0016056A FR0016056A FR2802318B1 FR 2802318 B1 FR2802318 B1 FR 2802318B1 FR 0016056 A FR0016056 A FR 0016056A FR 0016056 A FR0016056 A FR 0016056A FR 2802318 B1 FR2802318 B1 FR 2802318B1
Authority
FR
France
Prior art keywords
network system
accessing data
network
accessing
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0016056A
Other languages
English (en)
Other versions
FR2802318A1 (fr
Inventor
Hidetoshi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2802318A1 publication Critical patent/FR2802318A1/fr
Application granted granted Critical
Publication of FR2802318B1 publication Critical patent/FR2802318B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR0016056A 1999-12-09 2000-12-11 Procede d'acces a des donnees dans un systeme en reseau et systeme en reseau Expired - Fee Related FR2802318B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34980999A JP2001167077A (ja) 1999-12-09 1999-12-09 ネットワークシステムにおけるデータアクセス方法、ネットワークシステムおよび記録媒体

Publications (2)

Publication Number Publication Date
FR2802318A1 FR2802318A1 (fr) 2001-06-15
FR2802318B1 true FR2802318B1 (fr) 2006-09-22

Family

ID=18406272

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0016056A Expired - Fee Related FR2802318B1 (fr) 1999-12-09 2000-12-11 Procede d'acces a des donnees dans un systeme en reseau et systeme en reseau

Country Status (3)

Country Link
US (1) US7093078B2 (fr)
JP (1) JP2001167077A (fr)
FR (1) FR2802318B1 (fr)

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US7331010B2 (en) 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
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US7356737B2 (en) * 2004-10-29 2008-04-08 International Business Machines Corporation System, method and storage medium for testing a memory module
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JP4362454B2 (ja) * 2005-04-07 2009-11-11 富士通株式会社 キャッシュコヒーレンス管理装置およびキャッシュコヒーレンス管理方法
US7478259B2 (en) 2005-10-31 2009-01-13 International Business Machines Corporation System, method and storage medium for deriving clocks in a memory system
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
JP4848771B2 (ja) * 2006-01-04 2011-12-28 株式会社日立製作所 キャッシュ一貫性制御方法およびチップセットおよびマルチプロセッサシステム
US7640386B2 (en) * 2006-05-24 2009-12-29 International Business Machines Corporation Systems and methods for providing memory modules with multiple hub devices
US7493439B2 (en) * 2006-08-01 2009-02-17 International Business Machines Corporation Systems and methods for providing performance monitoring in a memory system
US7669086B2 (en) * 2006-08-02 2010-02-23 International Business Machines Corporation Systems and methods for providing collision detection in a memory system
US7587559B2 (en) * 2006-08-10 2009-09-08 International Business Machines Corporation Systems and methods for memory module power management
JP4829038B2 (ja) * 2006-08-17 2011-11-30 富士通株式会社 マルチプロセッサシステム
US7870459B2 (en) * 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US7721140B2 (en) 2007-01-02 2010-05-18 International Business Machines Corporation Systems and methods for improving serviceability of a memory system
US7606988B2 (en) * 2007-01-29 2009-10-20 International Business Machines Corporation Systems and methods for providing a dynamic memory bank page policy
US7603526B2 (en) * 2007-01-29 2009-10-13 International Business Machines Corporation Systems and methods for providing dynamic memory pre-fetch
JP5163220B2 (ja) 2008-03-26 2013-03-13 富士通株式会社 キャッシュ制御装置、情報処理装置
KR101426187B1 (ko) 2010-05-27 2014-07-31 후지쯔 가부시끼가이샤 메모리 시스템 및 메모리 인터페이스 장치
CN102947817B (zh) * 2010-06-23 2016-03-02 富士通株式会社 通信装置、通信方法以及通信程序
US9727879B2 (en) * 2011-03-30 2017-08-08 Nokia Technologies Oy Method and apparatus for providing tag-based content installation
US20130086328A1 (en) * 2011-06-13 2013-04-04 Paneve, Llc General Purpose Digital Data Processor, Systems and Methods
CN105706068B (zh) * 2013-04-30 2019-08-23 慧与发展有限责任合伙企业 路由存储器流量和i/o流量的存储器网络

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Also Published As

Publication number Publication date
JP2001167077A (ja) 2001-06-22
US20010003839A1 (en) 2001-06-14
US7093078B2 (en) 2006-08-15
FR2802318A1 (fr) 2001-06-15

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Legal Events

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ST Notification of lapse

Effective date: 20081020