FR2808920B1 - Procede de protection de puces de circuit integre - Google Patents
Procede de protection de puces de circuit integreInfo
- Publication number
- FR2808920B1 FR2808920B1 FR0005959A FR0005959A FR2808920B1 FR 2808920 B1 FR2808920 B1 FR 2808920B1 FR 0005959 A FR0005959 A FR 0005959A FR 0005959 A FR0005959 A FR 0005959A FR 2808920 B1 FR2808920 B1 FR 2808920B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- circuit chip
- protection method
- chip protection
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0005959A FR2808920B1 (fr) | 2000-05-10 | 2000-05-10 | Procede de protection de puces de circuit integre |
AU2001258505A AU2001258505A1 (en) | 2000-05-10 | 2001-05-07 | Thin layer chip insulation for conductive polymer connection |
PCT/FR2001/001384 WO2001086719A1 (fr) | 2000-05-10 | 2001-05-07 | Isolation de puces par couche mince pour connexion par polymere conducteur |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0005959A FR2808920B1 (fr) | 2000-05-10 | 2000-05-10 | Procede de protection de puces de circuit integre |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2808920A1 FR2808920A1 (fr) | 2001-11-16 |
FR2808920B1 true FR2808920B1 (fr) | 2003-10-03 |
Family
ID=8850067
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0005959A Expired - Fee Related FR2808920B1 (fr) | 2000-05-10 | 2000-05-10 | Procede de protection de puces de circuit integre |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU2001258505A1 (fr) |
FR (1) | FR2808920B1 (fr) |
WO (1) | WO2001086719A1 (fr) |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2348323A1 (de) * | 1973-09-26 | 1975-04-03 | Licentia Gmbh | Integrierte festkoerperschaltung mit einer vielzahl von bauelementen in einem gemeinsamen halbleiterkoerper |
JPS5272572A (en) * | 1975-12-15 | 1977-06-17 | Seiko Epson Corp | Semiconductor device |
JPS60165779A (ja) * | 1984-02-07 | 1985-08-28 | Rohm Co Ltd | 半導体レ−ザのチツプ製造方法 |
JPS6116592A (ja) * | 1984-07-02 | 1986-01-24 | Rohm Co Ltd | 半導体レ−ザのチツプ製造方法 |
JPS61172361A (ja) * | 1985-01-28 | 1986-08-04 | Shindo Denshi Kogyo Kk | テ−プキヤリアの製造方法 |
JPH0529379A (ja) * | 1991-07-25 | 1993-02-05 | Mitsubishi Electric Corp | 半導体装置およびそれの製造方法 |
US5744382A (en) * | 1992-05-13 | 1998-04-28 | Matsushita Electric Industrial Co., Ltd. | Method of packaging electronic chip component and method of bonding of electrode thereof |
US5693565A (en) * | 1996-07-15 | 1997-12-02 | Dow Corning Corporation | Semiconductor chips suitable for known good die testing |
FR2761498B1 (fr) * | 1997-03-27 | 1999-06-18 | Gemplus Card Int | Module electronique et son procede de fabrication et carte a puce comportant un tel module |
-
2000
- 2000-05-10 FR FR0005959A patent/FR2808920B1/fr not_active Expired - Fee Related
-
2001
- 2001-05-07 AU AU2001258505A patent/AU2001258505A1/en not_active Abandoned
- 2001-05-07 WO PCT/FR2001/001384 patent/WO2001086719A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
FR2808920A1 (fr) | 2001-11-16 |
AU2001258505A1 (en) | 2001-11-20 |
WO2001086719A1 (fr) | 2001-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20100129 |