FR2795554B1 - Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs - Google Patents
Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteursInfo
- Publication number
- FR2795554B1 FR2795554B1 FR9908248A FR9908248A FR2795554B1 FR 2795554 B1 FR2795554 B1 FR 2795554B1 FR 9908248 A FR9908248 A FR 9908248A FR 9908248 A FR9908248 A FR 9908248A FR 2795554 B1 FR2795554 B1 FR 2795554B1
- Authority
- FR
- France
- Prior art keywords
- semiconductor devices
- manufacturing semiconductor
- engraving method
- holes lateral
- lateral engraving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/515—Insulating materials associated therewith with cavities, e.g. containing a gas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9908248A FR2795554B1 (fr) | 1999-06-28 | 1999-06-28 | Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs |
US10/019,340 US6727186B1 (en) | 1999-06-28 | 2000-06-27 | Method for lateral etching with holes for making semiconductor devices |
EP00946027A EP1192653A1 (fr) | 1999-06-28 | 2000-06-27 | Procede de gravure laterale par trous pour fabriquer des dispositifs semi-conducteurs |
PCT/FR2000/001796 WO2001001477A1 (fr) | 1999-06-28 | 2000-06-27 | Procede de gravure laterale par trous pour fabriquer des dispositifs semi-conducteurs |
TW089112696A TW451334B (en) | 1999-06-28 | 2000-09-11 | Method for lateral etching with holes for making semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9908248A FR2795554B1 (fr) | 1999-06-28 | 1999-06-28 | Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2795554A1 FR2795554A1 (fr) | 2000-12-29 |
FR2795554B1 true FR2795554B1 (fr) | 2003-08-22 |
Family
ID=9547389
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9908248A Expired - Fee Related FR2795554B1 (fr) | 1999-06-28 | 1999-06-28 | Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs |
Country Status (5)
Country | Link |
---|---|
US (1) | US6727186B1 (fr) |
EP (1) | EP1192653A1 (fr) |
FR (1) | FR2795554B1 (fr) |
TW (1) | TW451334B (fr) |
WO (1) | WO2001001477A1 (fr) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2812764B1 (fr) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
FR2821483B1 (fr) * | 2001-02-28 | 2004-07-09 | St Microelectronics Sa | Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant |
ATE415703T1 (de) * | 2002-12-20 | 2008-12-15 | Soitec Silicon On Insulator | Herstellung von hohlräumen in einer siliziumscheibe |
FR2849269B1 (fr) * | 2002-12-20 | 2005-07-29 | Soitec Silicon On Insulator | Procede de realisation de cavites dans une plaque de silicium |
US7078298B2 (en) * | 2003-05-20 | 2006-07-18 | Sharp Laboratories Of America, Inc. | Silicon-on-nothing fabrication process |
GB2412009B (en) * | 2004-03-11 | 2006-01-25 | Toshiba Research Europ Limited | A semiconductor device and method of its manufacture |
US7262084B2 (en) * | 2004-04-15 | 2007-08-28 | International Business Machines Corporation | Methods for manufacturing a finFET using a conventional wafer and apparatus manufactured therefrom |
JP2005354024A (ja) * | 2004-05-11 | 2005-12-22 | Seiko Epson Corp | 半導体基板の製造方法および半導体装置の製造方法 |
FR2875947B1 (fr) * | 2004-09-30 | 2007-09-07 | Tracit Technologies | Nouvelle structure pour microelectronique et microsysteme et procede de realisation |
FR2876220B1 (fr) * | 2004-10-06 | 2007-09-28 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
FR2879820B1 (fr) * | 2004-12-16 | 2009-01-16 | Commissariat Energie Atomique | Modulateur a jonction capacitive, jonction capacitive et son procede de realisation |
JP2006278674A (ja) * | 2005-03-29 | 2006-10-12 | Nec Electronics Corp | 電界効果トランジスタとその製造方法、及び半導体装置 |
FR2884648B1 (fr) * | 2005-04-13 | 2007-09-07 | Commissariat Energie Atomique | Structure et procede de realisation d'un dispositif microelectronique dote d'un ou plusieurs fils quantiques aptes a former un canal ou plusieurs canaux de transistors |
FR2897982B1 (fr) | 2006-02-27 | 2008-07-11 | Tracit Technologies Sa | Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat |
WO2008087576A1 (fr) * | 2007-01-16 | 2008-07-24 | Nxp B.V. | Traitement d'un substrat semi-conducteur |
FR2923646A1 (fr) * | 2007-11-09 | 2009-05-15 | Commissariat Energie Atomique | Cellule memoire sram dotee de transistors a structure multi-canaux verticale |
DE102008011480B4 (de) * | 2008-02-27 | 2010-09-09 | Siemens Aktiengesellschaft | Trennsäulen-Einheit für einen Gaschromatograph und Verfahren zu ihrer Befüllung mit Trennpartikeln |
US8106468B2 (en) * | 2008-06-20 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for fabricating silicon-on-nothing MOSFETs |
DE102008040597A1 (de) * | 2008-07-22 | 2010-01-28 | Robert Bosch Gmbh | Mikromechanisches Bauelement mit Rückvolumen |
US8159029B2 (en) * | 2008-10-22 | 2012-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage device having reduced on-state resistance |
US9685456B2 (en) | 2015-09-04 | 2017-06-20 | Stmicroelectronics, Inc. | Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method |
DE102016119799B4 (de) * | 2016-10-18 | 2020-08-06 | Infineon Technologies Ag | Integrierte schaltung, die einen vergrabenen hohlraum enthält, und herstellungsverfahren |
JP6817895B2 (ja) * | 2017-05-24 | 2021-01-20 | 株式会社東芝 | 半導体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5153813A (en) * | 1991-10-31 | 1992-10-06 | International Business Machines Corporation | High area capacitor formation using dry etching |
JPH06120490A (ja) * | 1992-10-06 | 1994-04-28 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR0138317B1 (ko) * | 1994-08-31 | 1998-04-28 | 김광호 | 반도체장치 커패시터 제조방법 |
US5622882A (en) * | 1994-12-30 | 1997-04-22 | Lsi Logic Corporation | Method of making a CMOS dynamic random-access memory (DRAM) |
-
1999
- 1999-06-28 FR FR9908248A patent/FR2795554B1/fr not_active Expired - Fee Related
-
2000
- 2000-06-27 WO PCT/FR2000/001796 patent/WO2001001477A1/fr not_active Application Discontinuation
- 2000-06-27 EP EP00946027A patent/EP1192653A1/fr not_active Withdrawn
- 2000-06-27 US US10/019,340 patent/US6727186B1/en not_active Expired - Fee Related
- 2000-09-11 TW TW089112696A patent/TW451334B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO2001001477A1 (fr) | 2001-01-04 |
FR2795554A1 (fr) | 2000-12-29 |
US6727186B1 (en) | 2004-04-27 |
EP1192653A1 (fr) | 2002-04-03 |
TW451334B (en) | 2001-08-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20080229 |