FR2779255B1 - METHOD FOR MANUFACTURING A PORTABLE ELECTRONIC DEVICE COMPRISING AT LEAST ONE INTEGRATED CIRCUIT CHIP - Google Patents

METHOD FOR MANUFACTURING A PORTABLE ELECTRONIC DEVICE COMPRISING AT LEAST ONE INTEGRATED CIRCUIT CHIP

Info

Publication number
FR2779255B1
FR2779255B1 FR9806684A FR9806684A FR2779255B1 FR 2779255 B1 FR2779255 B1 FR 2779255B1 FR 9806684 A FR9806684 A FR 9806684A FR 9806684 A FR9806684 A FR 9806684A FR 2779255 B1 FR2779255 B1 FR 2779255B1
Authority
FR
France
Prior art keywords
manufacturing
electronic device
integrated circuit
portable electronic
circuit chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9806684A
Other languages
French (fr)
Other versions
FR2779255A1 (en
Inventor
Olivier Brunet
Jean Christophe Fidalgo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR9806684A priority Critical patent/FR2779255B1/en
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Priority to CA002333431A priority patent/CA2333431A1/en
Priority to AU38322/99A priority patent/AU3832299A/en
Priority to EP99920924A priority patent/EP1084481A1/en
Priority to PCT/FR1999/001232 priority patent/WO1999062028A1/en
Priority to BR9910718-0A priority patent/BR9910718A/en
Priority to JP2000551358A priority patent/JP2002517047A/en
Priority to CN99806621A priority patent/CN1309796A/en
Publication of FR2779255A1 publication Critical patent/FR2779255A1/en
Application granted granted Critical
Publication of FR2779255B1 publication Critical patent/FR2779255B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
    • G06K19/07769—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
FR9806684A 1998-05-27 1998-05-27 METHOD FOR MANUFACTURING A PORTABLE ELECTRONIC DEVICE COMPRISING AT LEAST ONE INTEGRATED CIRCUIT CHIP Expired - Fee Related FR2779255B1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR9806684A FR2779255B1 (en) 1998-05-27 1998-05-27 METHOD FOR MANUFACTURING A PORTABLE ELECTRONIC DEVICE COMPRISING AT LEAST ONE INTEGRATED CIRCUIT CHIP
AU38322/99A AU3832299A (en) 1998-05-27 1999-05-26 Method for making a portable electronic device comprising at least an integratedcircuit chip
EP99920924A EP1084481A1 (en) 1998-05-27 1999-05-26 Method for making a portable electronic device comprising at least an integrated circuit chip
PCT/FR1999/001232 WO1999062028A1 (en) 1998-05-27 1999-05-26 Method for making a portable electronic device comprising at least an integrated circuit chip
CA002333431A CA2333431A1 (en) 1998-05-27 1999-05-26 Method for making a portable electronic device comprising at least an integrated circuit chip
BR9910718-0A BR9910718A (en) 1998-05-27 1999-05-26 Manufacturing process for a portable electronic device that includes at least one integrated circuit microchip
JP2000551358A JP2002517047A (en) 1998-05-27 1999-05-26 Method of manufacturing a portable electronic device having at least one integrated circuit chip
CN99806621A CN1309796A (en) 1998-05-27 1999-05-26 Method for making portable electronic device comprising at least one integrated circuit chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9806684A FR2779255B1 (en) 1998-05-27 1998-05-27 METHOD FOR MANUFACTURING A PORTABLE ELECTRONIC DEVICE COMPRISING AT LEAST ONE INTEGRATED CIRCUIT CHIP

Publications (2)

Publication Number Publication Date
FR2779255A1 FR2779255A1 (en) 1999-12-03
FR2779255B1 true FR2779255B1 (en) 2001-10-12

Family

ID=9526770

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9806684A Expired - Fee Related FR2779255B1 (en) 1998-05-27 1998-05-27 METHOD FOR MANUFACTURING A PORTABLE ELECTRONIC DEVICE COMPRISING AT LEAST ONE INTEGRATED CIRCUIT CHIP

Country Status (8)

Country Link
EP (1) EP1084481A1 (en)
JP (1) JP2002517047A (en)
CN (1) CN1309796A (en)
AU (1) AU3832299A (en)
BR (1) BR9910718A (en)
CA (1) CA2333431A1 (en)
FR (1) FR2779255B1 (en)
WO (1) WO1999062028A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2875995B1 (en) 2004-09-24 2014-10-24 Oberthur Card Syst Sa METHOD FOR MOUNTING AN ELECTRONIC COMPONENT ON A SUPPORT, PREFERABLY MOU, AND ELECTRONIC ENTITY THUS OBTAINED, SUCH AS A PASSPORT
JP2006318217A (en) 2005-05-12 2006-11-24 Matsushita Electric Works Ltd Adapter for memory card
JP4500214B2 (en) * 2005-05-30 2010-07-14 株式会社日立製作所 Wireless IC tag and method of manufacturing wireless IC tag
CN101025796B (en) * 2006-02-17 2010-05-12 上海英内电子标签有限公司 Electronic label reverse packaging process
JP4950627B2 (en) * 2006-11-10 2012-06-13 株式会社日立製作所 RFIC tag and its use
FR3009411A1 (en) * 2013-08-02 2015-02-06 Ask Sa IDENTITY BOOK COVER WITH RADIO FREQUENCY DEVICE AND METHOD FOR MANUFACTURING THE SAME
FR3027433A1 (en) 2014-10-16 2016-04-22 Ask Sa METHOD FOR MANUFACTURING A RADIO FREQUENCY DEVICE SUPPORT CONSISTING OF A SINGLE LAYER
CN106299623A (en) * 2016-09-27 2017-01-04 北京小米移动软件有限公司 Wireless Fidelity WiFi antenna and manufacture method
CN106897766A (en) * 2017-03-31 2017-06-27 金邦达有限公司 The manufacture method of smart card and smart card with IC chip

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2684471B1 (en) * 1991-12-02 1994-03-04 Solaic METHOD FOR MANUFACTURING A MEMORY CARD AND MEMORY CARD THUS OBTAINED.
EP0688050A1 (en) * 1994-06-15 1995-12-20 Philips Cartes Et Systemes Assembly method for integrated circuit card and such obtained card
US6329213B1 (en) * 1997-05-01 2001-12-11 Micron Technology, Inc. Methods for forming integrated circuits within substrates

Also Published As

Publication number Publication date
JP2002517047A (en) 2002-06-11
CN1309796A (en) 2001-08-22
BR9910718A (en) 2001-01-09
AU3832299A (en) 1999-12-13
CA2333431A1 (en) 1999-12-02
FR2779255A1 (en) 1999-12-03
WO1999062028A1 (en) 1999-12-02
EP1084481A1 (en) 2001-03-21

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Effective date: 20100129