FR2775121B1 - METHOD FOR MANUFACTURING THIN FILM SUBSTRATES OF SEMICONDUCTOR MATERIAL, EPITAXIAL STRUCTURES OF SEMICONDUCTOR MATERIAL FORMED ON SUCH SUBSTRATES, AND COMPONENTS OBTAINED FROM SUCH STRUCTURES - Google Patents
METHOD FOR MANUFACTURING THIN FILM SUBSTRATES OF SEMICONDUCTOR MATERIAL, EPITAXIAL STRUCTURES OF SEMICONDUCTOR MATERIAL FORMED ON SUCH SUBSTRATES, AND COMPONENTS OBTAINED FROM SUCH STRUCTURESInfo
- Publication number
- FR2775121B1 FR2775121B1 FR9801790A FR9801790A FR2775121B1 FR 2775121 B1 FR2775121 B1 FR 2775121B1 FR 9801790 A FR9801790 A FR 9801790A FR 9801790 A FR9801790 A FR 9801790A FR 2775121 B1 FR2775121 B1 FR 2775121B1
- Authority
- FR
- France
- Prior art keywords
- semiconductor material
- structures
- substrates
- thin film
- components obtained
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000463 material Substances 0.000 title 2
- 239000004065 semiconductor Substances 0.000 title 2
- 239000000758 substrate Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000010409 thin film Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9801790A FR2775121B1 (en) | 1998-02-13 | 1998-02-13 | METHOD FOR MANUFACTURING THIN FILM SUBSTRATES OF SEMICONDUCTOR MATERIAL, EPITAXIAL STRUCTURES OF SEMICONDUCTOR MATERIAL FORMED ON SUCH SUBSTRATES, AND COMPONENTS OBTAINED FROM SUCH STRUCTURES |
PCT/FR1999/000309 WO1999041776A1 (en) | 1998-02-13 | 1999-02-11 | Semiconductor material epitaxial structures formed on thin-film substrates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9801790A FR2775121B1 (en) | 1998-02-13 | 1998-02-13 | METHOD FOR MANUFACTURING THIN FILM SUBSTRATES OF SEMICONDUCTOR MATERIAL, EPITAXIAL STRUCTURES OF SEMICONDUCTOR MATERIAL FORMED ON SUCH SUBSTRATES, AND COMPONENTS OBTAINED FROM SUCH STRUCTURES |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2775121A1 FR2775121A1 (en) | 1999-08-20 |
FR2775121B1 true FR2775121B1 (en) | 2000-05-05 |
Family
ID=9522974
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9801790A Expired - Fee Related FR2775121B1 (en) | 1998-02-13 | 1998-02-13 | METHOD FOR MANUFACTURING THIN FILM SUBSTRATES OF SEMICONDUCTOR MATERIAL, EPITAXIAL STRUCTURES OF SEMICONDUCTOR MATERIAL FORMED ON SUCH SUBSTRATES, AND COMPONENTS OBTAINED FROM SUCH STRUCTURES |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2775121B1 (en) |
WO (1) | WO1999041776A1 (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2817395B1 (en) | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A SUBSTRATE, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED THEREBY |
FR2834124B1 (en) | 2001-12-20 | 2005-05-20 | Osram Opto Semiconductors Gmbh | PROCESS FOR PRODUCING SEMICONDUCTOR LAYERS |
DE10223719C1 (en) * | 2002-05-28 | 2003-11-27 | Infineon Technologies Ag | Layer arrangement comprises first substrate having first main surface containing first thermally dissolvable delamination layer, and second substrate having second main surface containing second thermally dissolvable delamination layer |
DE602004020181D1 (en) * | 2003-01-07 | 2009-05-07 | Soitec Silicon On Insulator | RECYCLING A WATER WITH A MULTILAYER STRUCTURE AFTER REMOVING A THIN LAYER |
FR2849715B1 (en) * | 2003-01-07 | 2007-03-09 | Soitec Silicon On Insulator | RECYCLING A PLATE COMPRISING A MULTILAYER STRUCTURE AFTER REMOVING A THIN LAYER |
FR2849714B1 (en) * | 2003-01-07 | 2007-03-09 | RECYCLING BY MECHANICAL MEANS OF A PLATE COMPRISING A MULTILAYER STRUCTURE AFTER SAMPLING A THIN LAYER | |
WO2004061943A1 (en) * | 2003-01-07 | 2004-07-22 | S.O.I.Tec Silicon On Insulator Technologies | Recycling by mechanical means of a wafer comprising a taking-off structure after taking-off a thin layer thereof |
US7018909B2 (en) | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
FR2855650B1 (en) | 2003-05-30 | 2006-03-03 | Soitec Silicon On Insulator | SUBSTRATES FOR CONSTRAINTS SYSTEMS AND METHOD FOR CRYSTALLINE GROWTH ON SUCH A SUBSTRATE |
DE102004062290A1 (en) | 2004-12-23 | 2006-07-06 | Osram Opto Semiconductors Gmbh | Method for producing a semiconductor chip |
FR2929758B1 (en) | 2008-04-07 | 2011-02-11 | Commissariat Energie Atomique | TRANSFER METHOD USING A FERROELECTRIC SUBSTRATE |
FR2931293B1 (en) | 2008-05-15 | 2010-09-03 | Soitec Silicon On Insulator | PROCESS FOR MANUFACTURING AN EPITAXIA SUPPORT HETEROSTRUCTURE AND CORRESPONDING HETEROSTRUCTURE |
EP2151861A1 (en) | 2008-08-06 | 2010-02-10 | S.O.I. TEC Silicon | Passivation of etched semiconductor structures |
TWI457984B (en) | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | Relaxation of strained layers |
EP2151852B1 (en) | 2008-08-06 | 2020-01-15 | Soitec | Relaxation and transfer of strained layers |
EP2151856A1 (en) | 2008-08-06 | 2010-02-10 | S.O.I. TEC Silicon | Relaxation of strained layers |
EP2159836B1 (en) | 2008-08-25 | 2017-05-31 | Soitec | Stiffening layers for the relaxation of strained layers |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4891329A (en) * | 1988-11-29 | 1990-01-02 | University Of North Carolina | Method of forming a nonsilicon semiconductor on insulator structure |
JPH07187892A (en) * | 1991-06-28 | 1995-07-25 | Internatl Business Mach Corp <Ibm> | Silicon and its formation |
FR2681472B1 (en) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL. |
EP1179842A3 (en) * | 1992-01-31 | 2002-09-04 | Canon Kabushiki Kaisha | Semiconductor substrate and method for preparing same |
FR2731109A1 (en) * | 1995-02-27 | 1996-08-30 | Picogiga Sa | III-V SEMICONDUCTOR COMPONENT AND ITS MANUFACTURING METHOD |
-
1998
- 1998-02-13 FR FR9801790A patent/FR2775121B1/en not_active Expired - Fee Related
-
1999
- 1999-02-11 WO PCT/FR1999/000309 patent/WO1999041776A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
FR2775121A1 (en) | 1999-08-20 |
WO1999041776A1 (en) | 1999-08-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property | ||
ST | Notification of lapse |
Effective date: 20141031 |