FR2772507B1 - Dispositif de memoire a circuits integres ayant des lignes d'entree et de sortie de donnees s'etendant dans la direction des colonnes, et circuits et procedes pour reparer des cellules defectueuses - Google Patents
Dispositif de memoire a circuits integres ayant des lignes d'entree et de sortie de donnees s'etendant dans la direction des colonnes, et circuits et procedes pour reparer des cellules defectueusesInfo
- Publication number
- FR2772507B1 FR2772507B1 FR9815298A FR9815298A FR2772507B1 FR 2772507 B1 FR2772507 B1 FR 2772507B1 FR 9815298 A FR9815298 A FR 9815298A FR 9815298 A FR9815298 A FR 9815298A FR 2772507 B1 FR2772507 B1 FR 2772507B1
- Authority
- FR
- France
- Prior art keywords
- columns
- circuits
- methods
- integrated circuit
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970065906A KR100252053B1 (ko) | 1997-12-04 | 1997-12-04 | 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2772507A1 FR2772507A1 (fr) | 1999-06-18 |
FR2772507B1 true FR2772507B1 (fr) | 2001-09-14 |
Family
ID=19526456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9815298A Expired - Fee Related FR2772507B1 (fr) | 1997-12-04 | 1998-12-03 | Dispositif de memoire a circuits integres ayant des lignes d'entree et de sortie de donnees s'etendant dans la direction des colonnes, et circuits et procedes pour reparer des cellules defectueuses |
Country Status (7)
Country | Link |
---|---|
US (2) | US6151263A (fr) |
JP (1) | JP3757059B2 (fr) |
KR (1) | KR100252053B1 (fr) |
DE (1) | DE19823584B4 (fr) |
FR (1) | FR2772507B1 (fr) |
GB (2) | GB2332292B (fr) |
TW (1) | TW402722B (fr) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100252053B1 (ko) * | 1997-12-04 | 2000-05-01 | 윤종용 | 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법 |
EP1052572B1 (fr) * | 1999-05-12 | 2003-07-30 | STMicroelectronics S.r.l. | Mémoire non volatile avec redondance de ligne |
JP2001256794A (ja) | 2000-03-13 | 2001-09-21 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2002014875A (ja) | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | 半導体集積回路、半導体集積回路のメモリリペア方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体 |
US6327197B1 (en) * | 2000-09-13 | 2001-12-04 | Silicon Access Networks, Inc. | Structure and method of a column redundancy memory |
FR2817982B1 (fr) * | 2000-12-08 | 2003-10-24 | St Microelectronics Sa | Circuit memoire a redondance partagee |
KR100351992B1 (ko) * | 2000-12-30 | 2002-09-12 | 주식회사 하이닉스반도체 | 반도체 메모리장치의 데이타 입/출력 패스 변경장치 |
FR2820844B1 (fr) * | 2001-02-12 | 2003-05-30 | Iroc Technologies | Dispositif de reconfiguration d'un ensemble memoire presentant des defauts |
KR100447224B1 (ko) * | 2001-09-20 | 2004-09-04 | 주식회사 하이닉스반도체 | 비휘발성 강유전체 메모리 장치의 칼럼 리페어 회로 |
US20040015771A1 (en) * | 2002-07-16 | 2004-01-22 | Menahem Lasser | Error correction for non-volatile memory |
EP1408515B1 (fr) * | 2002-10-07 | 2005-12-14 | Infineon Technologies AG | Circuit pour la réparation de sous-colonnes |
KR100936790B1 (ko) * | 2003-04-29 | 2010-01-14 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
US7054206B2 (en) * | 2003-05-28 | 2006-05-30 | Infineon Technologies Ag | Sub-column-repair-circuit |
KR20040108220A (ko) * | 2003-06-17 | 2004-12-23 | 삼성전자주식회사 | 분할 워드라인 구조를 가지는 저 전력 반도체 메모리 장치 |
JP2005267686A (ja) * | 2004-03-16 | 2005-09-29 | Toshiba Corp | 半導体記憶装置 |
KR100648266B1 (ko) * | 2004-08-30 | 2006-11-23 | 삼성전자주식회사 | 리던던시 칼럼의 리페어 효율을 향상시킨 반도체 메모리장치 |
KR100732633B1 (ko) * | 2006-02-01 | 2007-06-27 | 삼성전자주식회사 | 비연속적인 비트라인 디코딩을 수행하는 플래시 메모리장치 |
JP2008097675A (ja) * | 2006-10-06 | 2008-04-24 | Elpida Memory Inc | 半導体装置 |
FR2972838B1 (fr) * | 2011-03-18 | 2013-04-12 | Soitec Silicon On Insulator | Memoire a semi-conducteurs comportant des amplificateurs de lecture decales associes a un decodeur de colonne local |
KR102415835B1 (ko) | 2016-01-08 | 2022-07-01 | 삼성전자주식회사 | 반도체 메모리 장치, 및 상기 반도체 메모리 장치를 포함하는 메모리 시스템 |
KR20200132035A (ko) * | 2019-05-15 | 2020-11-25 | 삼성전자주식회사 | 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법 |
US12027224B2 (en) | 2022-03-16 | 2024-07-02 | International Business Machines Corporation | Authenticity and yield by reading defective cells |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4473895A (en) * | 1979-06-15 | 1984-09-25 | Fujitsu Limited | Semiconductor memory device |
US4979145A (en) * | 1986-05-01 | 1990-12-18 | Motorola, Inc. | Structure and method for improving high speed data rate in a DRAM |
US4866676A (en) * | 1988-03-24 | 1989-09-12 | Motorola, Inc. | Testing arrangement for a DRAM with redundancy |
JPH0289299A (ja) * | 1988-09-27 | 1990-03-29 | Nec Corp | 半導体記憶装置 |
JP2837433B2 (ja) * | 1989-06-05 | 1998-12-16 | 三菱電機株式会社 | 半導体記憶装置における不良ビット救済回路 |
GB8926004D0 (en) * | 1989-11-17 | 1990-01-10 | Inmos Ltd | Repairable memory circuit |
JPH03214500A (ja) * | 1990-01-18 | 1991-09-19 | Sony Corp | メモリ装置 |
JPH0437904A (ja) * | 1990-06-01 | 1992-02-07 | Mitsubishi Electric Corp | カウンタ装置 |
US5274593A (en) * | 1990-09-28 | 1993-12-28 | Intergraph Corporation | High speed redundant rows and columns for semiconductor memories |
JPH06103599B2 (ja) * | 1990-11-16 | 1994-12-14 | 三菱電機株式会社 | 半導体集積回路装置 |
US5301153A (en) * | 1992-06-03 | 1994-04-05 | Mips Computer Systems, Inc. | Redundant element substitution apparatus |
US5469401A (en) * | 1992-07-14 | 1995-11-21 | Mosaid Technologies Incorporated | Column redundancy scheme for DRAM using normal and redundant column decoders programmed with defective array address and defective column address |
JPH0636560A (ja) * | 1992-07-21 | 1994-02-10 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR960006271B1 (ko) * | 1993-08-14 | 1996-05-13 | 삼성전자주식회사 | 고속동작을 위한 입출력라인구동방식을 가지는 반도체메모리장치 |
JP3265076B2 (ja) * | 1993-09-20 | 2002-03-11 | 株式会社東芝 | 半導体記憶装置 |
JPH07130163A (ja) * | 1993-11-01 | 1995-05-19 | Matsushita Electron Corp | 半導体メモリ |
KR0130030B1 (ko) * | 1994-08-25 | 1998-10-01 | 김광호 | 반도체 메모리 장치의 컬럼 리던던시 회로 및 그 방법 |
JP2570203B2 (ja) * | 1994-11-22 | 1997-01-08 | 日本電気株式会社 | 半導体記憶装置 |
JP3518562B2 (ja) * | 1995-02-17 | 2004-04-12 | 株式会社ルネサステクノロジ | 半導体装置 |
US5502676A (en) * | 1995-04-24 | 1996-03-26 | Motorola, Inc. | Integrated circuit memory with column redundancy having shared read global data lines |
KR0142962B1 (ko) * | 1995-05-12 | 1998-08-17 | 김광호 | 계급적 컬럼선택라인구조를 가지는 반도체 메모리 장치 |
JP3501893B2 (ja) * | 1996-02-23 | 2004-03-02 | 株式会社 沖マイクロデザイン | 半導体記憶装置 |
KR100252053B1 (ko) * | 1997-12-04 | 2000-05-01 | 윤종용 | 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법 |
JP2001101890A (ja) * | 1999-09-28 | 2001-04-13 | Mitsubishi Electric Corp | 半導体記憶装置 |
-
1997
- 1997-12-04 KR KR1019970065906A patent/KR100252053B1/ko not_active IP Right Cessation
-
1998
- 1998-05-22 GB GB9811155A patent/GB2332292B/en not_active Expired - Fee Related
- 1998-05-27 DE DE19823584A patent/DE19823584B4/de not_active Expired - Fee Related
- 1998-07-08 TW TW087111042A patent/TW402722B/zh not_active IP Right Cessation
- 1998-07-23 JP JP20821498A patent/JP3757059B2/ja not_active Expired - Fee Related
- 1998-12-01 US US09/203,262 patent/US6151263A/en not_active Expired - Lifetime
- 1998-12-03 FR FR9815298A patent/FR2772507B1/fr not_active Expired - Fee Related
-
2000
- 2000-11-15 US US09/713,107 patent/US6304500B1/en not_active Expired - Lifetime
-
2001
- 2001-11-28 GB GBGB0128500.6A patent/GB0128500D0/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
DE19823584A1 (de) | 1999-06-10 |
KR19990047471A (ko) | 1999-07-05 |
TW402722B (en) | 2000-08-21 |
GB2332292B (en) | 2002-06-19 |
DE19823584B4 (de) | 2010-06-10 |
US6151263A (en) | 2000-11-21 |
FR2772507A1 (fr) | 1999-06-18 |
KR100252053B1 (ko) | 2000-05-01 |
GB0128500D0 (en) | 2002-01-23 |
GB9811155D0 (en) | 1998-07-22 |
GB2332292A (en) | 1999-06-16 |
US6304500B1 (en) | 2001-10-16 |
JP3757059B2 (ja) | 2006-03-22 |
JPH11176187A (ja) | 1999-07-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20140829 |