FR2543326B1 - Systeme de traitement de donnees comprenant un circuit de conversion d'adresse utilise en commun avec une unite centrale de traitement et une unite de canaux - Google Patents

Systeme de traitement de donnees comprenant un circuit de conversion d'adresse utilise en commun avec une unite centrale de traitement et une unite de canaux

Info

Publication number
FR2543326B1
FR2543326B1 FR848404570A FR8404570A FR2543326B1 FR 2543326 B1 FR2543326 B1 FR 2543326B1 FR 848404570 A FR848404570 A FR 848404570A FR 8404570 A FR8404570 A FR 8404570A FR 2543326 B1 FR2543326 B1 FR 2543326B1
Authority
FR
France
Prior art keywords
joint
conversion circuit
system including
unit
address conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR848404570A
Other languages
English (en)
Other versions
FR2543326A1 (fr
Inventor
Akihito Ohtake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2543326A1 publication Critical patent/FR2543326A1/fr
Application granted granted Critical
Publication of FR2543326B1 publication Critical patent/FR2543326B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR848404570A 1983-03-23 1984-03-23 Systeme de traitement de donnees comprenant un circuit de conversion d'adresse utilise en commun avec une unite centrale de traitement et une unite de canaux Expired - Fee Related FR2543326B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58048233A JPS59173828A (ja) 1983-03-23 1983-03-23 デ−タ処理システム

Publications (2)

Publication Number Publication Date
FR2543326A1 FR2543326A1 (fr) 1984-09-28
FR2543326B1 true FR2543326B1 (fr) 1990-10-26

Family

ID=12797721

Family Applications (1)

Application Number Title Priority Date Filing Date
FR848404570A Expired - Fee Related FR2543326B1 (fr) 1983-03-23 1984-03-23 Systeme de traitement de donnees comprenant un circuit de conversion d'adresse utilise en commun avec une unite centrale de traitement et une unite de canaux

Country Status (3)

Country Link
US (1) US4602329A (fr)
JP (1) JPS59173828A (fr)
FR (1) FR2543326B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5890220A (en) * 1991-02-05 1999-03-30 Hitachi, Ltd. Address conversion apparatus accessible to both I/O devices and processor and having a reduced number of index buffers
US5367661A (en) * 1992-11-19 1994-11-22 International Business Machines Corporation Technique for controlling channel operations in a host computer by updating signals defining a dynamically alterable channel program
JPH06290076A (ja) * 1993-04-05 1994-10-18 Nec Ic Microcomput Syst Ltd デバッグ装置
US5668949A (en) * 1993-11-12 1997-09-16 Intel Corporation System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource
JP2003029932A (ja) * 2001-07-18 2003-01-31 Hitachi Ltd ディスク制御装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810105A (en) * 1967-10-26 1974-05-07 Xerox Corp Computer input-output system
US3820079A (en) * 1971-11-01 1974-06-25 Hewlett Packard Co Bus oriented,modular,multiprocessing computer
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
GB1574468A (en) * 1976-09-30 1980-09-10 Burroughs Corp Input-output subsystem in a digital data processing system
US4137565A (en) * 1977-01-10 1979-01-30 Xerox Corporation Direct memory access module for a controller
US4155119A (en) * 1977-09-21 1979-05-15 Sperry Rand Corporation Method for providing virtual addressing for externally specified addressed input/output operations
JPS57204935A (en) * 1981-06-12 1982-12-15 Fujitsu Ltd Dynamic address conversion system for channel device

Also Published As

Publication number Publication date
JPS59173828A (ja) 1984-10-02
FR2543326A1 (fr) 1984-09-28
US4602329A (en) 1986-07-22

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Legal Events

Date Code Title Description
ST Notification of lapse