FR2513778B1 - Dispositif et procede d'informatique - Google Patents

Dispositif et procede d'informatique

Info

Publication number
FR2513778B1
FR2513778B1 FR8216392A FR8216392A FR2513778B1 FR 2513778 B1 FR2513778 B1 FR 2513778B1 FR 8216392 A FR8216392 A FR 8216392A FR 8216392 A FR8216392 A FR 8216392A FR 2513778 B1 FR2513778 B1 FR 2513778B1
Authority
FR
France
Prior art keywords
computer device
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8216392A
Other languages
English (en)
Other versions
FR2513778A1 (fr
Inventor
Fumitaka Sato
Kunihiro Nagura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of FR2513778A1 publication Critical patent/FR2513778A1/fr
Application granted granted Critical
Publication of FR2513778B1 publication Critical patent/FR2513778B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/253—Centralized memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Storage Device Security (AREA)
FR8216392A 1981-09-29 1982-09-29 Dispositif et procede d'informatique Expired FR2513778B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56153045A JPS5856277A (ja) 1981-09-29 1981-09-29 情報処理装置ならびに方法

Publications (2)

Publication Number Publication Date
FR2513778A1 FR2513778A1 (fr) 1983-04-01
FR2513778B1 true FR2513778B1 (fr) 1988-10-28

Family

ID=15553760

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8216392A Expired FR2513778B1 (fr) 1981-09-29 1982-09-29 Dispositif et procede d'informatique

Country Status (5)

Country Link
US (1) US4628450A (fr)
JP (1) JPS5856277A (fr)
DE (1) DE3235264A1 (fr)
FR (1) FR2513778B1 (fr)
GB (1) GB2107091B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942367Y2 (ja) * 1978-11-06 1984-12-11 ソニー株式会社 包装装置
US4729091A (en) * 1984-11-13 1988-03-01 International Business Machines Corporation Directing storage requests prior to address comparator initialization with a reference address range
JP2740326B2 (ja) * 1989-03-01 1998-04-15 三洋電機株式会社 接触吸熱、放熱装置
US6209061B1 (en) * 1998-03-02 2001-03-27 Hewlett-Packard Co. Integrated hierarchical memory overlay having invariant address space span that inactivates a same address space span in main memory
US20050097304A1 (en) * 2003-10-30 2005-05-05 International Business Machines Corporation Pipeline recirculation for data misprediction in a fast-load data cache

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3701107A (en) * 1970-10-01 1972-10-24 Rca Corp Computer with probability means to transfer pages from large memory to fast memory
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
US3753242A (en) * 1971-12-16 1973-08-14 Honeywell Inf Systems Memory overlay system
US4016541A (en) * 1972-10-10 1977-04-05 Digital Equipment Corporation Memory unit for connection to central processor unit and interconnecting bus
GB1441817A (en) * 1973-07-19 1976-07-07 Int Computers Ltd Data processing apparatus
JPS5211728A (en) * 1975-07-18 1977-01-28 Oki Electric Ind Co Ltd Memory device with stratum composition
JPS5263038A (en) * 1975-10-01 1977-05-25 Hitachi Ltd Data processing device
IT1052738B (it) * 1975-12-24 1981-07-20 Cselt Centro Studi Lab Telecom Dispositivo per il caricamento automatico della memoria centrale di calcolatori elettronici
US4181937A (en) * 1976-11-10 1980-01-01 Fujitsu Limited Data processing system having an intermediate buffer memory
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
US4126894A (en) * 1977-02-17 1978-11-21 Xerox Corporation Memory overlay linking system
US4136386A (en) * 1977-10-06 1979-01-23 International Business Machines Corporation Backing store access coordination in a multi-processor system
US4161024A (en) * 1977-12-22 1979-07-10 Honeywell Information Systems Inc. Private cache-to-CPU interface in a bus oriented data processing system
IT1111606B (it) * 1978-03-03 1986-01-13 Cselt Centro Studi Lab Telecom Sistema elaborativo modulare multiconfigurabile integrato con un sistema di preelaborazione
US4253146A (en) * 1978-12-21 1981-02-24 Burroughs Corporation Module for coupling computer-processors
US4280176A (en) * 1978-12-26 1981-07-21 International Business Machines Corporation Memory configuration, address interleaving, relocation and access control system
US4481580A (en) * 1979-11-19 1984-11-06 Sperry Corporation Distributed data transfer control for parallel processor architectures
US4473877A (en) * 1981-04-16 1984-09-25 Tulk Ronald K Parasitic memory expansion for computers
US4450524A (en) * 1981-09-23 1984-05-22 Rca Corporation Single chip microcomputer with external decoder and memory and internal logic for disabling the ROM and relocating the RAM
US4484267A (en) * 1981-12-30 1984-11-20 International Business Machines Corporation Cache sharing control in a multiprocessor
US4463420A (en) * 1982-02-23 1984-07-31 International Business Machines Corporation Multiprocessor cache replacement under task control

Also Published As

Publication number Publication date
GB2107091B (en) 1985-10-23
DE3235264A1 (de) 1983-04-07
GB2107091A (en) 1983-04-20
US4628450A (en) 1986-12-09
JPS5856277A (ja) 1983-04-02
FR2513778A1 (fr) 1983-04-01
DE3235264C2 (fr) 1991-10-24

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Legal Events

Date Code Title Description
CD Change of name or company name
ST Notification of lapse