FR2470496B1 - Registre - Google Patents

Registre

Info

Publication number
FR2470496B1
FR2470496B1 FR8024574A FR8024574A FR2470496B1 FR 2470496 B1 FR2470496 B1 FR 2470496B1 FR 8024574 A FR8024574 A FR 8024574A FR 8024574 A FR8024574 A FR 8024574A FR 2470496 B1 FR2470496 B1 FR 2470496B1
Authority
FR
France
Prior art keywords
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8024574A
Other languages
English (en)
Other versions
FR2470496A1 (fr
Inventor
Maurice Leron Hutson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Control Data Corp
Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Control Data Corp filed Critical Control Data Corp
Publication of FR2470496A1 publication Critical patent/FR2470496A1/fr
Application granted granted Critical
Publication of FR2470496B1 publication Critical patent/FR2470496B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Shift Register Type Memory (AREA)
  • Information Transfer Systems (AREA)
FR8024574A 1979-11-19 1980-11-19 Registre Expired FR2470496B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/095,698 US4296477A (en) 1979-11-19 1979-11-19 Register device for transmission of data having two data ranks one of which receives data only when the other is full

Publications (2)

Publication Number Publication Date
FR2470496A1 FR2470496A1 (fr) 1981-05-29
FR2470496B1 true FR2470496B1 (fr) 1986-05-09

Family

ID=22253203

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8024574A Expired FR2470496B1 (fr) 1979-11-19 1980-11-19 Registre

Country Status (7)

Country Link
US (1) US4296477A (fr)
JP (1) JPS6027060B2 (fr)
AU (1) AU537192B2 (fr)
CA (1) CA1125406A (fr)
DE (1) DE3042105A1 (fr)
FR (1) FR2470496B1 (fr)
GB (2) GB2064180B (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433391A (en) * 1981-08-17 1984-02-21 Burroughs Corporation Buffered handshake bus with transmission and response counters for avoiding receiver overflow
JPS62211725A (ja) * 1986-03-12 1987-09-17 Sanyo Electric Co Ltd デ−タ伝送路制御装置
US4833655A (en) * 1985-06-28 1989-05-23 Wang Laboratories, Inc. FIFO memory with decreased fall-through delay
JPH0823807B2 (ja) * 1987-08-26 1996-03-06 松下電器産業株式会社 Ｆｉｆｏメモリ
US5095462A (en) * 1990-05-25 1992-03-10 Advanced Micro Devices, Inc. Fifo information storage apparatus including status and logic modules for each cell
US5418910A (en) * 1992-05-05 1995-05-23 Tandy Corporation Dual buffer cache system for transferring audio compact disk subchannel information to a computer
CA2106271C (fr) * 1993-01-11 2004-11-30 Joseph H. Steinmetz Architecture de memoires premier entre premier sorti a un et a plusieurs etages pour synchroniseurs de transfert de donnees
IT1293652B1 (it) * 1997-07-25 1999-03-08 Alsthom Cge Alcatel Sistema di implementazione di una memoria elastica
TWI560552B (en) * 2015-01-30 2016-12-01 Via Tech Inc Interface chip and control method therefor
JP6390806B1 (ja) 2017-08-02 2018-09-19 株式会社明電舎 インバータ装置
CN114816319B (zh) * 2022-04-21 2023-02-17 中国人民解放军32802部队 一种fifo存储器的多级流水读写方法和装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1259397A (fr) * 1960-02-19 1961-04-28 Alsthom Cgee Bascule binaire logique
NL297562A (fr) * 1962-09-06
US3460098A (en) * 1967-03-15 1969-08-05 Sperry Rand Corp Non-synchronous design for digital device control
DE1933907A1 (de) * 1969-07-03 1971-03-11 Siemens Ag Pufferspeicher
NL7014737A (fr) * 1970-10-08 1972-04-11
US3704452A (en) * 1970-12-31 1972-11-28 Ibm Shift register storage unit
NL7105512A (fr) * 1971-04-23 1972-10-25
US3742466A (en) * 1971-11-24 1973-06-26 Honeywell Inf Systems Memory system for receiving and transmitting information over a plurality of communication lines
US3781821A (en) * 1972-06-02 1973-12-25 Ibm Selective shift register
FR2231295A1 (en) * 1973-05-25 1974-12-20 Cit Alcatel Buffer memory between data input and processor - supplies input data to processor with different priority
US3992699A (en) * 1974-11-13 1976-11-16 Communication Mfg. Co. First-in/first-out data storage system
US3988601A (en) * 1974-12-23 1976-10-26 Rca Corporation Data processor reorder shift register memory
US4051353A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Accordion shift register and its application in the implementation of level sensitive logic system

Also Published As

Publication number Publication date
AU537192B2 (en) 1984-06-14
GB2132456A (en) 1984-07-04
JPS6027060B2 (ja) 1985-06-27
FR2470496A1 (fr) 1981-05-29
DE3042105A1 (de) 1981-05-21
GB2064180A (en) 1981-06-10
CA1125406A (fr) 1982-06-08
GB8314578D0 (en) 1983-06-29
AU6291380A (en) 1981-05-28
DE3042105C2 (fr) 1990-04-26
GB2132456B (en) 1985-01-09
GB2064180B (en) 1984-07-25
JPS5674731A (en) 1981-06-20
US4296477A (en) 1981-10-20

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Legal Events

Date Code Title Description
ST Notification of lapse