FR2450008A1 - Circuit de synchronisation de signaux numeriques plesiochrones par justification - Google Patents

Circuit de synchronisation de signaux numeriques plesiochrones par justification

Info

Publication number
FR2450008A1
FR2450008A1 FR7905109A FR7905109A FR2450008A1 FR 2450008 A1 FR2450008 A1 FR 2450008A1 FR 7905109 A FR7905109 A FR 7905109A FR 7905109 A FR7905109 A FR 7905109A FR 2450008 A1 FR2450008 A1 FR 2450008A1
Authority
FR
France
Prior art keywords
justification
memory
digital signals
synchronizing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7905109A
Other languages
English (en)
Other versions
FR2450008B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PORTEJOIE JEAN FRANCOIS
Original Assignee
PORTEJOIE JEAN FRANCOIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PORTEJOIE JEAN FRANCOIS filed Critical PORTEJOIE JEAN FRANCOIS
Priority to FR7905109A priority Critical patent/FR2450008A1/fr
Priority to US06/121,420 priority patent/US4355387A/en
Priority to GB8005368A priority patent/GB2049364B/en
Priority to CA000345972A priority patent/CA1147876A/fr
Priority to IT47951/80A priority patent/IT1146930B/it
Priority to JP1981580A priority patent/JPS55115751A/ja
Publication of FR2450008A1 publication Critical patent/FR2450008A1/fr
Application granted granted Critical
Publication of FR2450008B1 publication Critical patent/FR2450008B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

DANS LES CIRCUITS D'ENTREE D'UN EQUIPEMENT DE MULTIPLEXAGE, POUR ASSURER LA SYNCHRONISATION DE SIGNAUX NUMERIQUES PLESIOCHRONES, ON UTILISE LE PRINCIPE DE LA JUSTIFICATION, AVEC DES MOYENS POUR ENGENDRER UNE JUSTIFICATION A LA RECEPTION D'UN SIGNAL DE JUSTIFICATION, ET UNE MEMOIRE TAMPON A ECRITURE ET LECTURE INDEPENDANTES. LA MEMOIRE TAMPON EST FORMEE DE DEUX MEMOIRES FIFO EN CASCADE, L'ETAT DE LA LIAISON ENTRE LA SORTIE IR (INPUT-READY) DE LA SECONDE MEMOIRE FIFO ET L'ENTREE SO (SHIFT-OUT) DE LA PREMIERE MEMOIRE FIFO DETERMINANT LE SIGNAL DE DEMANDE DE JUSTIFICATION. LA MEME MEMOIRE PEUT SERVIR DANS L'EQUIPEMENT DE DEMULTIPLEXAGE. UTILISABLE POUR LE MULTIPLEXAGE OU LE DEMULTIPLEXAGE DE SIGNAUX PLESIOCHRONES.
FR7905109A 1979-02-21 1979-02-21 Circuit de synchronisation de signaux numeriques plesiochrones par justification Granted FR2450008A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR7905109A FR2450008A1 (fr) 1979-02-21 1979-02-21 Circuit de synchronisation de signaux numeriques plesiochrones par justification
US06/121,420 US4355387A (en) 1979-02-21 1980-02-14 Resynchronizing circuit for time division multiplex system
GB8005368A GB2049364B (en) 1979-02-21 1980-02-18 Synchronisation in tdm systems
CA000345972A CA1147876A (fr) 1979-02-21 1980-02-19 Circuit de resynchronisation pour systeme a multiplexage par repartition dans le temps
IT47951/80A IT1146930B (it) 1979-02-21 1980-02-20 Circuito di sincronizzazione di segnali numerici plesiocroni mediante allineamento
JP1981580A JPS55115751A (en) 1979-02-21 1980-02-21 Tuning circuit for time division multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7905109A FR2450008A1 (fr) 1979-02-21 1979-02-21 Circuit de synchronisation de signaux numeriques plesiochrones par justification

Publications (2)

Publication Number Publication Date
FR2450008A1 true FR2450008A1 (fr) 1980-09-19
FR2450008B1 FR2450008B1 (fr) 1983-11-18

Family

ID=9222533

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7905109A Granted FR2450008A1 (fr) 1979-02-21 1979-02-21 Circuit de synchronisation de signaux numeriques plesiochrones par justification

Country Status (6)

Country Link
US (1) US4355387A (fr)
JP (1) JPS55115751A (fr)
CA (1) CA1147876A (fr)
FR (1) FR2450008A1 (fr)
GB (1) GB2049364B (fr)
IT (1) IT1146930B (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0060155B1 (fr) * 1981-02-19 1985-06-26 Jean-Claude Billy Système de multiplexage et de démultiplexage avec justification
FR2637141A1 (fr) * 1988-09-27 1990-03-30 Alcatel Thomson Faisceaux Dispositif de traitement de signaux plesiochrones
EP0558136A1 (fr) * 1992-02-27 1993-09-01 Philips Patentverwaltung GmbH Système de transmission équipé avec un circuit pour la correction de la gigue de fréquence et/ou phase entre un signal d'entrée et un signal de sortie

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860285A (en) * 1987-10-21 1989-08-22 Advanced Micro Devices, Inc. Master/slave synchronizer
DE3922897A1 (de) * 1989-07-12 1991-01-17 Philips Patentverwaltung Stopfentscheidungsschaltung fuer eine anordnung zur bitratenanpassung
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
IT1244350B (it) * 1990-12-21 1994-07-08 Telettra Spa Metodo per la riduzione del rumore di fase introdotto nella resincronizzazione di segnali digitali mediante giustificazione, e circuiti integrati per l'implementazione del metodo
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
EP0541288B1 (fr) * 1991-11-05 1998-07-08 Fu-Chieh Hsu Architecture à redondance pour module de circuit
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
AU4798793A (en) * 1992-08-10 1994-03-03 Monolithic System Technology, Inc. Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
US5689689A (en) * 1992-12-17 1997-11-18 Tandem Computers Incorporated Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
DK133495A (da) * 1995-11-24 1997-05-25 Dsc Communications As Fremgangsmåde og modtagerkredsløb til desynkronisering i et digitalt transmissionssystem
FR2765427B1 (fr) 1997-06-27 2000-09-08 Sgs Thomson Microelectronics Circuit d'emission-reception pour relier une station de base a une centrale de commande de station de base selon la norme dect
FR3094593B1 (fr) * 2019-03-29 2021-02-19 Teledyne E2V Semiconductors Sas Procédé de synchronisation de données numériques envoyées en série

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2134406A1 (fr) * 1971-04-23 1972-12-08 Philips Nv

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2178418A5 (fr) * 1972-03-31 1973-11-09 Peron Roger
FR2373198A1 (fr) * 1976-12-03 1978-06-30 Cit Alcatel Dispositif de multiplexage numerique de trains plesiochrones
US4095053A (en) * 1977-09-01 1978-06-13 Bell Telephone Laboratories, Incorporated Quasi-pulse stuffing synchronization
US4224473A (en) * 1978-05-31 1980-09-23 Digital Communications Corporation TDMA Multiplexer-demultiplexer with multiple ports

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2134406A1 (fr) * 1971-04-23 1972-12-08 Philips Nv

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/73 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0060155B1 (fr) * 1981-02-19 1985-06-26 Jean-Claude Billy Système de multiplexage et de démultiplexage avec justification
FR2637141A1 (fr) * 1988-09-27 1990-03-30 Alcatel Thomson Faisceaux Dispositif de traitement de signaux plesiochrones
EP0361395A1 (fr) * 1988-09-27 1990-04-04 Alcatel Telspace Dispositif de traitement de signaux plesiochrones
EP0558136A1 (fr) * 1992-02-27 1993-09-01 Philips Patentverwaltung GmbH Système de transmission équipé avec un circuit pour la correction de la gigue de fréquence et/ou phase entre un signal d'entrée et un signal de sortie

Also Published As

Publication number Publication date
JPS55115751A (en) 1980-09-05
IT1146930B (it) 1986-11-19
GB2049364A (en) 1980-12-17
IT8047951A0 (it) 1980-02-20
US4355387A (en) 1982-10-19
FR2450008B1 (fr) 1983-11-18
CA1147876A (fr) 1983-06-07
GB2049364B (en) 1983-02-16

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Legal Events

Date Code Title Description
TP Transmission of property
TP Transmission of property
ST Notification of lapse