FR2380637A1 - Procede de traitement de circuits integres cmos et circuits obtenus - Google Patents

Procede de traitement de circuits integres cmos et circuits obtenus

Info

Publication number
FR2380637A1
FR2380637A1 FR7803655A FR7803655A FR2380637A1 FR 2380637 A1 FR2380637 A1 FR 2380637A1 FR 7803655 A FR7803655 A FR 7803655A FR 7803655 A FR7803655 A FR 7803655A FR 2380637 A1 FR2380637 A1 FR 2380637A1
Authority
FR
France
Prior art keywords
islands
insulating material
sapphire substrate
sepd
same level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7803655A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CBS Corp
Original Assignee
Westinghouse Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westinghouse Electric Corp filed Critical Westinghouse Electric Corp
Publication of FR2380637A1 publication Critical patent/FR2380637A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

a. Procédé de traitement de circuits intégrés CMOS et circuits obtenus. b. Procédé caractérisé en ce qu'on forme un masque sur un matériau semi-conducteur d'un premier matériau isolant électriquement, on oxyde les parties exposées du matériau semi-conducteur jusqu'à la surface du premier matériau isolant électriquement, on masque la structure, on développe de l'oxyde de porte sur la surface semi-conductrice, on forme les connexions métalliques sur les surfaces séparées et on réalise une couche conductrice recouvrant l'oxyde. c. L'invention s'applique notamment à la réalisation de circuits intégrés de type CMOS.
FR7803655A 1977-02-15 1978-02-09 Procede de traitement de circuits integres cmos et circuits obtenus Withdrawn FR2380637A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76913877A 1977-02-15 1977-02-15

Publications (1)

Publication Number Publication Date
FR2380637A1 true FR2380637A1 (fr) 1978-09-08

Family

ID=25084568

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7803655A Withdrawn FR2380637A1 (fr) 1977-02-15 1978-02-09 Procede de traitement de circuits integres cmos et circuits obtenus

Country Status (3)

Country Link
JP (1) JPS53100784A (fr)
DE (1) DE2806410A1 (fr)
FR (1) FR2380637A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996029733A1 (fr) * 1995-03-21 1996-09-26 Peregrine Semiconductor Corp. Reglage de tranche dans un substrat en silicium sur isolant
US5864162A (en) * 1993-07-12 1999-01-26 Peregrine Seimconductor Corporation Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire
US5930638A (en) * 1993-07-12 1999-07-27 Peregrine Semiconductor Corp. Method of making a low parasitic resistor on ultrathin silicon on insulator
US5973363A (en) * 1993-07-12 1999-10-26 Peregrine Semiconductor Corp. CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator
US5973382A (en) * 1993-07-12 1999-10-26 Peregrine Semiconductor Corporation Capacitor on ultrathin semiconductor on insulator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10029288A1 (de) * 2000-06-14 2002-01-03 Infineon Technologies Ag Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1160744A (en) * 1965-11-05 1969-08-06 Plessey Co Ltd Improvements in or relating to Semiconductor Devices
US3740280A (en) * 1971-05-14 1973-06-19 Rca Corp Method of making semiconductor device
US3865653A (en) * 1971-10-12 1975-02-11 Karl Goser Logic circuit having a switching transistor and a load transistor, in particular for a semiconductor storage element
DE2446558A1 (de) * 1974-09-30 1976-04-01 Siemens Ag Verfahren zur herstellung von komplementaer-mis schaltungen

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917069A (fr) * 1972-06-10 1974-02-15
JPS504511A (fr) * 1972-06-15 1975-01-17
JPS567315B2 (fr) * 1973-07-30 1981-02-17
DE2344320C2 (de) * 1973-09-03 1975-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Kompensation von Grenzflächenladungen bei epitaktisch auf ein Substrat aufgewachsenen Siliziumdünnschichten
JPS50151480A (fr) * 1974-05-24 1975-12-05

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1160744A (en) * 1965-11-05 1969-08-06 Plessey Co Ltd Improvements in or relating to Semiconductor Devices
US3740280A (en) * 1971-05-14 1973-06-19 Rca Corp Method of making semiconductor device
US3865653A (en) * 1971-10-12 1975-02-11 Karl Goser Logic circuit having a switching transistor and a load transistor, in particular for a semiconductor storage element
DE2446558A1 (de) * 1974-09-30 1976-04-01 Siemens Ag Verfahren zur herstellung von komplementaer-mis schaltungen

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ABJP/77 *
EXBK/73 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864162A (en) * 1993-07-12 1999-01-26 Peregrine Seimconductor Corporation Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire
US5863823A (en) * 1993-07-12 1999-01-26 Peregrine Semiconductor Corporation Self-aligned edge control in silicon on insulator
US5930638A (en) * 1993-07-12 1999-07-27 Peregrine Semiconductor Corp. Method of making a low parasitic resistor on ultrathin silicon on insulator
US5973363A (en) * 1993-07-12 1999-10-26 Peregrine Semiconductor Corp. CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator
US5973382A (en) * 1993-07-12 1999-10-26 Peregrine Semiconductor Corporation Capacitor on ultrathin semiconductor on insulator
WO1996029733A1 (fr) * 1995-03-21 1996-09-26 Peregrine Semiconductor Corp. Reglage de tranche dans un substrat en silicium sur isolant

Also Published As

Publication number Publication date
DE2806410A1 (de) 1978-08-17
JPS5551343B2 (fr) 1980-12-23
JPS53100784A (en) 1978-09-02

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