FR2335909A1 - Procede et circuit de commande d'une memoire a semi-conducteurs - Google Patents
Procede et circuit de commande d'une memoire a semi-conducteursInfo
- Publication number
- FR2335909A1 FR2335909A1 FR7634520A FR7634520A FR2335909A1 FR 2335909 A1 FR2335909 A1 FR 2335909A1 FR 7634520 A FR7634520 A FR 7634520A FR 7634520 A FR7634520 A FR 7634520A FR 2335909 A1 FR2335909 A1 FR 2335909A1
- Authority
- FR
- France
- Prior art keywords
- circuit
- control
- semiconductor memory
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/415—Address circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2556833A DE2556833C3 (de) | 1975-12-17 | 1975-12-17 | Verfahren und Schaltungsanordnung zum Betreiben eines Halbleiterspeichers |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2335909A1 true FR2335909A1 (fr) | 1977-07-15 |
FR2335909B1 FR2335909B1 (fr) | 1978-12-15 |
Family
ID=5964641
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7634520A Granted FR2335909A1 (fr) | 1975-12-17 | 1976-11-08 | Procede et circuit de commande d'une memoire a semi-conducteurs |
Country Status (5)
Country | Link |
---|---|
US (1) | US4070656A (fr) |
JP (1) | JPS5818712B2 (fr) |
DE (1) | DE2556833C3 (fr) |
FR (1) | FR2335909A1 (fr) |
GB (1) | GB1564418A (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2926050C2 (de) * | 1979-06-28 | 1981-10-01 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren und Schaltungsanordnung zum Lesen Und/oder Schreiben eines integrierten Halbleiterspeichers mit Speicherzellen in MTL-Technik |
DE2926094A1 (de) * | 1979-06-28 | 1981-01-08 | Ibm Deutschland | Verfahren und schaltungsanordnung zum entladen von bitleitungskapazitaeten eines integrierten halbleiterspeichers |
DE2929384C2 (de) * | 1979-07-20 | 1981-07-30 | Ibm Deutschland Gmbh, 7000 Stuttgart | Nachladeschaltung für einen Halbleiterspeicher |
US4302823A (en) * | 1979-12-27 | 1981-11-24 | International Business Machines Corp. | Differential charge sensing system |
US4357687A (en) * | 1980-12-11 | 1982-11-02 | Fairchild Camera And Instr. Corp. | Adaptive word line pull down |
JPS5841597B2 (ja) * | 1980-12-24 | 1983-09-13 | 富士通株式会社 | 半導体メモリディスチャ−ジ回路 |
US4991138A (en) * | 1989-04-03 | 1991-02-05 | International Business Machines Corporation | High speed memory cell with multiple port capability |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3736572A (en) * | 1970-08-19 | 1973-05-29 | Cogar Corp | Bipolar driver for dynamic mos memory array chip |
FR2304991A1 (fr) * | 1975-03-15 | 1976-10-15 | Ibm | Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement |
-
1975
- 1975-12-17 DE DE2556833A patent/DE2556833C3/de not_active Expired
-
1976
- 1976-11-08 FR FR7634520A patent/FR2335909A1/fr active Granted
- 1976-11-08 US US05/739,669 patent/US4070656A/en not_active Expired - Lifetime
- 1976-11-11 GB GB47061/76A patent/GB1564418A/en not_active Expired
- 1976-11-26 JP JP51141361A patent/JPS5818712B2/ja not_active Expired
Non-Patent Citations (3)
Title |
---|
IBM TECHNICAL DISCLOSURE BULLETIN, VOL. 19, NO. 3, AOUT 1976, ARMONK US , HEUBER ET AL "WRITE AUXILIAIRY CIRCUIT", PAGES 965 A 966) * |
IFIP SYMPOSIUM, OCTOBRE 1965, MUNICH, STOPPER: "EINE INTEGRIERTE SCHALTUNG ZUR REALISIERUNG EINES HALBLEITERSPEICHERS", PAGES 259 A 273 * |
PROCEEDINGS OF THE IFAC * |
Also Published As
Publication number | Publication date |
---|---|
US4070656A (en) | 1978-01-24 |
DE2556833B2 (de) | 1980-10-09 |
JPS5818712B2 (ja) | 1983-04-14 |
DE2556833A1 (de) | 1977-06-30 |
FR2335909B1 (fr) | 1978-12-15 |
DE2556833C3 (de) | 1981-11-05 |
GB1564418A (en) | 1980-04-10 |
JPS5275941A (en) | 1977-06-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |