FR2325186A1 - Procede de fabrication de transistor mos et structure de transistor resultante - Google Patents

Procede de fabrication de transistor mos et structure de transistor resultante

Info

Publication number
FR2325186A1
FR2325186A1 FR7400999A FR7400999A FR2325186A1 FR 2325186 A1 FR2325186 A1 FR 2325186A1 FR 7400999 A FR7400999 A FR 7400999A FR 7400999 A FR7400999 A FR 7400999A FR 2325186 A1 FR2325186 A1 FR 2325186A1
Authority
FR
France
Prior art keywords
transistor
manufacturing process
resulting
mos manufacturing
transistor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7400999A
Other languages
English (en)
Other versions
FR2325186B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of FR2325186A1 publication Critical patent/FR2325186A1/fr
Application granted granted Critical
Publication of FR2325186B1 publication Critical patent/FR2325186B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)
FR7400999A 1973-01-15 1974-01-11 Procede de fabrication de transistor mos et structure de transistor resultante Granted FR2325186A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US32367273A 1973-01-15 1973-01-15
US441098A US3913211A (en) 1973-01-15 1974-02-11 Method of MOS transistor manufacture
US05/498,674 US3936858A (en) 1973-01-15 1974-08-19 MOS transistor structure

Publications (2)

Publication Number Publication Date
FR2325186A1 true FR2325186A1 (fr) 1977-04-15
FR2325186B1 FR2325186B1 (fr) 1982-10-01

Family

ID=27406290

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7400999A Granted FR2325186A1 (fr) 1973-01-15 1974-01-11 Procede de fabrication de transistor mos et structure de transistor resultante

Country Status (5)

Country Link
US (2) US3913211A (fr)
CA (1) CA1001771A (fr)
DE (1) DE2400670A1 (fr)
FR (1) FR2325186A1 (fr)
GB (1) GB1454084A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2428324A1 (fr) * 1978-06-06 1980-01-04 Rockwell International Corp Circuits integres a tres grande echelle et leur procede de realisation par alignement automatique de contacts
FR2428358A1 (fr) * 1978-06-06 1980-01-04 Rockwell International Corp Procede de realisation de circuits integres a tres grande echelle ayant des grilles et contacts alignes automatiquement

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IN140846B (fr) * 1973-08-06 1976-12-25 Rca Corp
JPS5197385A (en) * 1975-02-21 1976-08-26 Handotaisochino seizohoho
US3958323A (en) * 1975-04-29 1976-05-25 International Business Machines Corporation Three mask self aligned IGFET fabrication process
US4056825A (en) * 1975-06-30 1977-11-01 International Business Machines Corporation FET device with reduced gate overlap capacitance of source/drain and method of manufacture
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
FR2351502A1 (fr) * 1976-05-14 1977-12-09 Ibm Procede de fabrication de transistors a effet de champ a porte en silicium polycristallin auto-alignee avec les regions source et drain ainsi qu'avec les regions d'isolation de champ encastrees
US4103415A (en) * 1976-12-09 1978-08-01 Fairchild Camera And Instrument Corporation Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
US4553314B1 (en) * 1977-01-26 2000-04-18 Sgs Thomson Microelectronics Method for making a semiconductor device
NL7703941A (nl) * 1977-04-12 1978-10-16 Philips Nv Werkwijze ter vervaardiging van een halfgelei- derinrichting en inrichting, vervaardigd door toepassing van de werkwijze.
US4145803A (en) * 1977-07-22 1979-03-27 Texas Instruments Incorporated Lithographic offset alignment techniques for RAM fabrication
US4216573A (en) * 1978-05-08 1980-08-12 International Business Machines Corporation Three mask process for making field effect transistors
US4231051A (en) * 1978-06-06 1980-10-28 Rockwell International Corporation Process for producing minimal geometry devices for VSLI applications utilizing self-aligned gates and self-aligned contacts, and resultant structures
JPS5529116A (en) * 1978-08-23 1980-03-01 Hitachi Ltd Manufacture of complementary misic
US4219379A (en) * 1978-09-25 1980-08-26 Mostek Corporation Method for making a semiconductor device
US4401691A (en) * 1978-12-18 1983-08-30 Burroughs Corporation Oxidation of silicon wafers to eliminate white ribbon
US4466172A (en) * 1979-01-08 1984-08-21 American Microsystems, Inc. Method for fabricating MOS device with self-aligned contacts
US4278705A (en) * 1979-11-08 1981-07-14 Bell Telephone Laboratories, Incorporated Sequentially annealed oxidation of silicon to fill trenches with silicon dioxide
JPS5693344A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device
US4252582A (en) * 1980-01-25 1981-02-24 International Business Machines Corporation Self aligned method for making bipolar transistor having minimum base to emitter contact spacing
JPS5735341A (en) * 1980-08-12 1982-02-25 Toshiba Corp Method of seperating elements of semiconductor device
JPS5766673A (en) * 1980-10-09 1982-04-22 Toshiba Corp Manufacture of mos type semiconductor device
NL186886C (nl) * 1980-11-28 1992-03-16 Philips Nv Halfgeleiderinrichting.
US4341009A (en) * 1980-12-05 1982-07-27 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
US4472873A (en) 1981-10-22 1984-09-25 Fairchild Camera And Instrument Corporation Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
US4466174A (en) * 1981-12-28 1984-08-21 Texas Instruments Incorporated Method for fabricating MESFET device using a double LOCOS process
JPS59215742A (ja) * 1983-05-24 1984-12-05 Toshiba Corp 半導体装置
US4771328A (en) * 1983-10-13 1988-09-13 International Business Machine Corporation Semiconductor device and process
JPS6088468A (ja) * 1983-10-13 1985-05-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体集積装置の製造方法
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US5247197A (en) * 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
US5192993A (en) * 1988-09-27 1993-03-09 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area
US5439842A (en) * 1992-09-21 1995-08-08 Siliconix Incorporated Low temperature oxide layer over field implant mask
KR960006693B1 (ko) * 1992-11-24 1996-05-22 현대전자산업주식회사 고집적 반도체 접속장치 및 그 제조방법
US6780718B2 (en) * 1993-11-30 2004-08-24 Stmicroelectronics, Inc. Transistor structure and method for making same
US5604370A (en) * 1995-07-11 1997-02-18 Advanced Micro Devices, Inc. Field implant for semiconductor device
JPH09120965A (ja) * 1995-10-25 1997-05-06 Toshiba Corp 半導体装置の製造方法
US6444534B1 (en) 2001-01-30 2002-09-03 Advanced Micro Devices, Inc. SOI semiconductor device opening implantation gettering method
US6376336B1 (en) 2001-02-01 2002-04-23 Advanced Micro Devices, Inc. Frontside SOI gettering with phosphorus doping
US6670259B1 (en) 2001-02-21 2003-12-30 Advanced Micro Devices, Inc. Inert atom implantation method for SOI gettering
US6958264B1 (en) 2001-04-03 2005-10-25 Advanced Micro Devices, Inc. Scribe lane for gettering of contaminants on SOI wafers and gettering method
US6847081B2 (en) * 2001-12-10 2005-01-25 Koninklijke Philips Electronics N.V. Dual gate oxide high-voltage semiconductor device
KR20080081837A (ko) * 2007-03-05 2008-09-10 서울반도체 주식회사 발광 장치

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
NL7113561A (fr) * 1971-10-02 1973-04-04
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2428324A1 (fr) * 1978-06-06 1980-01-04 Rockwell International Corp Circuits integres a tres grande echelle et leur procede de realisation par alignement automatique de contacts
FR2428358A1 (fr) * 1978-06-06 1980-01-04 Rockwell International Corp Procede de realisation de circuits integres a tres grande echelle ayant des grilles et contacts alignes automatiquement

Also Published As

Publication number Publication date
US3936858A (en) 1976-02-03
GB1454084A (en) 1976-10-27
AU6162373A (en) 1975-04-24
DE2400670A1 (de) 1974-07-18
US3913211A (en) 1975-10-21
CA1001771A (en) 1976-12-14
FR2325186B1 (fr) 1982-10-01

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