FR1422913A - Simplified data processing system - Google Patents

Simplified data processing system

Info

Publication number
FR1422913A
FR1422913A FR991221A FR991221A FR1422913A FR 1422913 A FR1422913 A FR 1422913A FR 991221 A FR991221 A FR 991221A FR 991221 A FR991221 A FR 991221A FR 1422913 A FR1422913 A FR 1422913A
Authority
FR
France
Prior art keywords
data processing
processing system
simplified data
simplified
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR991221A
Other languages
French (fr)
Inventor
Serge Delaigue
Rene Rauche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
CSF Compagnie Generale de Telegraphie sans Fil SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSF Compagnie Generale de Telegraphie sans Fil SA filed Critical CSF Compagnie Generale de Telegraphie sans Fil SA
Priority to FR991221A priority Critical patent/FR1422913A/en
Priority to GB4275865A priority patent/GB1133712A/en
Application granted granted Critical
Publication of FR1422913A publication Critical patent/FR1422913A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/017Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising using recirculating storage elements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
FR991221A 1964-10-13 1964-10-13 Simplified data processing system Expired FR1422913A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR991221A FR1422913A (en) 1964-10-13 1964-10-13 Simplified data processing system
GB4275865A GB1133712A (en) 1964-10-13 1965-10-08 Simplified data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR991221A FR1422913A (en) 1964-10-13 1964-10-13 Simplified data processing system

Publications (1)

Publication Number Publication Date
FR1422913A true FR1422913A (en) 1966-01-03

Family

ID=8840211

Family Applications (1)

Application Number Title Priority Date Filing Date
FR991221A Expired FR1422913A (en) 1964-10-13 1964-10-13 Simplified data processing system

Country Status (2)

Country Link
FR (1) FR1422913A (en)
GB (1) GB1133712A (en)

Also Published As

Publication number Publication date
GB1133712A (en) 1968-11-13

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