FI91696C - Method for making a rate adjustment decision at a node in a digital data communication system - Google Patents
Method for making a rate adjustment decision at a node in a digital data communication system Download PDFInfo
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- FI91696C FI91696C FI922992A FI922992A FI91696C FI 91696 C FI91696 C FI 91696C FI 922992 A FI922992 A FI 922992A FI 922992 A FI922992 A FI 922992A FI 91696 C FI91696 C FI 91696C
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/073—Bit stuffing, e.g. PDH
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Description
9169691696
MenetelmS tasausp&éttiksen aikaansaamiseksi digitaalisen tietoliikennejarjestelman solmupisteessaMethod for obtaining equalization at a node in a digital communication system
KeksinnOn kohteena on oheisen patenttivaatimuksen 1 5 johdanto-osan mukainen menetelma tasauspaatOksen aikaansaamiseksi digitaalisen tietoliikennejarjestelman solmupisteessa.The invention relates to a method according to the preamble of appended claim 1 for providing an equalization solution at a node of a digital communication system.
Digitaalisen siirtoverkon solmupisteissa haaroite-taan osa siirtokapasiteetista kyseiselle asemalle loppu-10 osan jatkaessa seuraavalle siirtotielle. Nykyiselia tek-niikalla toteutettuna siirtokehyksen kanavat puretaan solmupisteessa haaroittuvan kapasiteetin tasolle ja haaroitus seka lapikytkenta toteutetaan tyypillisesti kaapeloimalla halutut kanavat rinnakkaismuodossa siirtolaitteelta toi-15 selle. Kaikille kanaville on siis solmupisteessa jokai-sessa siirtolaitteessa oma liitantansa, joka on tyypillisesti G.703-standardin mukainen. Nain toteutettuna solmupisteissa on paljon liitantdja ja kaapelointia, mika tekee tailaisesta ratkaisusta kalliin. Tama ongelma on 20 valtetty FI-patenttihakemuksessa 904833 esitetylia tois-tinasemalla, jossa haaroittumattomia kanavia ei pureta rinnakkaismuotoisiksi, vaan ne viedaan sarjamuotoisena siirtolaitteelta toiselle toistinvayiaa pitkin. Viimemai-nittu toistinasema onkin esilia olevan keksinnOn eras 25 edullinen kayttttkohde, joskin keksintoa voidaan kayttaa myOs edelia kuvatussa toistinasemassa, jossa seka haaroitus etta lapikytkenta tehdaan rinnakkaismuodossa, samoin kuin missa tahansa muussa solmupisteessa, jossa suorite-taan tasauksia puskuroimalla dataa puskurimuistiin.At the nodes of a digital transmission network, part of the transmission capacity is branched to that station as the remaining 10 continue to the next transmission path. Implemented with the current technique, the channels of the transmission frame are decoupled at the node level to the level of branching capacity, and the branching and patching are typically implemented by cabling the desired channels in parallel from one transmission device to another. Thus, for each channel, each transmission device has its own interface at the node, which is typically in accordance with the G.703 standard. Implemented this way, there is a lot of connection and cabling in the nodes, which makes such a solution expensive. This problem has been overcome in the repeater station disclosed in FI patent application 904833, in which unbranched channels are not disassembled in parallel, but are passed in series from one transmission device to another along the repeater. The latter repeater station is therefore a preferred application of the present invention, although the invention can be used in the repeater station described above in myOs, where both branching and patching are performed in parallel, as well as at any other node where equalization is buffered by buffering.
30 Toistinaseman toistava siirtolaite lukkiutuu siir- totielta tulevaan kehykseen ja purkaa kanavat joustaviin puskurimuisteihin, joita on yhta monta kuin siirtokehyk-sessa on kanavia. Joustavista puskurimuisteista dataa lue-taan lahetyspuolen kehyslaskurin tahdissa, ja se multi-35 pleksataan uudeksi siirtokehykseksi.The repeater's repeater's transmission device locks into the frame coming from the transmission path and decrypts the channels into flexible buffer memories as many as there are channels in the transmission frame. Vista flexible buffer memories data read-in lahetyspuolen frame counter at pace, and multi-multiplexed into a new 35 transmission frames.
2 916962,91696
Koska siirtotielta tulevassa kehyksessa on varsi-naisen datan lisaksi mybs muita bitteja (ns. kehysbitte-ja), esim. kehyslukitussignaalin ja huoltopuhelinsignaalin bitit, ei joustaviin puskurimuisteihin kirjoiteta tai 5 niista lueta tasaisella nopeudella, vaan datan kirjoituk-sessa tai luvussa on aikarasterissa tarkasteltuna eri pi-tuisia "aukkoja", jotka aiheutuvat naista kehysbiteista.Since the frame coming from the transmission path has mybs other bits (so-called frame bits) in addition to the actual data, e.g. bits of the frame lock signal and the service telephone signal, the flexible buffer memories are not written or read at a different rate, but in the data write or read time. long "gaps" caused by female frame bits.
Puskurimuistiin tulevan ja sielta lahtevan bitti-virran kanavien nopeusero sovitetaan toisiinsa ns. tasauk-10 sella. Tasausmenetelma voi olla joko positiivinen tai ne-gatiivinen. (Tdssa selostuksessa on kaytetty esimerkkinS positiivista tasausta, ellei erikseen toisin mainita.) Jos lukunopeus puskurimuistista on suurempi kuin tulevan kana-van nopeus, lisataan lahtevåån signaaliin ylimaaraisia, 15 informaatiota sisaitamattOmia bitteja, ns. tasausbitteja, tamdn eron poistamiseksi (positiivinen tasaus). Jos lukunopeus puskurimuistista on pienempi kuin tulevan kanavan nopeus (kirjoitusnopeus puskurimuistiin), kaytetaan nor-maalisti tyhjan tasausbitin paikalla databittia (negatii-20 vinen tasaus). Tasaus suoritetaan yleensa kerran kehyk-sessa, ja tasauksen kayttiS ilmoitetaan tasauksen osoitus-biteilia. Jatkossa kaytetaan esimerkkina positiivista tasausta.The difference in the speed of the channels of the bit stream entering and leaving the buffer memory is matched to the so-called tasauk-10 with. The equalization method can be either positive or negative. (Positive smoothing in Example S is used in this description, unless otherwise stated.) If the read speed from the buffer memory is higher than the speed of the incoming channel, additional 15 information bits without information are added to the outgoing signal, so-called. equalization bits, to remove the tamdn difference (positive equalization). If the read speed from the buffer memory is lower than the speed of the incoming channel (write speed to the buffer memory), a data bit (negative-20 equalization) is normally used in place of the empty equalization bit. The equalization is usually performed once in a frame, and the use of the equalization is indicated by the equalization indication bit. In the future, positive equalization will be used as an example.
Nykyisin yleisesti kaytettavissa laitteissa maari-25 tetaan tasauksen tarve puskurimuistin tayttiiasteen perus-• teella vertaamalla tayttbastetta kiinteaan tasauspaatbsra- jaan. Molempien bittivirtojen ollessa edelia kuvatulla tavalla aukollisia aiheuttaa kiintea tasauspaatbsraja pus-kurin tayttttasteeseen kuitenkin suuria yhtakkisia heilah-30 teluja, jotka nakyvat ajastuksen varinana purettaessa bit-tivirta kanaviksi. Ongelmaa voidaan lieventåå suoritta-malla puskurimuistista luku tai sinne kirjoitus aukotto-malla signaalilla, mutta taildin joudutaan bittivirran kehysbiteista aiheutuvat aukot poistamaan lukemalla pusku-35 rimuistista vaihelukitulla oskillaattorilla muodostetulla 3 91696 kellolla, jota ohjataan vaiheilmaisimella, joka vertaa puskurimuistin luku- ja kirjoituslaskurien vaihetta.In commonly used devices today, the need for equalization is determined based on the degree of filling of the buffer memory by • comparing the filling base with a fixed equalization limit. However, with both bit streams as apertures as described above, the fixed equalization path limit to the buffer fill level causes large sudden oscillations that appear as a timing variation when the bit stream is decomposed into channels. The problem can be alleviated by performing a read or write to the buffer memory with a gapless signal, but the taild has to eliminate gaps caused by bitstream frame bits by reading a 3,91696 clock in the buffer memory 35 with a phase locked oscillator controlled by a phase detector.
Esilia olevan keksinnOn tarkoituksena onkin saada aikaan menetelma, jossa ajastuksen vSrinån aiheuttamat 5 ongelmat saadaan mlnlmoitua, valkka el kaytetakaan edelia kuvattuja vaihelukittuja silmukoita. Tama saavutetaan keksinnOn mukaisella menetelmaiia, jolle on tunnusomaista se, mita kuvataan ohelsen patenttivaatimuksen 1 tunnusmerkki-osassa.It is therefore an object of the present invention to provide a method in which the problems caused by the timing vSrinå can be mitigated, no matter the phase-locked loops described above. This is achieved by a method according to the invention, which is characterized by what is described in the characterizing part of the appended claim 1.
10 KeksinnOn mukalsena perusajatuksena on tehda ta- sauspaatOs puskurIn tayttOasteen perusteella kuten ennen-kin, mutta muuttaa niita arvoja, joita verrataan keskenaan tasauspaatOsvertailussa (tasauspaatOsrajaa tai tayttOasteen arvoa) siten, etta puskurimuistin keskimaarainen vai-15 hevara (eli tayttOaste) saadaan pysymaan mahdollisimman vakiona. Nain tasauspaatOksia saadaan syntymaan mahdollisimman tasaisesti, jolloin tasauksesta johtuva varina on niin suurella taajuudella, etta se suodattuu pois kanavaa purettaessa joustavan puskurin silmukkasuodattimen ansios-20 ta.The basic idea according to the invention is to equalize on the basis of the buffer filling level as before, but to change the values which are compared with each other in the equalization comparison (equalization limit or filling level value) so that the average or 15 hew of the buffer memory is obtained. In this way, the equalization pairs are created as evenly as possible, so that the Varina due to the equalization is at such a high frequency that it is filtered out when the channel is discharged thanks to the loop filter of the flexible buffer.
Seuraavassa keksintOå selitetaan tarkemmin viitaten oheisten piirustusten mukaisiin esimerkkeihin, joissa kuvio 1 esittaa erasta digitaalisen siirtoverkon toistinasemaa, jossa voidaan kayttaa keksinnOn mukaista 25 menetelmaa, kuvio 2 esittaa keksinnOn ensimmaisen suoritusmuo-don mukaista ratkaisua kuvion 1 mukaisessa toistinasemas-sa, kuvio 3 esittaa erasta toistinaseman siirtolait-30 teessa kaytettavaa kehysrakennetta, kuvio 4 esittaa joustavan puskurimuistin vaihekayt-taytymista, kun kaytetaan tunnettua kiinteaa tasauspaatOsrajaa lahetys- ja vastaanottosuunnan kehysten ollessa samassa vaiheessa, 35 4 91696 kuvio 5 esittaa joustavan puskurimuistin vaihekayt-taytymista, kun kaytetaan tunnettua kiinteaa tasauspaa-tOsrajaa lahetys- ja vastaanottosuunnan kehysten ollessa keskenaan eri vaiheessa, 5 kuvio 6 esittaa tasauspaatOsrajojen maaraamista seka joustavan puskurimuistin vaihekayttaytymista keksin-ηΰη mukaisella dynaamisella tasauspaatOsrajalla lahetys-ja vastaanottosuunnan kehysten ollessa samassa vaiheessa, kuvio 7 esittaa joustavan puskurimuistin vaihekayt-10 taytymista keksinnOn mukaisella dynaamisella tasauspaatds-rajalla lahetys- ja vastaanottosuunnan kehysten ollessa keskenaan eri vaiheessa, ja kuvio 8 esittaa keksinnOn toisen suoritusmuodon mu-kaista ratkaisua kuvion 1 mukaisessa toistinasemassa.The invention will now be described in more detail with reference to the examples according to the accompanying drawings, in which Fig. 1 shows a digital transmission network repeater station using the method according to the invention, Fig. 2 shows a solution according to a first embodiment of the invention in the repeater station according to Fig. 1, Fig. 3 shows Fig. 4 shows the phase usage of the flexible buffer memory when a known fixed equalization limit is used while the transmission and reception frames are in phase, Fig. 4 shows and the reception direction frames are at different stages from each other, Fig. 6 shows the determination of equalization limits and the phase behavior of the flexible buffer memory with the dynamic equalization limit according to the invention ηΰη transmission and reception direction frame n is in phase, Fig. 7 shows the phase operation of the flexible buffer memory at the dynamic equalization limit according to the invention with the transmission and reception direction frames at different stages, and Fig. 8 shows a solution according to the second embodiment of the invention in the repeater according to Fig. 1.
15 Kuviossa 1 on esitetty digitaalisen tietoliikenne- jarjestelman solmupisteena toimiva toistinasema, jolla kaytetaan keksinnOn mukaista menetelmaa. Toistinasemalla on kahden siirtotien, tassa tapauksessa radioteiden A ja B, vaiissa siirtolaitteet 11 ja 12, jotka ovat tåsså ta-20 pauksessa radiolinkkeja, joiden antenneja on merkitty vii-temerkeilia 11a ja 12a. Siirtoteilta A ja B tulee tois-tinasemalle esim. TDMA- (Time Division Multiple Access) aikamultipleksattuja kanavia, joista haaroittuvat kanavat C puretaan datasiirtokehyksistS&n demultipleksoimalla ne 25 haaroittuvien kanavien hierarkiatasolle. Haaroittuvat kanavat C johdotetaan sen jSlkeen esim. tavanomaisen G.703-liitannfln kautta tiedonsiirtoverkon sen haaran siirto-laitteelle (ei esitetty), johon mainitut kanavat on tar-koitettu.Figure 1 shows a repeater station serving as a node of a digital communication system using the method according to the invention. The repeater station has two transmission paths, in this case radio paths A and B, silent transmission devices 11 and 12, which in this case are radio links, the antennas of which are marked with reference signals 11a and 12a. Transmission paths A and B provide the repeater station with e.g. TDMA (Time Division Multiple Access) time multiplexed channels, from which the branch channels C are decompressed from the data transmission frames S & n by demultiplexing them to the hierarchical level of the 25 branch channels. The branched channels C are then wired, e.g. via a conventional G.703 interface, to the transmission device (not shown) of the branch of the communication network to which said channels are intended.
30 Haaroittumattomat kanavat eli suoraan siirtotielta .. A siirtotielle B (tai painvastoin) siirtyvat kanavat vie- daan siirtolaitteelta 11 (tai vastaavasti siirtolaitteelta 12) sarjamuotoisena siirtolaitteelle 12 (tai vastaavasti siirtolaitteelle 11) toistinvayiaa 13 pitkin.Unbranched channels, i.e. directly from the transmission path A, the channels moving to the transmission path B (or vice versa) are fed from the transmission device 11 (or from the transmission device 12, respectively) in series to the transmission device 12 (or to the transmission device 11, respectively) along the repeater line 13.
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5 91696 TSta digitaalisen siirtoverkon solmupisteena toimi-vaa toistinasemaa on kuvattu edelia mainitussa FI-patent-tihakemuksessa 904833, johon viitataan tarkemman kuvauksen suhteen.A repeater station serving as a node in a digital transmission network of 5,91696 TS is described in the aforementioned FI patent application 904833, which is referred to for a more detailed description.
5 Kuviossa 2 on esitetty keksinnOn mukaisen menetel- man ensimmaisen suoritusmuodon toteutusta kuvion 1 mukai-sella toistinasemalla, jossa siirtokehys viedaan toistin-vayiaa 13 pitkin sellaisenaan sarjamuotoisena siirtolait-teelta 11 siirtolaitteelle 12. Tassa esityksessa tarkas-10 tellaan vain siirtosuuntaa vasemmalta oikealle; toinen siirtosuunta on toiminnaltaan samanlainen. Siirtolaitteen 12 sisaanmenossa oleva, kanaville yhteinen kehysohjainyk-sikkd 18 lukkiutuu sisaantulevaan kehykseen, poistaa ta-sauksen ja purkaa kehyksen kanavat kanavakohtaisten pusku-15 riyksikttiden 17 joustaviin puskurimuisteihin 20. Pusku-riyksikOita on siis yhta monta kuin siirtoyhteydelia on kanavia. Siirtotielta A tulevilta kanavilta ei vaadita synkronisuutta, vaan ne voivat olla plesiokronisia. Jokai-nen puskuriyksikkO kasittaa, paitsi joustavan puskurimuis-20 tin 20, myds siihen liittyvSn kirjoituslaskurin 19, joka ohjaa puskurimuistiin kirjoitusta ja lukulaskurin 22, joka ohjaa puskurimuistista lukua. Aina, kun tietyn kanavan bitti on vuorossa kehyksessS, kirjoitetaan bitti téman kanavan puskuriyksikOn joustavaan puskurimuistiin 20 kir-25 joituslaskurin 19 osoittamaan paikkaan ja annetaan kirjoituslaskurin askeltaa yhden askeleen eteenpain. Vastaa-vasti lahetyspuolen kehyslaskurin 26 tahdissa luetaan da-taa joustavasta puskurimuistista 20 lukulaskurin 22 osoit-tamasta paikasta. Aina, kun puskurimuistista luetaan bit-30 ti, valitaan multiplekserilia 21 kyseisen kanavan luku-ja kirjoituslaskurien lukemat summaimelle 23, joka laskee kirjoituslaskurin ja lukulaskurin erotuksen E eli vaiheva-ran kyseisellS hetkelia. Tata vaihevaraa E verrataan kom-paraattorilla 24 ennalta maårattyyn tasauspaatdsrajaan L, 35 joka saadaan tasauspaatdsrajamuistilta 25. Vertailun tulos 6 91696 syOtetaan kehys- ja settilaskurille 26, joka ohjaa kehys-multiplekseria 27 vertailun perusteella. Jos vaihevara E on esim. pienempi kuin tasauspåatOsraja, tehdaan tasaus-paatOs eli kyseisen kanavan seuraavan tasausbitin kohdal-5 la puskurimuistista 20 ei lueta bittia kehysmultiplekse-rille 27, jolloin vaihevara kasvaa yhdelia bitilia (posi-tiivinen tasaus). TasauspaatOksia ei vaittamatta tehda joka kerta puskurimuistista luettaessa. Kirjoitus- ja lukul askur it pyGrahtavat ympari tultuaan joustavan puskuri-10 muistin loppuun. Kehyslaskurien 19 ja 26 kehysten ei tar-vitse olla samoja, vaan kapasiteetti voi vaihtua toistin-asemalla. Siirtotielle B lahteva kehys kootaan kehysmulti-plekserissa 27, jonka sisaanmenoihin luetaan dataa kanava-kohtaisista puskurimuisteista 20.Fig. 2 shows an implementation of a first embodiment of the method according to the invention at the repeater station according to Fig. 1, in which the transmission frame is passed along the repeater slot 13 as such in series from the transmission device 11 to the transmission device 12. Only the transmission direction is checked from left to right; the second direction of transmission is similar in function. The channel-common frame controller unit 18 at the input of the transfer device 12 locks into the incoming frame, equalizes, and decompresses the frame channels into the flexible buffer memories 20 of the channel-specific buffer units 15. The buffer units thus have as many channels as there are transmission links. Channels coming from transmission path A are not required to be synchronous, but may be plesiochronous. Each buffer unit, except the flexible buffer memory 20, has an associated write counter 19 which controls write to the buffer memory and a read counter 22 which controls a read from the buffer memory. Whenever a bit of a particular channel is in turn in frame S, the bit is written to the flexible buffer memory 20 of that channel's buffer unit 20 at the position indicated by the write counter 19 and the write counter is allowed to step one step forward. Reply accordingly lahetyspuolen frame counter 26 is read pace da-TAA elastic buffer memory 20 read counter 22 from ADDRESS-tamasta. Whenever bit-30 ti is read from the buffer memory, the multiplexer 21 selects the read and write counters of that channel for the adder 23, which calculates the difference E of the write counter and the read counter, i.e. the phase margin at the respective moments. This phase margin E is compared by a comparator 24 to a predetermined equalization limit L, 35 obtained from the equalization limit memory 25. The result of the comparison 6 91696 is fed to a frame and set counter 26 which controls the frame multiplexer 27 based on the comparison. If, for example, the phase margin E is smaller than the equalization decision limit, an equalization decision is made, i.e. at the next equalization bit of the channel in question, 5 bits from the buffer memory 20 are not read to the frame multiplexer 27, increasing the phase margin by one bit (positive equalization). Equalization pairs are not necessarily made every time the buffer memory is read. The write and read counters rotate around when the flexible buffer-10 memory runs out. The frames of the frame counters 19 and 26 need not be the same, but the capacity may change at the repeater station. The frame output to the transmission path B is assembled in a frame multiplexer 27, the inputs of which read data from channel-specific buffer memories 20.
15 Kuvioon 2 palataan viela jaijempana kuvion 6 seli- tyksen jaikeen.Returning to Figure 2 further, the verse of the description of Figure 6 is shown.
Kuviossa 3 on esitetty eraan siirtokehyksen raken-ne. Esimerkissa on kyseessa 2*2 Mbit/s- kapasiteetin omaa-vassa siirtolaitteessa (radiolinkissa) kaytetty kehys.Figure 3 shows the structure of a transmission frame. The example is a frame used in a transmission device (radio link) with a capacity of 2 * 2 Mbit / s.
20 Esimerkki vastaa periaatteessa muuten kaytannbn tilannet-ta, mutta yksinkertaisuuden ja selvyyden vuoksi kehyksen pituutta on lyhennetty. Koko kehys on jaettu N kappalee-seen ns. setteja, jotka on esitetty kuviossa allekkain.20 The example corresponds in principle to the otherwise usable situation, but for the sake of simplicity and clarity, the length of the frame has been shortened. The whole frame is divided into N pieces in the so-called sets shown in the figure below.
Tassa tapauksessa N=8, ja setit on numeroitu nollasta 25 seitsemaan. Setin jarjestysnumero on esitetty kuvion 3 vasemmassa sarakkeessa. Kanavien dataa on merkitty nume-roilla (1 tai 2) ja kehysbitteja viitemerkilia K. Kanavien data tulee perakkain siten, etta ykkbselia merkitty data kuuluu ensimmaiseen 2 Mbit/s- jarjestelmaan (ensimmainen 30 kanava) ja kakkosella merkitty data toiseen 2 Mbit/s- jarjestelmaan (toinen kanava). Jokaisessa setissa on yhtå monta databittia, mutta setin alussa olevien kehysbittien K maara vaihtelee nollasta kahdeksaan.In this case, N = 8, and the sets are numbered from zero to 25 to seven. The sequence number of the set is shown in the left column of Figure 3. The channel data is denoted by numbers (1 or 2) and the frame bits by the reference character K. The channel data is consecutive so that the data denoted by one belongs to the first 2 Mbit / s system (the first 30 channels) and the data denoted by the second to the second 2 Mbit / s. system (second channel). Each set has an equal number of data bits, but the number of frame bits K at the beginning of the set varies from zero to eight.
Kuviossa 4 on esitetty joustavan puskurimuistin 35 vaihevara eli tayttttaste yhden kehyksen ajalta tunnetussaFigure 4 shows the phase margin of the flexible buffer memory 35, i.e. the filling level for one frame in a known
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7 91696 tapauksessa, jossa seka puskurimuistiin kirjoitus etta sielta luku tapahtuu aukollisella kellolla ja tasauspaa-tOsraja on kiintea 5 bittia. Kuviot 4 - 7 on piirretty kayttaen esimerkkina kuvion 3 kehysta, ja ne patevat kum-5 malle tahansa kehyksen kahdesta kanavasta. Vaaka-akselilla on esitetty aikaa siten, etta yksi asteikkovaii vastaa yhta settia. Kuvion 3 mukaisen kehyksen settien jarjestys-numerot on merkitty vaaka-akselille. Pystyakselilla esite-taan vaihevaraa E siten, etta yksi asteikkovaii vastaa 10 yhta bittia. Ylempi kayra WR vastaa tassa tapauksessa puskurimuistiin tapahtuvaa kirjoitusta, ja alempi kayra RD sielta tapahtuvaa lukua. Kayrien vaiiin jaava alue, jota on merkitty nuolilla F on puskurin vaihevara kullakin het-kelia.7 91696 in the case where both the write to the buffer memory that the reading from there takes place with an aperture clock and the equalization limit is fixed at 5 bits. Figures 4 to 7 are drawn using the frame of Figure 3 as an example, and are patched on either of the two channels in the frame. The time is shown on the horizontal axis so that one scale step corresponds to one set. The sequence numbers of the sets of the frame according to Figure 3 are marked on the horizontal axis. On the vertical axis, the phase margin E is represented such that one scale step corresponds to 10 equal bits. In this case, the upper Kayra WR corresponds to the writing to the buffer memory, and the lower Kayra RD corresponds to the reading from there. The area of the curves marked by the arrows F is the phase margin of the buffer at each instant.
15 Kuviossa 4 lahdetaan liikkeelle kohdasta, jossa lahetys- ja vastaanottosuunnan kehykset ovat samassa vai-heessa ja puskurin vaihevara E on 5 bittia. Koska kehykset ovat samassa vaiheessa, osuvat aukot luvussa ja kirjoituk-sessa aina samoihin kohtiin ja vaihevara sailyy koko ajan 20 viitena bittina. Kuviosta 3 ja 4 havaitaan, kuinka vaihe muuttuu aina kehysbittien kohdalla. Esim. setissa nolla tulee kanavaa kohti kolme kehysbittia, ja setissa kolme nelja kehysbittia (kuvio 3), jolloin tapahtuu vastaavan suuruinen muutos vaiheessa (kuvio 4).Figure 4 starts at the point where the frames of the transmission and reception directions are in the same phase and the phase margin E of the buffer is 5 bits. Since the frames are in the same phase, the gaps in the chapter and the writing always hit the same places and the phase margin remains at 20 reference bits at all times. Figures 3 and 4 show how the phase always changes for the frame bits. For example, in the set zero comes three frame bits per channel, and in the set three four frame bits (Fig. 3), whereby a correspondingly large change in phase takes place (Fig. 4).
25 Lahetys- ja vastaanottopuolen kehyslaskurit toimi- vat eri kelloilla, eika naiden kellojen tarvitse olla toi-siinsa nahden synkroniset. Tasta johtuen lahetys- ja vastaanottosuunnan kehykset liukuvat toisiinsa nahden. Ku-vioon 5 on piirretty tilanne, jossa on edelleen kiintea 30 tasauspaatOsraja 5 bittia, mutta kehykset ovat liukuneet hieman toisiinsa nahden. Koska tasauspaatOsraja on 5 bit-tia, pitaa tasausjarjestelma huolen siita, ettei vaihevara paase pienemmaksi kuin viisi bittia. Kuvasta 5 havaitaan, etta puskurin keskimaarainen vaihevara on kasvanut huomat-35 tavasti, ja myOs tasauksia tulee useita kertoja perakkain.25 the transmitting and receiving side frame counters function as different clocks, instead of the bells need to be to one another with respect to synchronous. Due to this, the frames of the transmission and reception direction slide relative to each other. Figure 5 shows a situation where there is still a fixed 30 equalization limit 5 bits, but the frames have slipped slightly relative to each other. Since the justification decision limit is 5 bits, keeping tasausjarjestelma concerns that the phase margin Get access to less than five bits. It can be seen from Figure 5 that the average phase margin of the buffer has increased considerably, and myOs equalizations occur several times in a row.
• 8 91696• 8,91696
Kehysten liukuessa toisiinsa nahden hitaasti vaihtelee puskurin keskimSåråinen vaihevara huomattavasti, eika ta-sauspaatOksia synny tasaisesti, vaan vaiilia tasataan useita kertoja perakkain ja vålilia taas tasauksia syntyy 5 harvoin.As the frames slide relative to each other, the average phase margin of the buffer varies considerably, and no equalization is created evenly, but the equalization is repeated several times in succession and the equalization is seldom equal.
Kuviossa 6 on esitetty vastaava tilanne keksinnOn mukaisella dynaamisella tasauspååtOsrajalla toteutettuna. KeksinnOn ensimmaisen suoritusmuodon mukaisesti tasauspaa-tOsrajaa muutetaan siirtotielle lahetettavan kehyksen vai-10 heen mukaan seuraamalla, mika kehyksen setti on kulloinkin lahetysvuorossa. Kuviossa 6 on esimerkkina tilanne, jossa setin nolla tasauspaatOsraja on 5 bittia, setin yksi tasauspaatOsraja 4 bittia, setin kaksi tasauspaatOsraja kol-me bittia, setin kolme tasauspaatOsraja kuusi bittia, se-15 tin nelja tasauspaatOsraja viisi bittia, setin viisi ta-sauspaatOsraja nelja bittia, setin kuusi tasauspaatOsraja nelja bittia, ja setin seitseman tasauspaatOsraja kolme bittia. Esimerkissa esitetyt tasauspaatOsrajat on saatu siten, etta puskurimuistista tapahtuvaa lukua esittavan 20 vaihekayran RD paatepisteiden kautta piirretylta suoralta 60 mitattuun vaihevaraan on lisatty kiintea 2 bitin lisa-vara ja saatu tulos on pyOristetty ylbspain. Siten esim. setin nolla kohdalta mitattuun vaihevaraan x=2,5 bittia on lisåtty 2 bittia ja lopputulos 4,5 bittia on pyOristetty 5 25 bitiksi. Vastaavasti saadaan esim. setille kolme vaiheva-raksi (3,5 + 2) bittia eli pyOristettyna 6 bittia.Figure 6 shows a corresponding situation implemented with a dynamic equalization end boundary according to the invention. According to a first embodiment of the invention, the equalization limit is changed according to the phase of the frame to be transmitted on the transmission path by monitoring which set of frames is in each transmission. Figure 6 shows by way of example a situation where the set zero equalization limit 5 bits, the set one equalization limit 4 bits, the set two equalization limit three bits, the set three equalization limit six bits, the set 15 equalization limit five bits and the set five bits , a set of six equalizers with a limit of four bits, and a set of seven equalizers with a limit of three bits. The equalization decision limits shown in the example are obtained by adding a solid 2-bit Lisa margin to the phase margin measured from the line 60 drawn through the end points of the 20 phase curves RD representing the number from the buffer memory, and the result is rounded up. Thus, for example, 2 bits have been added to the phase margin x = 2.5 bits measured at zero in the set, and the result 4.5 bits has been rounded to 5 25 bits. Correspondingly, for example, three phase (3.5 + 2) bits are obtained for the set, i.e. 6 bits rounded.
Kuviossa 2 esitetyssa laiterakenteessa toimii ke-hys- ja settilaskurin 26 settilukema osoitteena tasauspaa-tOsmuistille 25, jonka osoitteessa 0 on siten tassa esi-30 merkkitapauksessa tasauspaatbsraja L=5, osoitteessa 1 ta-sauspaatttsraja L=4, osoitteessa 2 tasauspaatOsraja L=3, • ♦ jne, ja osoitteessa 7 tasauspaatOsraja L=3.In the device structure shown in Fig. 2, the set reading of the frame and set counter 26 serves as an address for the equalization paus memory 25, the address 0 of which thus has an equalization limit L = 5 in the present case 30, address 1 a equalization limit L = 4, address 2 an equalization limit L = 3, • ♦ etc, and at address 7 equalization paatsO limit L = 3.
TasauspaatOsrajat L voidaan maarittaa mille tahansa siirtokehykselle vastaavasti. Koska kehysbittien paikat 35 kehyksessa tiedetaan, saadaan siita maaritettya vastaavan li 9 91696 lukulaskurin vaihekayttaytyminen eli kåyra RD, josta ta-sauspaatOsrajat voidaan maarittaa vastaavasti.Equalization limits L can be defined for any transmission frame, respectively. Since the positions of the frame bits in the frame 35 are known, the phase utilization of the read counter li 9 91696 corresponding to it is obtained, i.e. the curve RD, from which the equalization limits can be determined accordingly.
Kuviossa 7 on esitetty kuviota 6 muuten vastaava tilanne, mutta nyt lahetys- ja vastaanottokehykset liuku-5 vat toisiinsa nahden. Dynaaminen tasauspaatOsraja pitaa tassåkin tapauksessa huolen siita, etta keskimaarainen vaihevara pysyy vakiona, jolloin tasauspaatOksia syntyy tasaisesti.Fig. 7 shows a situation otherwise similar to Fig. 6, but now the transmission and reception frames slide relative to each other. The dynamic justification decision tassåkin border shall concern the case that the average phase margin remains constant so tasauspaatOksia generated evenly.
Vaikka keksintttå on edelia selostettu viitaten 10 ohelsten piirustusten mukalslin esimerkkeihin, on selvaa, ettei keksintd ole rajoittunut siihen, vaan sita voidaan muunnella monin tavoin edelia ja oheisissa patenttivaati-muksissa esitetyn keksinnOllisen ajatuksen puitteissa. Vaikka esim. edelia keksintda sovelletaan puskurimuistista 15 tapahtuvan luvun yhteydessa, on se yhta hyvin sovelletta-vissa myOs muistiin kirjoitukseen tai molempiin.Although the invention has been described above with reference to the examples of the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified in many ways within the scope of the inventive idea set forth above and in the appended claims. Although, for example, the foregoing invention is applied in conjunction with a chapter from buffer memory 15, it is equally applicable to write to myOs memory or both.
Claims (2)
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FI922992A FI91696C (en) | 1992-06-26 | 1992-06-26 | Method for making a rate adjustment decision at a node in a digital data communication system |
PCT/FI1993/000270 WO1994000935A1 (en) | 1992-06-26 | 1993-06-23 | Methods of making a justification decision in a node of a digital telecommunication system |
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FI922992A FI91696C (en) | 1992-06-26 | 1992-06-26 | Method for making a rate adjustment decision at a node in a digital data communication system |
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US4928275A (en) * | 1989-05-26 | 1990-05-22 | Northern Telecom Limited | Synchronization of asynchronous data signals |
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FI91696B (en) | 1994-04-15 |
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