FI914733A - TEST METOD OCH TEST APPARAT - Google Patents

TEST METOD OCH TEST APPARAT Download PDF

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Publication number
FI914733A
FI914733A FI914733A FI914733A FI914733A FI 914733 A FI914733 A FI 914733A FI 914733 A FI914733 A FI 914733A FI 914733 A FI914733 A FI 914733A FI 914733 A FI914733 A FI 914733A
Authority
FI
Finland
Prior art keywords
test
arrangement
standardized
metod
apparat
Prior art date
Application number
FI914733A
Other languages
Finnish (fi)
Other versions
FI914733A0 (en
FI100829B (en
Inventor
Matti Weissenfelt
Hannu Olkkola
Original Assignee
Matti Weissenfelt
Hannu Olkkola
Tiensyrjae Kari
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matti Weissenfelt, Hannu Olkkola, Tiensyrjae Kari filed Critical Matti Weissenfelt
Priority to FI914733A priority Critical patent/FI100829B/en
Publication of FI914733A0 publication Critical patent/FI914733A0/en
Publication of FI914733A publication Critical patent/FI914733A/en
Application granted granted Critical
Publication of FI100829B publication Critical patent/FI100829B/en

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  • Tests Of Electronic Circuits (AREA)

Abstract

The invention concerns a test method and test apparatus for detection and localization of manufacturing defects in an electronic arrangement that contains test structures according to standard IEEE 1149.1, hereafter "the tested arrangement" by means of selected current diagnosis. The selected current diagnosis significantly broadens the area of application of wiring tests according to standard IEEE 1149.1 (JTAG) on component boards that contain both components with standardized test structures and traditional components without the standardized test structure. Broadening of the area of application and the increased coverage of wiring tests are based on measurement of changes in the value of the operating current that an arrangement takes from a power source by means of a computer-control test arrangement that contains a current measurement device and a control device for the test structures, when the test arrangement by means of the standardized test structure placed in the test arrangement has guided the test arrangement into a desired controlled static state or states. <IMAGE>
FI914733A 1991-10-08 1991-10-08 Test method and test apparatus FI100829B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FI914733A FI100829B (en) 1991-10-08 1991-10-08 Test method and test apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI914733A FI100829B (en) 1991-10-08 1991-10-08 Test method and test apparatus

Publications (3)

Publication Number Publication Date
FI914733A0 FI914733A0 (en) 1991-10-08
FI914733A true FI914733A (en) 1993-04-09
FI100829B FI100829B (en) 1998-02-27

Family

ID=8533253

Family Applications (1)

Application Number Title Priority Date Filing Date
FI914733A FI100829B (en) 1991-10-08 1991-10-08 Test method and test apparatus

Country Status (1)

Country Link
FI (1) FI100829B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI110034B (en) * 2000-02-11 2002-11-15 Elektrobit Oy Test arrangement and test procedure
US7206547B2 (en) 2003-09-30 2007-04-17 Elektrobit Oy Method of testing electric circuit, and arrangement

Also Published As

Publication number Publication date
FI914733A0 (en) 1991-10-08
FI100829B (en) 1998-02-27

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Legal Events

Date Code Title Description
PC Transfer of assignment of patent

Owner name: ELEKTROBIT TESTING OY

Free format text: ELEKTROBIT TESTING OY

PC Transfer of assignment of patent

Owner name: ELEKTROBIT SYSTEM TEST OY

Free format text: ELEKTROBIT SYSTEM TEST OY