ES8303741A1 - Perfeccionamientos en sistemas multiprocesadores de datos. - Google Patents

Perfeccionamientos en sistemas multiprocesadores de datos.

Info

Publication number
ES8303741A1
ES8303741A1 ES509892A ES509892A ES8303741A1 ES 8303741 A1 ES8303741 A1 ES 8303741A1 ES 509892 A ES509892 A ES 509892A ES 509892 A ES509892 A ES 509892A ES 8303741 A1 ES8303741 A1 ES 8303741A1
Authority
ES
Spain
Prior art keywords
memory
board
bus
processor
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES509892A
Other languages
English (en)
Other versions
ES509892A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Publication of ES8303741A1 publication Critical patent/ES8303741A1/es
Publication of ES509892A0 publication Critical patent/ES509892A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

SISTEMA MODULAR INTEGRADO DE PROCESO DE DATOS Y TEXTOS. CADA SISTEMA ESTA CONSTITUIDO POR: UNA LINEA DE TRANSMISION COAXIAL (15); UNA PLURALIDAD DE NODOS (10), CADA UNO DE LOS CUALES COMPRENDE A SU VEZ UN BUS DE CONDUCTORES MULTIPLES PARA TRANSPORTAR SEÑALES DE DATOS Y DIRECCIONES, UN PROCESADOR CONECTADO AL BUS, Y UN MULTIPLEXOR EN SERIE QUE PROPORCIONA VARIAS PUERTAS DE ENTRADA-SALIDA; Y VARIOS DISPOSITIVOS DE ENTRADA-SALIDA (12) CONECTADOS A LAS RESPECTIVAS PUERTAS. EN CADA NODO DE LA LINEA COAXIAL HAY CONECTADA AL MENOS UNA PUERTA DE ENTRADA-SALIDA.
ES509892A 1981-02-25 1982-02-25 Perfeccionamientos en sistemas multiprocesadores de datos. Granted ES509892A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US23804881A 1981-02-25 1981-02-25

Publications (2)

Publication Number Publication Date
ES8303741A1 true ES8303741A1 (es) 1983-02-01
ES509892A0 ES509892A0 (es) 1983-02-01

Family

ID=22896287

Family Applications (1)

Application Number Title Priority Date Filing Date
ES509892A Granted ES509892A0 (es) 1981-02-25 1982-02-25 Perfeccionamientos en sistemas multiprocesadores de datos.

Country Status (6)

Country Link
EP (1) EP0073239A1 (es)
CA (1) CA1184310A (es)
ES (1) ES509892A0 (es)
GB (2) GB2107906B (es)
IT (1) IT1149773B (es)
WO (1) WO1982002965A1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484273A (en) * 1982-09-03 1984-11-20 Sequoia Systems, Inc. Modular computer system
FR2551282B1 (fr) * 1983-08-30 1994-05-13 Canon Kk Systeme de traitement d'image
FR2551236B1 (fr) * 1983-08-30 1990-07-06 Canon Kk Systeme de traitement d'image
US4731750A (en) * 1984-01-04 1988-03-15 International Business Machines Corporation Workstation resource sharing
GB2175421B (en) * 1985-05-13 1989-11-29 Singer Link Miles Ltd Computing system
GB2191612A (en) * 1986-06-11 1987-12-16 Ibm Display terminal
US5093913A (en) * 1986-12-22 1992-03-03 At&T Laboratories Multiprocessor memory management system with the flexible features of a tightly-coupled system in a non-shared memory system
DE3874517T2 (de) * 1988-01-22 1993-04-08 Ibm Abtasterschnittstelle fuer leitungsadapter einer uebertragungssteuerung.
EP0325080B1 (en) * 1988-01-22 1994-04-20 International Business Machines Corporation Protocol and apparatus for the selective scanning of a plurality of lines connected to a communication device
GB2206225A (en) * 1988-08-01 1988-12-29 Feltscope Ltd Point of sale terminals microcomputer system
EP0562251A2 (en) * 1992-03-24 1993-09-29 Universities Research Association, Inc. Parallel data transfer network controlled by a dynamically reconfigurable serial network

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916383A (en) * 1973-02-20 1975-10-28 Memorex Corp Multi-processor data processing system
US4030072A (en) * 1974-12-18 1977-06-14 Xerox Corporation Computer system operation and control
US4253146A (en) * 1978-12-21 1981-02-24 Burroughs Corporation Module for coupling computer-processors
US4245306A (en) * 1978-12-21 1981-01-13 Burroughs Corporation Selection of addressed processor in a multi-processor network
US4253144A (en) * 1978-12-21 1981-02-24 Burroughs Corporation Multi-processor communication network
US4240143A (en) * 1978-12-22 1980-12-16 Burroughs Corporation Hierarchical multi-processor network for memory sharing

Also Published As

Publication number Publication date
EP0073239A1 (en) 1983-03-09
GB8423510D0 (en) 1984-10-24
GB2107906B (en) 1985-10-09
IT8219853A0 (it) 1982-02-25
IT1149773B (it) 1986-12-10
GB2144892A (en) 1985-03-13
ES509892A0 (es) 1983-02-01
GB2107906A (en) 1983-05-05
CA1184310A (en) 1985-03-19
WO1982002965A1 (en) 1982-09-02

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970612