ES406107A1 - Un procedimiento para la fabricacion de modulos de multi- ples capas de circuitos integrados de vidrio y metal. - Google Patents

Un procedimiento para la fabricacion de modulos de multi- ples capas de circuitos integrados de vidrio y metal.

Info

Publication number
ES406107A1
ES406107A1 ES406107A ES406107A ES406107A1 ES 406107 A1 ES406107 A1 ES 406107A1 ES 406107 A ES406107 A ES 406107A ES 406107 A ES406107 A ES 406107A ES 406107 A1 ES406107 A1 ES 406107A1
Authority
ES
Spain
Prior art keywords
forming
layer glass
refractory substrate
integral mounting
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES406107A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES406107A1 publication Critical patent/ES406107A1/es
Expired legal-status Critical Current

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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49158Manufacturing circuit on or in base with molding of insulated base
    • Y10T29/4916Simultaneous circuit manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
ES406107A 1971-08-27 1972-08-25 Un procedimiento para la fabricacion de modulos de multi- ples capas de circuitos integrados de vidrio y metal. Expired ES406107A1 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17553071A 1971-08-27 1971-08-27
US05/175,529 US3968193A (en) 1971-08-27 1971-08-27 Firing process for forming a multilayer glass-metal module

Publications (1)

Publication Number Publication Date
ES406107A1 true ES406107A1 (es) 1976-01-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
ES406107A Expired ES406107A1 (es) 1971-08-27 1972-08-25 Un procedimiento para la fabricacion de modulos de multi- ples capas de circuitos integrados de vidrio y metal.

Country Status (7)

Country Link
US (2) US3968193A (es)
BE (1) BE787292A (es)
CA (1) CA973979A (es)
CH (1) CH542569A (es)
ES (1) ES406107A1 (es)
FR (1) FR2150923B1 (es)
GB (2) GB1366602A (es)

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Also Published As

Publication number Publication date
CH542569A (de) 1973-09-30
CA973979A (en) 1975-09-02
BE787292A (fr) 1972-12-01
FR2150923B1 (es) 1976-05-21
US3968193A (en) 1976-07-06
GB1366602A (en) 1974-09-11
FR2150923A1 (es) 1973-04-13
GB1366601A (en) 1974-09-11
US3726002A (en) 1973-04-10

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