ES2398552A1 - Neurona artificial. (Machine-translation by Google Translate, not legally binding) - Google Patents

Neurona artificial. (Machine-translation by Google Translate, not legally binding) Download PDF

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Publication number
ES2398552A1
ES2398552A1 ES201100057A ES201100057A ES2398552A1 ES 2398552 A1 ES2398552 A1 ES 2398552A1 ES 201100057 A ES201100057 A ES 201100057A ES 201100057 A ES201100057 A ES 201100057A ES 2398552 A1 ES2398552 A1 ES 2398552A1
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artificial
input
translation
machine
differential integrator
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ES2398552B1 (en
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José RUANO MOYANO
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
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  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

Artificial neuron characterized by comprising two adders connected respectively to the two inputs of a differential integrator, and this in turn to a power amplifier. (Machine-translation by Google Translate, not legally binding)

Description

NEURONA ARTIFICIAL ARTIFICIAL NEURONE

S S
El objeto de la presente invención es proporcionar un circuito electrónico que implemente una neurona artificial, que pueda suministrar grandes tecnológica, y gran estabilidad. potencias, sencillez The object of the present invention is to provide an electronic circuit that implements an artificial neuron, which can provide great technology, and great stability. powers, simplicity

ANTECEDENTES BACKGROUND

10 10
Las neuronas artificiales se utilizan actualmente en el procesado de la información, el cual tiene lugar a baja potencia. No son aptas para acometer cargas industriales, como motores eléctricos, hornos eléctricos, etc. Artificial neurons are currently used in information processing, which takes place at low power. They are not suitable for undertaking industrial loads, such as electric motors, electric ovens, etc.

DESCRIPCION DESCRIPTION
DE LA INVENCION FROM THE INVENTION

15 fifteen
La neurona artificial de la presente invención se caracteriza por comprender dos sumadores, conectados uno a la entrada negativa de un integrador diferencial y el otro a la entrada positiva de este integrador. Estando conectada la salida de este integrador diferencial a la entrada de un amplificador de potencia, donde su salida es la salida de la neurona. The artificial neuron of the present invention is characterized by comprising two adders, connected one to the negative input of a differential integrator and the other to the positive input of this integrator. The output of this differential integrator being connected to the input of a power amplifier, where its output is the output of the neuron.

20 twenty
Los sumadores comprende un nudo de resistencias, donde el borne común a todas ellas es su salida, y los otros las entradas. The adders include a knot of resistances, where the common terminal to all of them is its exit, and the others the entrances.

25 30 25 30
El integrador diferencial comprende un amplificador operacional, donde existe un condensador entre la entrada inversora y la salida de este amplificador, y una resistencia entre esta entrada y la entrada negativa del integrador diferencial. Habiendo un condensador entre la entrada no inversora del amplificador operacional y masa. Enlazándose esta entrada no inversora con la entrada positiva del integrador diferencial a través de una resistencia. The differential integrator comprises an operational amplifier, where there is a capacitor between the inverting input and the output of this amplifier, and a resistance between this input and the negative input of the differential integrator. There is a capacitor between the non-inverting input of the operational amplifier and ground. This non-inverting input is linked to the positive input of the differential integrator through a resistor.

La salida del amplificador operacional es la salida del integrador diferencial que conecta con la entrada de un amplificador de potencia. The output of the operational amplifier is the output of the differential integrator that connects to the input of a power amplifier.

S 10 S 10
Una neurona artificial así definida, su salida sería binaria, o tomaría el valor más alto o el más bajo en función de las entradas. Pero para conseguir, que la función de activación de esta neurona artificial sea la función identidad, en el que su salida se exprese como suma ponderada de sus entradas, establecemos una realimentación negativa, llevando la salida de la neurona a una de las entradas del sumador que conecta con la entrada negativa del integrador diferencial. An artificial neuron so defined, its output would be binary, or it would take the highest or lowest value depending on the inputs. But to achieve that the activation function of this artificial neuron is the identity function, in which its output is expressed as a weighted sum of its inputs, we establish a negative feedback, bringing the output of the neuron to one of the adder's inputs. which connects to the negative input of the differential integrator.

15 fifteen
La evolución del sistema es tal que la entrada negativa como positiva del integrador diferencial se hacen iguales, y de ahí que la salida se pueda expresar como suma ponderada de sus entradas. The evolution of the system is such that the negative input as positive of the differential integrator is made equal, and hence the output can be expressed as a weighted sum of its inputs.

20 twenty
El tiempo de respuesta y la estabilidad de esta neurona artificial van a depender en mucho del valor que tomen sus resistencias, Estableciéndose un dilema, pequeño o elevada estabilidad, hallar el punto óptimo. y sus condensadores. entre tiempo de respuesta que en cada caso se deberá The response time and stability of this artificial neuron will depend greatly on the value of its resistance, establishing a dilemma, small or high stability, find the optimal point. and its capacitors. between response time that in each case should be

BREVE BRIEF
DESCRIPCION DE LOS DIBUJOS DESCRIPTION FROM THE DRAWINGS

25 25
Descripción limitativos, de los dibujos mostrados como ejemplos no Limiting Description, from the drawings shown how examples no

Fig.l: Fig. L:
Diagrama de Bloques de una neurona artificial Diagram from Blocks from a neuron artificial

Fig.2:    Fig. 2:
Circuito de un integrador diferencial Circuit of a differential integrator

DESCRIPCION DESCRIPTION
DE UNA REALIZACION PREFERIDA FROM A REALIZATION PREFERRED

S S
Neurona Artificial (fig.l) caracterizada por comprender dos sumadores conectados respectivamente a las dos entradas de un integrador diferencial (ID), y este a su vez a un amplificador de potencia (AP) . Artificial Neuron (fig. 1) characterized by comprising two adders connected respectively to the two inputs of a differential integrator (ID), and this in turn to a power amplifier (AP).

10 10
El integrador diferencial (fig. 2) se caracteriza por comprender un amplificador operacional, un condensador (C) entre su salida y su entrada inversora, un condensador (C) entre su entrada no inversora y masa, una resistencia (R) entre la entrada negativa (S-) de este integrador y la entrada inversora del amplificador operacional, y una resistencia (R) entre la entrada positiva (S+) del integrador diferencial y la entrada no inversora del amplificador operacional. The differential integrator (fig. 2) is characterized by comprising an operational amplifier, a capacitor (C) between its output and its inverting input, a capacitor (C) between its non-inverting input and ground, a resistance (R) between the input negative (S-) of this integrator and the inverting input of the operational amplifier, and a resistance (R) between the positive input (S +) of the differential integrator and the non-inverting input of the operational amplifier.

15 fifteen
En los sumadores (fig.l) surgen sistemas de ecuaciones lineales, que en cada caso según la aplicación se debe resolver para hallar el valor de las resistencias. In the adders (fig.l) systems of linear equations arise, which in each case according to the application must be solved to find the value of the resistances.

Siendo una ecuación de estas, resistencia de salida (Ro) de estos dos Being an equation of these, output resistance (Ro) of these two
la que sumadores hace la iguales. which summers It does the same.

20 twenty
El tiempo de respuesta es igual a 3. C. (R+Ro) cuanto menor sea menor será su estabilidad. Por lo que se ha de encontrar un punto óptimo para cada aplicación. The response time is equal to 3. C. (R + Ro) the lower the lower its stability. So you have to find an optimal point for each application.

25 25
En varios trabajos de dan ejemplos de cálculo E S 2 O 1 O 3 O 57 4 , e te . invención del mismo para aplicaciones inventor se concretas.    In several works they give examples of calculation E S 2 O 1 O 3 O 57 4, e te. invention thereof for applications Inventor is concrete.

S S

Claims (1)

REIVINDICACIONES 1°. Neurona Artificial (1) caracterizada por comprender dos sumadores conectados respectivamente a las dos entradas de un integrador diferencial (ID), y este a su vez a un 1st. Artificial Neuron (1) characterized by comprising two adders connected respectively to the two inputs of a differential integrator (ID), and this in turn to a 10 amplificador de potencia (AP) . 10 power amplifier (AP). 2°. Neurona Artificial según reivindicación anterior, en la que el integrador diferencial (2) se caracteriza por comprender un amplificador operacional, un condensador entre su salida y su entrada inversora, un condensador 2nd. Artificial neuron according to the preceding claim, wherein the differential integrator (2) is characterized by comprising an operational amplifier, a capacitor between its output and its inverting input, a capacitor 15 entre su entrada no inversora y masa, una resistencia entre la entrada negativa (S-) de este integrador y la entrada inversora del amplificador operacional, y una resistencia entre la entrada positiva (S+) del integrador diferencial y la entrada no inversora del amplificador operacional. 15 between its non-inverting input and ground, a resistance between the negative input (S-) of this integrator and the inverting input of the operational amplifier, and a resistance between the positive input (S +) of the differential integrator and the non-inverting input of the amplifier operational.
ES201100057A 2010-04-20 2010-04-20 ARTIFICIAL NEURONE. Withdrawn - After Issue ES2398552B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES201100057A ES2398552B1 (en) 2010-04-20 2010-04-20 ARTIFICIAL NEURONE.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES201100057A ES2398552B1 (en) 2010-04-20 2010-04-20 ARTIFICIAL NEURONE.

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ES2398552A1 true ES2398552A1 (en) 2013-03-20
ES2398552B1 ES2398552B1 (en) 2014-01-30

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625752A (en) * 1994-06-17 1997-04-29 The United States Of America As Represented By The Secretary Of The Navy Artificial neural system with binary weighting by equal resistor network

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625752A (en) * 1994-06-17 1997-04-29 The United States Of America As Represented By The Secretary Of The Navy Artificial neural system with binary weighting by equal resistor network

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Genov et al.; "Dynamic MOS sigmoid array folding analog-to-digital conversion," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.51, no.1, pp. 182- 186, Jan. 2004; doi: 10.1109/TCSI.2003.821304 *
Peyton et a. "Analog Electronics with Op-Amps; A Source Book of Practical Circuits"; Cambridge University Press 12.08.1993; Colección: Electronics Texts for Engineers and Scientists; ISBN-10: 052133604X; ISBN-13: 978-0521336048 *

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