ES2062249T3 - Reloj sincronizado. - Google Patents

Reloj sincronizado.

Info

Publication number
ES2062249T3
ES2062249T3 ES90119677T ES90119677T ES2062249T3 ES 2062249 T3 ES2062249 T3 ES 2062249T3 ES 90119677 T ES90119677 T ES 90119677T ES 90119677 T ES90119677 T ES 90119677T ES 2062249 T3 ES2062249 T3 ES 2062249T3
Authority
ES
Spain
Prior art keywords
external synchronization
synchronized
shaving
clock
synchronization signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90119677T
Other languages
English (en)
Inventor
Alain Lalanne
Andre Lankar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of ES2062249T3 publication Critical patent/ES2062249T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G7/00—Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Control Of Electric Motors In General (AREA)
  • Facsimiles In General (AREA)
  • Burglar Alarm Systems (AREA)

Abstract

EL PRESENTE INVENTO CONSISTE EN UN RELOJ DE MUY GRANDE ESTABILIDAD SINCRONIZADA SOBRE UNA SEÑAL DE SINCRONIZACION EXTERNA. EL RELOJ SINCRONIZADO RECIBE VARIAS SEÑALES DE SINCRONIZACION EXTERNA (1, 2) Y COMPRENDE UNOS MEDIOS (DA, DR) PARA ELABORAR UN MANDO DE SERVOMECANISMO (8) ASOCIADO A CADA UNA DE LAS SEÑALES DE SINCRONIZACION EXTERNA. COMPRENDE IGUALMENTE UNA UNIDAD DE MANDO (UC) QUE PRODUCE LA SEÑAL DE MANDO (12) DE UN GENERADOR DE RELOJ (GH) POR SELECCION DE UNO DE LOS MANDOS DEL SERVOMECANISMO QUE SIGUE UNOS CRITERIOS DE CALIDAD.
ES90119677T 1989-10-17 1990-10-15 Reloj sincronizado. Expired - Lifetime ES2062249T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8913551A FR2653278B1 (fr) 1989-10-17 1989-10-17 Horloge synchronisee.

Publications (1)

Publication Number Publication Date
ES2062249T3 true ES2062249T3 (es) 1994-12-16

Family

ID=9386478

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90119677T Expired - Lifetime ES2062249T3 (es) 1989-10-17 1990-10-15 Reloj sincronizado.

Country Status (10)

Country Link
US (1) US5153824A (es)
EP (1) EP0423663B1 (es)
AT (1) ATE111241T1 (es)
CA (1) CA2027721C (es)
DE (1) DE69012269T2 (es)
DK (1) DK0423663T3 (es)
ES (1) ES2062249T3 (es)
FR (1) FR2653278B1 (es)
PL (1) PL284814A1 (es)
YU (1) YU79190A (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530393B1 (de) * 1991-09-02 1994-12-07 Siemens Aktiengesellschaft Verfahren und Vorrichtung zur Synchronisation einer Takteinrichtung eines Fernmeldevermittlungssystems
US5373537A (en) * 1991-09-02 1994-12-13 Siemens Aktiengesellschaft Method and apparatus for the synchronization of a clock means of a telecommunication switching system
US5440313A (en) * 1993-05-27 1995-08-08 Stellar Gps Corporation GPS synchronized frequency/time source
JP3505011B2 (ja) * 1995-06-22 2004-03-08 株式会社アドバンテスト 高精度信号発生回路
EP0821486B1 (en) * 1996-07-24 2003-09-24 STMicroelectronics S.r.l. Clock circuit with master-slave synchronisation
JP3420898B2 (ja) 1996-10-04 2003-06-30 富士通株式会社 シンクロナイゼーションメッセージ受信処理装置
JP3791983B2 (ja) * 1996-10-29 2006-06-28 富士通株式会社 シンクロナイゼーションメッセージによるアクティブリファレンスの切替え装置
JP3460118B2 (ja) * 1998-08-26 2003-10-27 富士通株式会社 同期網システムのクロック管理方法及び伝送装置
US6577232B1 (en) 1998-11-02 2003-06-10 Pittway Corporation Monopolar, synchronized communication system
US6384723B1 (en) 1998-11-02 2002-05-07 Pittway Corporation Digital communication system and method
US6538516B2 (en) * 2001-05-17 2003-03-25 Fairchild Semiconductor Corporation System and method for synchronizing multiple phase-lock loops or other synchronizable oscillators without using a master clock signal
JP2007266923A (ja) * 2006-03-28 2007-10-11 Fujitsu Ltd クロック供給装置
US8805505B1 (en) 2013-01-25 2014-08-12 Medtronic, Inc. Using telemetry downlink for real time clock calibration
US9484940B2 (en) 2013-01-25 2016-11-01 Medtronic, Inc. Using high frequency crystal from external module to trim real time clock
JP7251402B2 (ja) * 2019-08-20 2023-04-04 オムロン株式会社 制御システム、制御装置およびプログラム

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2546691B1 (fr) * 1983-05-27 1985-07-05 Cit Alcatel Base de temps asservie
US4835481A (en) * 1986-09-30 1989-05-30 Siemens Aktiengesellschaft Circuit arrangement for generating a clock signal which is synchronous in respect of frequency to a reference frequency
US4893318A (en) * 1988-01-26 1990-01-09 Computer Sports Medicine, Inc. Method for referencing multiple data processors to a common time reference
US4882739A (en) * 1988-01-26 1989-11-21 Computer Sports Medicine, Inc. Method for adjusting clocks of multiple data processors to a common time base
EP0326899A3 (de) * 1988-01-29 1990-05-30 Siemens Nixdorf Informationssysteme Aktiengesellschaft Schaltungsanordnung zur Bildung eines digitalen Taktsignals

Also Published As

Publication number Publication date
US5153824A (en) 1992-10-06
CA2027721C (fr) 1995-04-11
ATE111241T1 (de) 1994-09-15
FR2653278A1 (fr) 1991-04-19
FR2653278B1 (fr) 1995-07-21
YU79190A (sh) 1993-11-16
DK0423663T3 (da) 1994-11-14
EP0423663A1 (fr) 1991-04-24
DE69012269T2 (de) 1995-01-12
EP0423663B1 (fr) 1994-09-07
DE69012269D1 (de) 1994-10-13
PL284814A1 (en) 1991-04-22
CA2027721A1 (fr) 1991-04-18

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