ES2046984T3 - Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida. - Google Patents

Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida.

Info

Publication number
ES2046984T3
ES2046984T3 ES87202505T ES87202505T ES2046984T3 ES 2046984 T3 ES2046984 T3 ES 2046984T3 ES 87202505 T ES87202505 T ES 87202505T ES 87202505 T ES87202505 T ES 87202505T ES 2046984 T3 ES2046984 T3 ES 2046984T3
Authority
ES
Spain
Prior art keywords
voltage
manufacturing
semiconductor device
revestient
union
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES87202505T
Other languages
English (en)
Inventor
Myron Ralph Cagan
Douglas Frederick Ridley
Daniel James Belton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of ES2046984T3 publication Critical patent/ES2046984T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
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    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001Core members of the connector
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    • H01L2224/45012Cross-sectional shape
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    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
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    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

UN DISPOSITIVO SEMICONDUCTOR CONTIENE UNA CAPA DE DESAHOGO DE TENSION (46) QUE TIENE UNA TEMPERATURA DE TRANSICION DE CRISTAL POR DEBAJO DE LOS 150 (GRADOS) C. LA CAPA GENERALMENTE DESCANSA SOBRE UN SISTEMA DE INTERCONEXION ELECTRICA (12) EN EL DISPOSITIVO PERO NO SE APOYA EN LAS AREAS DE RELLENO DE LA UNION. ESTO ALIVIA SUBSTANCIALMENTE LA TENSION TERMICAMENTE INDUCIDA QUE DE OTRA MANERA PODRIA DAÑAR LOS COMPONENTES ELECTRONICOS EN EL DISPOSITIVO MIENTRAS SIMULTANEAMENTE PERMITE EL MAXIMO DE TENSION EN LOS CONDUCTORES ELECTRICOS (32 Y 34) QUE SOBRESALEN DEL REVESTIMIENTO DE EMPAQUETADO EXTERNO (48) PARA PRODUCIRSE EN LAS AREAS DE UNION QUE PUEDAN TOLERAR LA TENSION. LA CAPA SE HACE PREFERIBLEMENTE MEDIANTE DISEÑO LITOGRAFICO.
ES87202505T 1986-12-19 1987-12-14 Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida. Expired - Lifetime ES2046984T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US94426886A 1986-12-19 1986-12-19

Publications (1)

Publication Number Publication Date
ES2046984T3 true ES2046984T3 (es) 1994-02-16

Family

ID=25481096

Family Applications (1)

Application Number Title Priority Date Filing Date
ES87202505T Expired - Lifetime ES2046984T3 (es) 1986-12-19 1987-12-14 Metodo de fabricar un dispositivo semiconductor con tension de encapsulacion reducida.

Country Status (8)

Country Link
EP (1) EP0275588B1 (es)
JP (1) JP2818779B2 (es)
KR (1) KR960016238B1 (es)
CN (1) CN1014380B (es)
BR (1) BR8706895A (es)
DE (1) DE3788119T2 (es)
ES (1) ES2046984T3 (es)
HK (1) HK163795A (es)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212950A (ja) * 1988-06-30 1990-01-17 Toshiba Corp 半導体装置
NL8902018A (nl) * 1989-08-07 1991-03-01 Philips Nv Halfgeleiderinrichting.
JP3563877B2 (ja) * 1996-06-21 2004-09-08 三菱電機株式会社 半導体装置
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP3223246B2 (ja) * 1997-07-25 2001-10-29 東レ・ダウコーニング・シリコーン株式会社 半導体装置
JP2001284499A (ja) * 2000-03-09 2001-10-12 Lucent Technol Inc 半導体デバイスとその製造方法
GB0018028D0 (en) * 2000-07-24 2000-09-13 Koninkl Philips Electronics Nv Semiconductor devices and their manufacture
EP1664817A1 (en) * 2003-09-16 2006-06-07 Koninklijke Philips Electronics N.V. A method of manufacturing an electronic device and an electronic device
CN100370580C (zh) * 2004-03-29 2008-02-20 雅马哈株式会社 半导体晶片及其制造方法
WO2007052597A1 (ja) * 2005-11-02 2007-05-10 Matsushita Electric Industrial Co., Ltd. 電子部品パッケージ
CN102593190B (zh) * 2012-02-13 2015-11-25 贵州雅光电子科技股份有限公司 一种二极管
CN113517205A (zh) * 2020-04-27 2021-10-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11699663B2 (en) 2020-04-27 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme design for wafer singulation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3978578A (en) * 1974-08-29 1976-09-07 Fairchild Camera And Instrument Corporation Method for packaging semiconductor devices
JPS51147962A (en) * 1975-06-02 1976-12-18 Fairchild Camera Instr Co Method of mounting semiconductor devices
JPS5748252A (en) * 1980-09-08 1982-03-19 Nec Corp Semiconductor device and manufacture thereof
JPS5848443A (ja) * 1981-09-17 1983-03-22 Toshiba Corp 樹脂封止型半導体装置
JPS59191353A (ja) * 1983-04-15 1984-10-30 Hitachi Ltd 多層配線構造を有する電子装置
DE3327960A1 (de) * 1983-08-03 1985-02-14 Telefunken electronic GmbH, 7100 Heilbronn Halbleiteranordnung in einem isolierstoffgehaeuse

Also Published As

Publication number Publication date
HK163795A (en) 1995-10-27
EP0275588A1 (en) 1988-07-27
DE3788119D1 (de) 1993-12-16
CN1014380B (zh) 1991-10-16
DE3788119T2 (de) 1994-05-11
JP2818779B2 (ja) 1998-10-30
BR8706895A (pt) 1988-07-26
EP0275588B1 (en) 1993-11-10
CN87108334A (zh) 1988-07-13
JPS63226046A (ja) 1988-09-20
KR960016238B1 (en) 1996-12-07

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