EP4388593A1 - Procédé de séparation de composants semi-conducteurs - Google Patents

Procédé de séparation de composants semi-conducteurs

Info

Publication number
EP4388593A1
EP4388593A1 EP22764787.2A EP22764787A EP4388593A1 EP 4388593 A1 EP4388593 A1 EP 4388593A1 EP 22764787 A EP22764787 A EP 22764787A EP 4388593 A1 EP4388593 A1 EP 4388593A1
Authority
EP
European Patent Office
Prior art keywords
carrier substrate
semiconductor
separating
method step
semiconductor components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22764787.2A
Other languages
German (de)
English (en)
Inventor
Tobias DÖRSAM
Frank Dimroth
Puzant Baliozian
Armin RICHTER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP4388593A1 publication Critical patent/EP4388593A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP

Definitions

  • the invention relates to a method for dicing semiconductor components according to the preamble of claim 1 and to a semiconductor component according to claim 14.
  • a multiplicity of semiconductor components are formed on a carrier substrate and the carrier substrate is then divided in order to singulate the semiconductor components.
  • the present invention relates to a method for dicing III-V semiconductor components.
  • III-V semiconductor components have at least one functional semiconductor layer which is in the form of a III-V compound semiconductor.
  • Typical III-V semiconductor components are photovoltaic solar cells, in particular concentrator solar cells for exposure to concentrated radiation, in particular concentrated sunlight, or solar cells for signal and/or power transmission by means of laser radiation.
  • solar cells can be designed for terrestrial applications or for use in space, in particular on satellites.
  • radiation-emitting III-V semiconductor components are known, in particular light-emitting diodes.
  • wafer saws are used for a cut-off process.
  • Diamonds are typically embedded in a plastic or metal abrasive disc.
  • the abrasive sheet is moved relative to the semiconductor workpiece at a typical speed of 5 to 10 mm/s in order to divide the semiconductor workpiece along separating paths and to separate the semiconductor components. In this case, material is removed with water cooling, which leads to isolation.
  • the sawing process causes a material removal of several 100 ⁇ m width, so that a corresponding spacing of the semiconductor components on the carrier substrate is necessary and limits the area utilization.
  • the sawing process creates microcracks, which damage the electrically active layers in particular and can lead to short circuits.
  • a significant deterioration in the characteristic curves and the efficiency of the solar cells was determined due to short circuits at the edge after the sawing process.
  • the mesa trenches have a greater width than the width of the saw trench, so that there is no contact between the saw blade and the functional semiconductor layers during the subsequent isolation using wafer saws.
  • the invention is therefore based on the object of providing a method for isolating semiconductor components and a semiconductor component which requires the semiconductor components to be spaced less closely on the carrier substrate and which nevertheless avoids a significant impairment of the electronic quality of the semiconductor components due to edge damage occurring during the separating process.
  • the method according to the invention for dicing semiconductor components has the following method steps A and B:
  • method step B comprises the following method steps:
  • a method step B1 the metallic rear side contacting layer of the semiconductor components is severed along the isolating distances on the rear side of the carrier substrate and a separating trench is produced on the rear side of the carrier substrate at least in partial areas of the isolating distances.
  • the carrier substrate is severed along the isolating distances by energy input into the carrier substrate by means of laser radiation, the carrier substrate being heated below the melting temperature of the carrier substrate.
  • the method according to the invention is characterized in that in method step B2 the carrier substrate is severed along the separating paths by energy input by means of laser radiation, the carrier substrate being heated below the melting temperature of the carrier substrate.
  • the present separating method causes no or at least considerably less damage to the edge surfaces along the separating paths, in particular to the edge surfaces the functional semiconductor layers of the semiconductor components.
  • a separating trench is produced in the carrier substrate, at least in partial areas of the separating distances, in order to facilitate the subsequent separating process and to avoid breakouts.
  • the separating trench is formed in the carrier substrate with a depth of at least 5 ⁇ m in order to reduce the risk of fault lines in undesired areas.
  • step B1 laser radiation is used to sever the metallic rear-side contacting layer, with the metallic rear-side contacting layer being ablated by means of laser radiation.
  • Known devices for laser ablation can be used here, which allow processing that is gentle on the material with high accuracy.
  • both the ablation of the metal rear-side contacting layer and the creation of the separating trench take place by means of the laser radiation. This achieves a particularly process-economical method.
  • the separating trench is preferably produced by laser ablation. It is also within the scope of the invention to produce the separating trench by chemical etching or by a sawing process that does not completely sever the carrier substrate.
  • the separating trench In order to further reduce the risk of fracture lines in undesired areas, it is advantageous for the separating trench to be formed in the carrier substrate with a depth of at least 10 ⁇ m, in particular at least 30 ⁇ m, more preferably at least 50 ⁇ m. For this reason it is also advantageous that the separating trench is formed in the carrier substrate with a depth which is at least 5%, in particular at least 10%, more preferably at least 30%, in particular at least 50%, in particular at least 80% of the thickness of the carrier substrate.
  • TLS methods thermal laser separation
  • III-V semiconductor components have a high risk of irregular fracture edges during the dicing process, which can lead to damage or destruction of the III-V semiconductor devices. This applies in particular to III-V semiconductor components based on germanium.
  • the method according to the invention leads to an avoidance or at least a considerable reduction of this risk, in that in method step B1 on the rear side of the carrier substrate along the separating gaps the metallic rear-side contacting layer of the semiconductor components is removed, preferably severed and at least in partial areas of the separating gaps a separating trench on the rear side of the carrier substrate is produced.
  • the backside contacting layer of the semiconductor components is severed, in particular ablated, and the isolating gaps are created in such a way that the functional semiconductor layer of the semiconductor components, which is arranged on the front side of the carrier substrate, is not melted. This avoids an impairment of the electronic quality of the functional semiconductor layer.
  • the semiconductor components have at least one functional semiconductor layer arranged on the front side of the carrier substrate. It is within the scope of the invention that the semiconductor components have further functional semiconductor layers. In particular, it is within the scope of the invention that the carrier substrate is formed as a further functional semiconductor layer of the semiconductor components.
  • the semiconductor components have at least one pn junction. This can be formed between two functional layers which have dopings of opposite doping types. Doping types are p- and n-doping. It is also within the scope of the invention for one or more pn junctions to be formed within a functional layer.
  • a pn junction is formed in the carrier substrate on the front side of the carrier substrate, preferably in a manner known per se by means of diffusion of dopants.
  • method step B2 the energy is introduced into the carrier substrate by means of laser radiation from the rear side of the carrier substrate in order to avoid impairment of the functional semiconductor layer of the semiconductor components.
  • the generated in step B1 Separation trenches are formed with a depth that is less than the thickness of the carrier substrate, preferably less than 90%, in particular less than 80%, more preferably less than 60% of the thickness of the carrier substrate. This ensures that the separating trenches do not extend into the functional layer or, if there are a plurality of functional layers of semiconductor components, into the functional layers of the semiconductor components and lead to damage that reduces the electronic quality of the semiconductor component.
  • separating trenches are only partially formed along the separating distances in method step B1. Due to the crystal structure of the carrier substrate, in method step B2, the formation of cracks nevertheless continues along the separating gaps, even in the areas of the separating gaps in which no separating trenches were formed. Studies by the applicant show that it is advantageous for separating trenches to be formed at least at crossing points of the separating distances.
  • separating trenches In order to reduce the risk of fault lines forming in undesired areas, it is advantageous for separating trenches to be formed completely along the entire length of the separating distances in method step B1. A separating trench is thus formed in each partial area of a separating gap. In this way, the carrier substrate is divided up exclusively along separating paths at which a separating trench is also formed.
  • the isolating distances are advantageously arranged in such a way that at least subsets of the isolating distances intersect. It is therefore particularly advantageous to form separating trenches in the form of a cross (+) at least at the intersection points of the separating distances. This is particularly advantageous when the isolating distances are formed in a straight line. If all isolating distances are formed in a straight line, in a configuration that is advantageous in terms of process economy, only isolating trenches are formed at the intersection points of the isolating distances, preferably in each case in the form of a cross. It is also within the scope of the invention that some or all of the isolating distances are not formed in a straight line.
  • isolating trenches are advantageously formed at least in the non-rectilinear areas, in particular in arcuate areas of the isolating distances. This facilitates cutting through the wafer along the dividing lines and avoids deviating courses.
  • separating trenches are formed completely along the separating distances in method step B1. This significantly reduces the risk of cracks forming outside the isolating gaps in method step B2.
  • the carrier substrate is actively cooled in order to promote crack formation.
  • the active cooling takes place by means of a coolant jet, preferably by means of a coolant jet that follows the laser beam used to heat the carrier substrate.
  • a cooling liquid in particular water, is preferably used as the coolant for the coolant jet.
  • an expandable film is arranged on the front side of the semiconductor workpiece before method step B in method step A1 and after method step B in a method step C a spacing is formed between the semiconductor components by expanding the film.
  • the stretchable film is preferably arranged on the front side of the semiconductor workpiece by means of adhesive or adhesion films, which are preferably stretched over a frame.
  • other fixations for the foil can also be used, which make it possible to additionally hold the semiconductor workpiece during the process and then to create a distance between the components.
  • the side surfaces of the semiconductor components are treated in method step C, while the spatially separated semiconductor components are arranged at a distance from one another on the film.
  • the electronic quality of the semiconductor components can be increased further and/or the further processing of the semiconductor components can be simplified by also compensating for minimal damage to the side faces.
  • such protective layers in particular made of aluminum oxide, silicon oxide or silicon nitride, offer protection against environmental influences and thus a change in the semiconductor side surfaces due to corrosion, oxidation or contamination.
  • a protective layer is preferably arranged on the side faces of the semiconductor components by means of atomic layer deposition (ALD) or by means of a plasma process.
  • the protective layer on the side faces in such a way that edge passivation occurs, so that minority charge carriers recombine less in a non-radiative manner.
  • the protective layer on the side faces of the semiconductor components is preferably formed from amorphous silicon, silicon carbide (in particular when the carrier substrate is formed from germanium), from stoichiometric gallium oxides, particularly in the case of carrier substrates which have surfaces passivated with nitrogen or sulfur. It is within the scope of the invention to form a multilayer protective layer at the edges of the semiconductor components. In particular, it is advantageous to form a multilayer protective layer which has one or more of the layers from the group consisting of aluminum oxide layer and aluminum nitride layer. Depending on the method selected, when the protective layer is applied, the protective layer can also be applied on the front side and/or on the back side of the semiconductor structure.
  • the protective layer on the front or back is disadvantageous for the functioning, in particular the electronic properties and/or the efficiency of the semiconductor component. It is therefore advantageous to remove the protective layer on the front and/or rear, in particular to remove it mechanically by means of abrasion.
  • the semiconductor workpiece is provided with one or more layers between the rear side of the carrier substrate and the rear side contacting layer of the semiconductor components and/or between the front side of the carrier substrate and the functional semiconductor layer of the semiconductor components.
  • the semiconductor components can be in the form of III-V semiconductor components in a manner known per se and preferably have at least one pn junction. It is within the scope of the invention that the III-V semiconductor components have a plurality of functional semiconductor layers and in particular a plurality of pn junctions. In particular, it is within the scope of the invention for the III-V semiconductor components to be in the form of multiple solar cells.
  • the carrier substrate is preferably formed from one or more materials from the group germanium, GaAs, InP, GaSb, sapphire.
  • the carrier substrate is preferably a semiconductor wafer made of semiconductor materials of IV. or III. and V. main group formed, preferably as a germanium wafer, GaAs wafer, InP wafer or GaSb wafer.
  • the thickness of the carrier substrate is preferably in the range of 30-800 ⁇ m, particularly preferably in the range of 50-650 ⁇ m.
  • the method according to the invention is particularly suitable for forming small semiconductor components.
  • the method is therefore designed in such a way that the isolated semiconductor components on the front side Have an area of less than 100 mm 2 , in particular less than 10 mm 2 , preferably less than 3 mm 2 .
  • the semiconductor components are thus preferably in the form of optoelectronic components and have at least one pn junction.
  • the semiconductor components are preferably embodied as photovoltaic solar cells or as radiation-emitting diodes.
  • the semiconductor workpiece preferably has no pn junction on the rear side of the carrier substrate, so that a pn junction is not impaired by the separating trenches. It is therefore advantageous that no separating trench penetrates a pn junction of the semiconductor workpiece, in particular that the depth of the separating trench is selected in such a way that no separating trench penetrates a pn junction of the semiconductor workpiece.
  • no pn junction is formed on the rear side of the carrier substrate between the carrier substrate and the metallic rear-side contacting layer.
  • a semiconductor component according to the invention with a carrier substrate and at least one functional semiconductor layer arranged on a front side of the carrier substrate, which is embodied as a III-V compound semiconductor, and with at least one metallic rear-side contacting layer arranged on a rear side of the carrier substrate, the semiconductor component has at least one pn junction, solved.
  • the carrier substrate of the semiconductor component has a square roughness Rq (rms, root-mean-squared) greater than 0.5 pm, in particular greater than 1 pm, in particular greater than 3 pm on at least one side surface, at least in a partial area adjoining the rear side of the carrier substrate, and the functional one Semiconductor layer of the semiconductor component on the side surface has a square roughness Rq (rms, root-mean-squared) of less than 100 nm, in particular less than 50 nm, in particular less than 10 nm.
  • the roughness is measured using a laser confocal microscope.
  • a measurement using AFM atomic force microscope
  • 5 measurements with a single measurement distance of 1 mm are taken as a basis and the root mean square value is calculated from them.
  • the semiconductor component according to the invention has the advantage that, on the one hand, due to the lower roughness on the side surface in the area of the functional semiconductor layer, there is no or only a slight impairment of the electronic quality, compared to semiconductor components which, for example after a conventional sawing process, have greater roughness in this area have on the side surface.
  • greater roughness in the partial area of the side surfaces adjoining the rear side of the carrier substrate, greater roughness has no or only a slightly disadvantageous effect on the electronic quality of the semiconductor component. Greater roughness can therefore be tolerated in this area, which in particular makes it possible to produce the semiconductor component using the method according to the invention.
  • the semiconductor component according to the invention is preferably singulated using the method according to the invention.
  • the semiconductor component has the aforementioned features on at least two side surfaces, preferably on all side surfaces, that the carrier substrate of the semiconductor component has an effective average roughness Rq (rms, root -mean-squared) greater than 0.5 pm, in particular greater than 1 pm, in particular greater than 3 pm and the functional semiconductor layer of the semiconductor component on the side surface has an effective mean roughness Rq (rms, root-mean-squared) less than 100 nm, in particular less than 50 nm , In particular less than 10 nm.
  • the semiconductor components have one or more pn junctions.
  • no pn junction is advantageously formed, so that a Impairment of the electronic quality of the semiconductor component is avoided by influencing the pn junction due to the greater roughness in the lower area of the side surfaces of the carrier substrate.
  • the semiconductor component has a protective layer which is arranged on the side surface of the semiconductor component at least in the area of the functional semiconductor layer.
  • the protective layer avoids negative influences, in particular due to high recombination speeds on the side surface in the area of the pn junction.
  • the method according to the invention serves to singulate the semiconductor components.
  • the components are therefore advantageously separated after method step B2, so that the components are no longer in a composite, in particular are no longer mechanically or electrically connected.
  • the semiconductor components thus represent autonomous, isolated components.
  • the semiconductor components are preferably detached from the film at the end of the method.
  • FIG. 1 shows a semiconductor workpiece for dicing semiconductor components
  • FIG. 2 generation of a separating trench in an exemplary embodiment of a method according to the invention
  • FIG. 3 the separation by means of energy input in the exemplary embodiment
  • FIG. 4 shows a modification of the separating trench design
  • FIGS. 5 to 7 show a development of the exemplary embodiment using an elastic film
  • FIG. 8 shows an exemplary embodiment of a semiconductor component according to the invention
  • FIG. 11 shows a comparison of the isolation of semiconductor components without the use of separating trenches (partial image a) and with the use of separating trenches (partial image b).
  • FIGS. 1, 5 to 7 and 9 show sectional drawings of semiconductor components to be separated or separated. For better representation, the number of semiconductor components is reduced to 3, and FIGS. 8 and 10 show a semiconductor component as a sectional drawing.
  • FIGS. 2 to 4 show plan views from below of a semiconductor workpiece in each case.
  • FIG. 1 schematically shows a sectional illustration of a semiconductor workpiece 1.
  • the semiconductor workpiece 1 comprises a carrier substrate 2, which is predominantly in the form of a germanium wafer with a thickness of 190 ⁇ m.
  • a layer system with a plurality of semiconductor layers is formed on the front side of the carrier substrate 2, which is shown at the top in FIG. 1, in order to realize semiconductor components 5 formed as photovoltaic solar cells.
  • the layer system includes the following layers:
  • the layers marked with an * in the table represent functional semiconductor layers which are in the form of III-V compound semiconductors.
  • the layer structure shown in Tab. 1 has three pn junctions, two within the III-V structure and one in the germanium carrier substrate 2.
  • the carrier substrate 2 thus represents a further functional layer in this exemplary embodiment Structured development of the exemplary embodiment, the cover layer being removed in the areas not covered by the front-side contact.
  • a full-area metallic rear-side contacting layer 4 is arranged on the rear side of the carrier substrate 2, which is shown at the bottom in FIG.
  • the semiconductor workpiece 1 is to be separated into several parts in order—according to the simplified representation with a reduced number of semiconductor components—to obtain three semiconductor components 5 embodied as photovoltaic solar cells.
  • the separation of the semiconductor workpiece 1 should take place perpendicularly to the front side of the semiconductor workpiece at the positions marked with arrows in FIG. 1 and along the dashed lines.
  • the semiconductor workpiece shown in FIG. 1 is first provided in a method step A.
  • a method step B the semiconductor workpiece is severed along a plurality of isolating distances in order to isolate the semiconductor components 5 .
  • Process step B comprises the following process steps:
  • the metallic rear-side contacting layer 4 of the semiconductor components 5 is ablated by means of laser radiation on the rear side of the carrier substrate 2 along separating gaps.
  • FIG. 2 schematically shows method step B1.
  • the semiconductor workpiece 1 is shown in a plan view from the rear.
  • the isolating distances 6, at which the semiconductor workpiece 1 is to be severed and which thus define the future edges of the semiconductor components 5, are shown as dashed lines and form a rectangular grid.
  • a laser beam in this case with a wavelength of 1070 nm, pulse length in the range 1 ns, laser energy 1.5 W, pulse frequency 30 kHz, traversing speed 50 mm/s, the metallic rear-side contacting layer 4 is completely removed along the isolating distances 6 in method step B1.
  • separating trenches are simultaneously produced along the isolating distances 6, which trenches extend over the entire length of the isolating distances 6, with a width of approximately 30 ⁇ m and a depth in the carrier substrate 2 of approximately 95 ⁇ m.
  • the separating trenches thus penetrate approximately 50% into the carrier substrate 2 from the back.
  • a laser beam with the previously specified parameters is used to generate the isolating distances.
  • Typical carrier substrates have a diameter in the range of 50 mm - 200 mm. In typical applications, tens to several thousand semiconductor devices are formed from a carrier substrate.
  • step B2 the carrier substrate 2 is now severed along the isolating distances 6 by energy input by means of laser radiation, the carrier substrate being heated below the melting temperature of the carrier substrate.
  • This sub-step is shown in Figure 3:
  • a laser beam 7a in this case with the parameters wavelength 1070 nm, continuous laser beam, laser energy 88 W, traversing speed 200 mm/s, which traces the rear side of the semiconductor workpiece along the in Process step B1 applied separating trenches produced, the carrier substrate 2 is heated.
  • the laser beam 7a is tracked by a coolant jet 8, in this case a water jet, which causes local cooling immediately after the carrier substrate 2 has been locally heated by the laser beam 7a.
  • the thermal stress generated as a result leads to crack formation and thus to splitting of the carrier substrate 2 along the isolating distances 6 and perpendicular to the rear side of the carrier substrate 2.
  • FIG. 1 A modification of the exemplary embodiment is shown in FIG.
  • separating trenches are only produced in partial areas of the separating distances 6 in method step B2.
  • separating trenches 9 in the form of a cross (+) are produced at the crossing points of the separating distances 6 (see FIG. 3).
  • two cross-shaped separating trenches are identified in FIG. 4 with the reference number 9 .
  • the parameters of the laser beam 7 used to generate the separating trenches correspond to the parameters for generating separating trenches described above for FIG. These separating trenches also have a width of 30 ⁇ m and a depth of about 95 ⁇ m.
  • the carrier substrate is then severed along the separating paths in method step B2, heating by means of the laser beam 7a and immediately thereafter cooling by the coolant jet 8 taking place according to FIG.
  • FIGS. 5 to 7 A second development of the exemplary embodiment according to FIGS. 1 to 3 is shown in FIGS. 5 to 7:
  • the semiconductor workpiece 1 is arranged on an expandable film 10, in this case a film made of polyolefin with a thickness of 85 ⁇ m.
  • the semiconductor workpiece 1 is placed face-to-face with the foil 10 as shown in FIG. FIG. 5 shows the state in which the separating trenches 9 have already been formed, but the carrier substrate 2 has not yet been completely severed.
  • Method steps B1 and B2 are then carried out as previously described in the exemplary embodiment, so that the semiconductor workpiece 1 is severed perpendicularly to the front side of the semiconductor workpiece at the positions marked with arrows in FIG. 5 and the semiconductor components 5 are isolated. This is shown in FIG. 6: The semiconductor components 5 are already isolated, but are located at the severed edges
  • step B the film is stretched so that the semiconductor components 5 are spatially separated, as shown in FIG.
  • FIG. 8 shows a plan view of the side face identified by reference numeral 12 in FIG. The separating trench in the upper area of the semiconductor component 5 thus runs horizontally.
  • the isolated semiconductor component 5 represents an exemplary embodiment of a semiconductor component according to the invention, with the part of the carrier substrate 2, the functional semiconductor layer 3 arranged on the underlying front side according to the illustration in Figure 8, which is designed as a III-V compound semiconductor and one on the according to 8. Due to the separation as described above with the formation of a separating trench, the semiconductor component 5 has at the edge surface 12 according to FIG. 7, which can be seen in FIG Area a surface 13 with high roughness, which is the side wall of the previously formed separating trench. In the lower area, the carrier substrate 2 was severed in method step B2, so that a surface 14 with less roughness was achieved. Since pn junctions are located in the area of the front side lying underneath, in particular in the area of the functional semiconductor layer 3, the pn junctions do not border on the surface 13 with high roughness, but on the surface 14 with opposite surface
  • FIGS. 9 and 10 A development of the method according to FIGS. 5 to 7 is shown in FIGS. 9 and 10: before the semiconductor components 5 are detached from the film 10, a protective layer 11 is applied.
  • the protective layer 11 in this case an aluminum oxide layer with a layer thickness of 50 nm, is applied to the side surfaces by means of ALD (Atomic Layer Deposition) in order to further increase the electrical quality of the semiconductor components 5 by edge passivation. During this process, the protective layer 11 also covers the rear-side contacting layers 4 of the semiconductor components 5 and the film 10 in the spaces between the spaced-apart semiconductor components 5.
  • ALD Atomic Layer Deposition
  • the protective layer 11 is mechanically removed from the back contact layers 4 by polishing.
  • Such a semiconductor component 5 is shown in FIG. 10 and thus represents a further development of the exemplary embodiment of a semiconductor component according to the invention shown in FIG.
  • FIG. 11 shows photographs of semiconductor workpieces with isolated semiconductor components in a plan view from the rear of the semiconductor workpieces.
  • the semiconductor workpiece according to part a) was not processed using a method according to the invention.
  • isolation was carried out in accordance with method step B2, without separating trenches having been produced beforehand. It is clearly evident that dividing lines according to the desired rectangular grid could only be achieved in partial areas. During the separation, parts with very different sizes were formed.
  • the semiconductor workpiece was also severed along oblique, diagonal and irregular severing lines in some partial areas.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Dicing (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne un procédé de séparation de composants semi-conducteurs (5), comprenant une étape de procédé A consistant à fournir une pièce à usiner semi-conductrice (1), qui a un substrat de support (2) et une pluralité de composants semi-conducteurs (5), les composants semi-conducteurs (5) ayant : - au moins une couche fonctionnelle semi-conductrice (3), qui est située sur un côté avant du substrat de support (2) et qui se présente sous la forme d'un semi-conducteur composé III-V, et - au moins une couche de contact arrière métallique (4), qui est située sur un côté arrière du substrat de support (2), et comprenant une étape de procédé B consistant à couper à travers la pièce à usiner semi-conductrice (1) le long d'une pluralité de trajectoires de coupe afin de séparer les composants semi-conducteurs. Il est essentiel que l'étape de procédé B comprenne les étapes de procédé suivantes : dans une étape de procédé B1, la couche de contact arrière métallique (4) des composants semi-conducteurs (5) est coupée à travers le côté arrière du substrat de support (2) le long des trajets de coupe et une tranchée de coupe (9) est produite sur le côté arrière du substrat de support (2), au moins dans des parties des trajectoires de coupe, au moyen d'une ablation par rayonnement laser, et dans une étape de procédé B2, le substrat de support (2) est coupé le long des trajets de coupe par apport d'énergie dans le substrat de support (2) au moyen d'un rayonnement laser, le substrat de support (2) étant chauffé au-dessous de la température de fusion du substrat de support (2). L'invention concerne également un composant semi-conducteur (5) séparé.
EP22764787.2A 2021-08-20 2022-08-15 Procédé de séparation de composants semi-conducteurs Pending EP4388593A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102021121684.2A DE102021121684A1 (de) 2021-08-20 2021-08-20 Verfahren zum Vereinzeln von Halbleiterbauelementen
PCT/EP2022/072777 WO2023021002A1 (fr) 2021-08-20 2022-08-15 Procédé de séparation de composants semi-conducteurs

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EP4388593A1 true EP4388593A1 (fr) 2024-06-26

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DE (1) DE102021121684A1 (fr)
WO (1) WO2023021002A1 (fr)

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