Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/92—Capacitors having potential barriers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/40—Capacitors
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/26—Deposition of carbon only
  • C23C16/27—Diamond only
  • C23C16/278—Diamond only doping or introduction of a secondary phase in the diamond
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
  • C30B25/02—Epitaxial-layer growth
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/02—Elements
  • C30B29/04—Diamond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/005—Electrodes
  • H01G4/008—Selection of materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/018—Dielectrics
  • H01G4/06—Solid dielectrics
  • H01G4/08—Inorganic dielectrics
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/40—Capacitors
  • H01L28/60—Electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
  • H01L29/1602—Diamond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
  • H01L29/1608—Silicon carbide
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L29/2003—Nitride compounds
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22

Definitions

• the present invention relates to the field of microelectronic devices. It relates in particular to a capacitor comprising a stack of layers of semiconductor material with a wide forbidden band.
• a micro-electronic circuit also requires passive components, such as capacitors, supporting very high voltages (for example greater than 1000V, or even greater than 3000V), to form RC dampers capable of suppressing voltage transients when switching between closed circuit and open circuit; this avoids damage by overloading the active devices.
• Ceramic insulator capacitors are known to hold very high voltages. They nevertheless have several drawbacks: first of all, their large size prevents them from being integrated as close as possible to the active devices; the significant distance between active and passive devices creates parasitic inductances, this becoming all the more true as the switching frequencies increase.
• these capacitors are not compatible with integration during the micro-electronic manufacturing of active devices, in a clean room. Finally, they operate in a limited temperature range, typically between room temperature and 125°C.
• the present invention aims to remedy all or part of the aforementioned drawbacks. It proposes a capacitor with fixed capacitance comprising a stack of layers of semiconductor material with a wide forbidden band, capable of withstanding very high voltages, reliable, whose capacitance value is constant regardless of the applied voltage, having dimensions reduced and capable of operating in a wide range of temperatures, typically up to 300°C.
• the capacitor according to the invention is also compatible with microelectronic manufacturing methods and can therefore be monolithically co-integrated close to active power devices.
• the invention relates to a capacitor comprising a stack of layers made of a semiconductor material having a band gap energy greater than 2.3 eV, said stack of layers comprising: - an intermediate layer, electrically insulating, having a resistivity greater than 10 kohm.cm and comprising n- or p-type deep dopants producing energy levels located at more than 0.4 eV from the conduction band or the band valence of the semiconductor material,
• two contact layers having a resistivity of less than 10 kohm.cm and comprising dopants of the opposite type to that of the deep dopants of the intermediate layer, the two contact layers, electrically insulated from each other, being arranged either side of the intermediate layer to form two pn junctions.
• the two contact layers have a resistivity less than or equal to 1 mohm.cm, to confer a purely capacitive nature on the capacitor;
• the capacitor comprises two metal electrodes respectively electrically connected to the two contact layers;
• the deep dopants are present in the intermediate layer in a concentration of between lxl0 14 /cm 3 and lxlO 21 /cm 3 ;
• the intermediate layer has a thickness of between 10 nm and 2 mm, preferably between 500 nm and 50 microns;
• each contact layer has a thickness between 5 nm and 50 microns, preferably between 50 nm and 1 micron;
• the semiconductor material of the stack of layers is chosen from among silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), ternary or quaternary alloys based on nitride, boron nitride (BN), gallium oxide (Ga203) and diamond;
• the capacitor comprises a support substrate on which the stack of layers is arranged
• the support substrate is composed of a semiconductor material of the same nature as the semiconductor material of the stack of layers;
• the semiconductor material forming the stack of layers is diamond, the deep dopants of the intermediate layer are n-type, and the dopants of the contact layers are p-type and are boron atoms;
• the deep dopants of the intermediate layer are nitrogen atoms
• the semiconductor material forming the stack of layers is silicon carbide
• the deep dopants of the intermediate layer are p-type and are vanadium atoms
• the (shallow) dopants of the contact layers are of type n and are nitrogen atoms.
• Figure 1 shows a first embodiment of a capacitor according to the invention
• FIG. 2 shows a second embodiment of a capacitor according to the invention.
• the same references in the figures may be used for elements of the same type.
• the figures are schematic representations which, for the purpose of readability, are not to scale. In particular, the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers between them are not necessarily observed in the figures.
• the invention relates to a capacitor 10 comprising a stack of layers 1 formed from a so-called wide-bandgap semiconductor material, that is to say having a bandgap energy, between the valence band and the conduction band. , greater than 2.3 eV.
• the semiconductor material can in particular be chosen from: silicon carbide (SiC), for example 4H-SiC, whose forbidden band energy is 3.26 eV,
• GaN gallium nitride
• AIN aluminum nitride
• nitride for example AlGaN, InGaN, etc.
• Ga2Ct gallium oxide
• the stack of layers 1 of the capacitor 10 comprises three layers 2a, 2b, 3 formed in the semiconductor material with a large band gap: an intermediate layer 3 arranged between two contact layers 2a, 2b ( Figure 1 and Figure 2).
• the contact layers 2a, 2b have a resistivity of less than 10 kohm.cm. They can, according to different aspects of the invention, have a resistivity less than or equal to 10 ohm.cm, less than or equal to 1 ohm.cm, less than or equal to 10 mohm.cm, or even less than or equal to 1 mohm.cm .
• the contact layers 2a, 2b are doped with n-type (donors) or p-type (acceptors) dopants capable of increasing the conductivity of the semiconductor material, to adjust the expected resistivity. They are electrically isolated from each other because they are intended to form (in whole or in part) the two metal plates of capacitor 10.
• donors and acceptors are impurities (atoms) introduced, voluntarily or not, into a semiconductor; donors (n-type) are able to donate electrons to the conduction band or other levels in the bandgap, and acceptors (p-type) are able to capture electrons from the valence band or from other bandgap levels.
• shallow donors are defined as being able to easily donate an electron to the conduction band of the semiconductor. This is related to the fact that their energy level in the forbidden band is slightly removed from the conduction band.
• a semiconductor heavily doped with shallow donors therefore has electrical conductor properties, at room temperature, due to the free electrons transferred to the conduction band by the donors.
• shallow acceptors are defined as capable of easily capturing an electron at the valence band of the semiconductor, because their energy level in the bandgap is slightly away from the valence band.
• a semiconductor heavily doped with shallow acceptors therefore has electrical conductor properties, at room temperature, due to the free holes generated in the valence band by the acceptors.
• the dopants introduced into said layers 2a, 2b will generally be qualified as shallow dopants. Nevertheless, certain dopants, which are not ordinarily considered shallow, can be used to achieve the resistivities mentioned above.
• the ionization energy of the boron dopant is 0.38 eV for low concentrations of dopants and tends towards 0 eV when the concentration increases until reaching the insulator-metal transition for a doping of 5xl0 20 /cm 3 . It is then possible to achieve resistivities of less than 5 mohm.cm in diamond heavily doped with boron.
• Conduction by jumping (“hopping” according to the Anglo-Saxon terminology) also makes it possible to achieve low resistivities by using dopants, such as for example boron (acceptor) or phosphorus (donor) in diamond.
• dopants such as for example boron (acceptor) or phosphorus (donor) in diamond.
• concentration of boron must be between lxl0 19 /cm 3 and 5xl0 2 °/cm 3 and that of phosphorus must be greater than lxl0 19 /cm 3 .
• the semiconductor material of the contact layers 2a, 2b may have a polycrystalline structure, or preferably monocrystalline, to reduce leakage (interference) and provide a better interface with the intermediate layer 3 when itself is monocrystalline.
• the intermediate layer 3 is electrically insulating, that is to say it has a resistivity greater than 10 kohm.cm.
• the resistivity of intermediate layer 3 is as high as possible, for example greater than 1000 kohm.cm.
• It includes deep dopants which are defined here as producing energy levels situated at more than 0.4 eV from the conduction band or the valence band of the semiconductor material.
• the deep dopants of the intermediate layer 3 can be deep donors (n-type) or deep acceptors (p-type), specific to the nature of the semiconductor material.
• Deep dopants are donors or acceptors with higher binding energies for electrons and holes, respectively, and therefore are not substantially ionized at room temperature. Compared to shallow donors and acceptors, the energy levels of deep donors and acceptors are positioned deeper in the bandgap, i.e. further away from the conduction band and the valence band, respectively. The insulating character of the intermediate layer 3 can therefore be perfectly preserved in the presence of these deep dopants.
• deep dopants will be chosen producing energy levels situated at more than leV of the valence bands (acceptors) or conduction bands (donors).
• the ionization energy of the deep dopant should be greater than leV or l.3eV, in order to ensure a resistivity of the intermediate layer 3 greater than or equal to 1000 kohm.cm, respectively for operation at 150° C. or at 250° C.
• the deep dopants are present in the intermediate layer 3, at a concentration of between 1 ⁇ 10 14 /cm 3 and 1 ⁇ 10 21 /cm 3 .
• this range of concentration is likely to be more restricted, typically between lxl0 14 /cm 3 and lxl0 18 /cm 3 , in certain specific cases of deep dopants; indeed, beyond a certain concentration, certain deep dopants (such as phosphorus in diamond, already mentioned above) can participate in electrical conduction by a phenomenon of conduction by jumping (“hopping”), which does not is not desired in the intermediate layer 3.
• the semi-conductor material of the intermediate layer 3 can have a polycrystalline or preferably monocrystalline structure to guarantee good electrical insulation by avoiding leakage currents and premature breakdown, which could be favored by the presence of grain boundaries.
• the dopants of the contact layers 2a, 2b are of the opposite type to that of the deep dopants of the intermediate layer 3.
• the stack of layers 1 thus forms two pn junctions, respectively between the upper contact layer 2a and the intermediate layer 3, and between the lower contact layer 2b and the intermediate layer 3.
• Capacitor 10 thus successively comprises upper contact layer 2a, a pn junction, intermediate insulating layer 3, a pn junction, and lower contact layer 2b.
• the pn junctions avoid the injection of carriers from the contact layers 2a, 2b into the intermediate layer 3, when a high voltage is applied to the capacitor 10, via the contact layers 2a, 2b. Such an injection would greatly degrade the insulating character of the intermediate layer 3.
• the pn junctions which are established between the contact layers 2a, 2b and the intermediate layer 3 confer great stability and excellent reliability on the capacitor 10 according to the invention.
• the capacitor effect is ensured by the non-deserted zone of the intermediate layer 3, when the dopants of the intermediate layer 3 are deep enough to provide electrical insulation at the working temperature, and by the two space charge zones of the two pn junctions. For high working temperatures (typically above 150° C.), overlapping of the two space charge zones of the two pn junctions can be used to reinforce the electrical insulation of the intermediate layer 3.
• the capacitor 10 according to the invention takes advantage of the presence of deep dopants in the intermediate layer 3, of the type opposite to the shallow dopants of the contact layers 2a, 2b, on the one hand, to ensure the insulating nature of said intermediate layer 3 (property of deep impurities), and on the other hand, to establish two pn junctions (deep impurities used as dopants) which ensure a fixed capacitance value and give electrical insulation, stability and reliability to capacitor 10.
• the intermediate layer 3 may have a thickness (along the z axis in the figures) of between 10 nm and 2 mm, preferably between 500 nm and 50 microns.
• Each contact layer 2a, 2b can have a thickness of between 5 nm and 50 microns, preferably between 50 nm and 1 micron.
• the semiconductor material forming the stack of layers 1 is diamond.
• the deep dopants of the intermediate layer 3 are n-type (donors). They may be phosphorus (P) atoms or preferably nitrogen (N) atoms. In diamond, phosphorus and nitrogen produce levels deep in the forbidden band, respectively at 0.57eV and 1.7eV below the conduction band.
• the concentration of deep nitrogen donors is of the order of 3 ⁇ 10 19 /cm 3
• the intermediate layer 3 has a resistivity greater than 1000 kohm.cm
• the concentration of deep phosphorus donors is of the order of 1 ⁇ 10 15 /cm 3
• the resistivity of the intermediate layer 3 is greater than 100 kohm.cm.
• the dopants of the contact layers 2a, 2b are boron atoms (B), of p type (acceptors).
• B boron atoms
• acceptors p type
• boron produces a band gap level, 0.38eV above the valence band. But, as previously mentioned, the ionization energy of boron decreases when the concentration of dopants increases.
• the contact layers 2a, 2b have a resistivity of less than 5 mohm.cm. Still by way of example, with a concentration of acceptors of the order of 5 ⁇ 10 14 /cm 3 , the contact layers 2a, 2b have a resistivity of the order of 1 kohm.cm.
• the stack 1 of the three layers 2a, 3, 2b defines a stack of p/n/p types.
• the semiconductor material forming the stack of layers is silicon carbide (SiC).
• the deep dopants of the intermediate layer 3 are vanadium (V) atoms, of the p type.
• V vanadium
• the concentration of deep acceptors is of the order of lxl0 15 /cm 3
• the intermediate layer 3 has a resistivity greater than 100 kohm.cm.
• the shallow dopants of the contact layers 2a, 2b are nitrogen atoms, of n type. In Sic, nitrogen produces a shallow level in the bandgap, 0.08 eV below the conduction band.
• the contact layers 3 have a resistivity of less than 20 mohm.cm.
• the stack 1 of the three layers 2a, 3, 2b defines a stack of n/p/n types.
• the capacitor 10 advantageously comprises two metal electrodes 4a, 4b respectively electrically connected to the two contact layers 2a, 2b. These electrodes 4a, 4b are in ohmic contact with said layers 2a, 2b and will allow the electrical connection of capacitor 10 to the exterior.
• Each electrode 4a, 4b can thus consist of one or more metal layer(s) deposited on a contact layer 2a, 2b.
• connection between the two contact layers 2a, 2b and the outside can alternatively be made by any other known means making it possible to electrically connect said layers 2a, 2b.
• Capacitor 10 belongs to the category of fixed-capacitance non-polarized capacitors.
• the capacitance remains constant (i.e. with less than 10% variation, or even less than 1% variation) regardless of the voltage applied to these plates (contact layers 2a, 2b or electrodes 4a, 4b), said voltage being greater than several kV, greater than 1000V, greater than 2000V, or even more.
• the two contact layers 2a, 2b (potentially with their electrodes 4a, 4b) form the two metal plates of the capacitor 10, separated by an insulating material (the intermediate layer 3). When a voltage is applied between the two armatures, an electric field is formed in the insulating material (intermediate layer 3).
• Capacitor 10 is defined by its capacitance C expressed in Farad (F):
• the value of the capacitance C will therefore depend on S, the larger S is, the larger C will be, d, the smaller d is, the larger C will be,
• the lateral dimensions of the capacitor 10, defining the surface S of the metal plates can be between 10 microns and 10 mm.
• the capacitor 10 is limited by the maximum electric field that the intermediate layer 3 can withstand.
• Semiconductors with a wide forbidden band are known to have very high maximum electric fields. For example, for SiC this field is about 3 MV/cm and for diamond it is 10 MV/cm.
• This intrinsic property of the intermediate layer 3 makes it possible to push back the limits of the capacitors currently available.
• the two contact layers 2a, 2b have a resistivity less than or equal to 1 mohm.cm: the series resistance of capacitor 10 is then negligible (compared to the other resistances of the circuit in which said capacitor 10 will be integrated). Capacitor 10 then has a purely capacitive character.
• the two contact layers 2a, 2b have a resistivity greater than 1 mohm.cm (and, it should be remembered, less than 10 kohm.cm).
• the series resistance of capacitor 10 becomes significant (compared to the other resistances of the circuit in which said capacitor 10 will be integrated) and can be adjusted to produce an RC snubber.
• Capacitor 10 then defines a capacitance with an integrated resistor and forms an RC snubber device.
• each electrode 4a, 4b is arranged on a main face (in the (x,y) plane) of layer stack 1.
• the stack of layers 1 is arranged on a support substrate 5, included in the capacitor 10, which typically forms the growth support for the layers of the stack 1.
• the substrate support 5 may be composed of a semiconductor material of the same nature as the semiconductor material of the stack of layers 1 or of a different nature but allowing the growth of the layers of the stack 1.
• this support substrate 5 modifies the arrangement of the electrodes 4a, 4b.
• An electrode 4a is placed on the free main face of the upper contact layer 2a.
• Layer lower contact layer 4b has a surface in the plane (x,y) greater than the surface, in this same plane, of the other layers of the stack 1 (namely the intermediate layer 3 and the upper contact layer 4a).
• the other electrode 4b can be in contact with the lower contact layer 2b at its peripheral surface, free of the other layers of the stack 1 (FIG. 2).
• Diamond is chosen here as the semiconductor material.
• the starting point is a type Ib diamond wafer, enriched in nitrogen (N), obtained by a high pressure high temperature (HPHT) or chemical vapor deposition (CVD) technique.
• This wafer has a concentration of deep N donors of 1 ⁇ 10 19 /cm 3 and has the expected insulating properties (resistivity greater than 10 kohm.cm).
• this wafer will form the intermediate layer
• the intermediate layer 3 is then treated in a conventional acid cleaning bath, so as to eliminate contaminants such as graphite, metals, organic and inorganic materials.
• a deposit (growth) of a highly conductive monocrystalline diamond layer (of p++ type) is operated on either side of the intermediate layer 3, to form the two contact layers 2a, 2b.
• the deposition can be carried out, for example, by hot filament (HF) CVD or by microwave plasma (MP).
• HF hot filament
• MP microwave plasma
• the concentration of boron B atoms is 5 ⁇ 10 2 ° atm/cm 3 .
• the thickness is, for example, 200 nm.
• the next step consists of the metallization of the surfaces of the contact layers 2a, 2b.
• a deposition of metal, titanium (Ti) followed by gold (Au), is for example carried out, on the free faces of the two layers 2a, 2b, with a total thickness of 70 nm (30 nm Ti and 40 nm At).
• Other metals can of course be used which will form an ohmic contact.
• the structure is then annealed to promote the formation of a carbide, and to confer the ohmic character on contact.
• the annealing can be carried out using a simple furnace or an RTA system for rapid and controlled rises in temperature, for example at 450° C. for 1 hour under vacuum with a flow of inert gas of the argon type.
• a capacitor structure 10 conforming to the first embodiment of the invention (FIG. 1) is then obtained, compatible with a very high voltage, typically up to several kV, and with a capacitance of the order of 1 pF/mm 2 .
• the contact layers 2a, 2b here have a resistivity of less than 1 mohm.cm, giving a purely capacitive character to the capacitor 10 (first aspect of the invention).
• the starting support substrate 5, made of monocrystalline diamond, of any known type, is obtained by a high pressure high temperature (HPHT) or chemical vapor deposition (CVD) technique.
• HPHT high pressure high temperature
• CVD chemical vapor deposition
• a conventional acid bath cleaning is applied to the support substrate 5 so as to remove the contaminants.
• the growth of a highly conductive single-crystal diamond layer (of the p++ type) is carried out on the support substrate 5, to form the lower contact layer 2b of the stack 1.
• the deposition can be carried out, for example, by CVD hot filament (HF) or microwave plasma (MP).
• the concentration of boron B atoms is 5 ⁇ 10 2 ° atm/cm 3 .
• the thickness is 200 nm.
• This is followed by the deposition (growth) of a monocrystalline diamond layer, electrically insulating and n-type (dopants deep nitrogen), to form the intermediate layer 3.
• the concentration of deep donors is 1x10 19 atm/cm 3 and the thickness of the intermediate layer 3 is approximately 1 micron.
• a new growth of a highly conductive monocrystalline diamond layer (of p++ type) is carried out on the intermediate layer 3, to form the upper contact layer 2a of the stack 1, identical to the lower contact layer 2b.
• a mask for example made of aluminum, is then deposited on the upper contact layer 2a, to delimit a smaller surface than the desired surface for the lower contact layer 2b. It is then possible to etch the unmasked portion of the upper contact layer 2a and of the intermediate layer 3, until reaching the lower contact layer 2b.
• the metallization of the free surfaces of the contact layers 2a, 2b can be carried out, for example in two successive steps, by using masks and/or by implementing lithography techniques. Titanium (Ti) and gold (Au) or other metal deposits can be made to form an ohmic contact between each contact layer 2a, 2b and its electrode 4a, 4b. Each electrode 4a, 4b has a thickness of 70 nm. An annealing of the structure, for example such as that described in the first embodiment, is then carried out to promote the formation of a carbide, and to confer the ohmic character on contact.
• a metal mask is deposited on the surface of said layer 2b which must remain free of the other layers of the stack 1. Then, the intermediate layer 3 and the upper contact layer 2a are produced, by selective growth, only on a defined surface (the central surface in FIG. 2). Withdrawal of the mask and the metallization can then take place as previously described.
• a capacitor structure 10 conforming to the second embodiment of the invention is then obtained, compatible with a very high voltage, typically up to 1000 V, with a fixed capacitance of the order of 0 .05nF/mm 2 , whatever the voltage applied to its terminals.
• the contact layers 2a, 2b here have a resistivity of less than 1 mohm.cm, giving a purely capacitive character to the capacitor 10 (first aspect of the invention).
• the contact layers 2a, 2b will be produced with a thickness of approximately 1 micron and a resistivity of 1 kohm.cm (typically corresponding to a concentration in boron dopants of the order of 5 ⁇ 10 14 /cm 3 ). It is thus possible to obtain a time constant of the RC damping circuit of 1 ns, with the same capacitance as mentioned above, of the order of 0.05 nF/mm 2 .
• the second embodiment provides more flexibility on the value of the capacitance, the thickness of the intermediate (insulating) layer 3 being able to be manufactured and adjusted with greater ease than in the first embodiment.
• Capacitor 10 is capable of storing high energies, typically a voltage greater than 1000V, greater than 3000V, or even greater than 5000V. It provides great stability of capacitance values with temperature, in a wide temperature range between -30°C and 300°C. Leakage currents generated by temperature are negligible. Capacitor 10 is produced by microelectronic processes; it is therefore easily co-integrable monolithically with active components, on the same chip.
• the capacitor according to the invention constitutes a passive component capable of being integrated into all electric power converters, used for example in hybrid and/or electric cars, aeronautics, energy management, etc. Integrated in busbars and damping RC networks, it protects electrical circuits from component failure due to a voltage peak, typically greater than 2000V, generated during switching between closed and open circuit.
• the capacitor according to the invention can be used for the protection of a high voltage electrical circuit against voltage transients.

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• 2021
  • 2021-03-05 FR FR2102170A patent/FR3120470B1/fr active Active
• 2022
  • 2022-03-03 CN CN202280018667.7A patent/CN117121659A/zh active Pending
  • 2022-03-03 EP EP22712961.6A patent/EP4302339A1/de active Pending
  • 2022-03-03 KR KR1020237030118A patent/KR20230160240A/ko unknown
  • 2022-03-03 JP JP2023553959A patent/JP2024510144A/ja active Pending
  • 2022-03-03 US US18/549,016 patent/US20240154045A1/en active Pending
  • 2022-03-03 WO PCT/FR2022/050383 patent/WO2022185014A1/fr active Application Filing
  • 2022-03-04 TW TW111108009A patent/TW202249319A/zh unknown

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