Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/32—Means for protecting converters other than automatic disconnection
  • H02M1/34—Snubber circuits
  • H02M1/342—Active non-dissipative snubbers
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0048—Circuits or arrangements for reducing losses
  • H02M1/0054—Transistor switching losses
  • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
  • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
  • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
  • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
  • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
  • H02M3/33573—Full-bridge at primary side of an isolation transformer
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
  • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
  • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
  • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
  • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
  • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0083—Converters characterised by their input or output configuration
  • H02M1/0087—Converters characterised by their input or output configuration adapted for receiving as input a current source
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/01—Resonant DC/DC converters
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
  • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
  • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

• TITLE Method and device for converting a voltage with gentle switching of switches.
• the present invention relates to the field of DC-DC converters, and in particular converters which include a transformer providing galvanic isolation.
• DC-DC converters are based on the use of full bridge switching cells, coupled with a transformer.
• a switching cell usually includes a switch and a capacitor.
• the switching cells are configured for soft switching, ie with zero voltage at the terminals of the switch when closing and opening said switch, in other words respectively when the said switch is turned ON and when the switch is turned OFF. .
• soft switching is only effective when closing, in other words when switching the switch to ON, and is not effective when switching on. 'opening, in other words when the switch is turned OFF.
• the present invention relates to a method for converting an input voltage between two input terminals of a primary circuit of a converter into an output voltage between two output terminals of a secondary circuit of the converter.
• the primary circuit comprising:
• first bridge arm formed by a first switch and a second switch, the first and the second switch being connected in series between the input terminals of the primary circuit, a first midpoint of the first bridge arm designating a connection point intermediate between the first switch and the second switch;
• a third bridge arm formed by a fifth switch and a sixth switch, the fifth and the sixth switch being connected in series between the input terminals of the primary circuit, a third midpoint of the third bridge arm designating a connection point intermediate between the fifth switch and the sixth switch, the third bridge arm being connected in parallel with the first and second bridge arms between the input terminals of the primary circuit;
• control unit configured to control a state of the switches, each switch being configured to be alternately on
• control unit ON or OFF, the control unit being configured to implement a switch command cycle comprising the following steps:
• the invention comprises one or more of the following characteristics, alone or in a technically acceptable combination.
• the first instant is determined as a function of a time when the diode associated with the first switch is in conduction, so that a voltage across the first switch is zero.
• the capacitor arranged in parallel between the respective terminals of each of the first, second, third, and fourth switches allows gentle switching when the switches are turned OFF and when the switches of the first bridge arm are turned ON.
• the injection inductance allows gentle switching of the switches over the entire operating range, in particular by extending the operating range to the lowest operating powers.
• the injection duration is determined as a function of the predetermined minimum injection current.
• the injection duration is determined by the relationship:
• the minimum predetermined injection current is determined as a function of a level of current available l LKdispo in the primary coil of the primary circuit and a critical current level l LK.min in the primary coil of the primary circuit.
• the predetermined minimum injection current is equal to l LK.min -l LKdispo .
• the level of current available l LKdispo is a function of a ratio between a number of turns Np of the primary coil and a number of turns Ns of the secondary coil and an average value of one current l L1.moy in an inductor L1, L2 of the secondary circuit.
• the level of current available LKdispo is determined by the relation: [Math 3]
• the critical current level l LK.min in the primary coil of the primary circuit is a function of a capacitance Cres of the capacitor arranged in parallel between the respective terminals of each of the first, second, third, and fourth switches and the leakage inductance L k of the primary coil of the primary circuit and the input voltage Vin between the input terminals of the primary circuit of the converter.
• the critical current level l LK.min in the primary coil of the primary circuit is determined by the relation:
• Kmarge is a margin coefficient to be adjusted so that the freewheeling diode of one of the switches of the first bridge arm conducts long enough so that the gate voltage of the transistor of said switch can be applied to guarantee a soft switching when the second switch B is turned ON, between an instant ts, defined as a function of the fourth instant t 4 , and the fifth instant t 6 , and to guarantee a soft switching when the first switch A is turned ON between an instant t 10 defined as a function of the eighth instant t 9 and the first instant t 0 ;
• the coefficient Kmarge is equal to 1.2.
• the second instant of the cycle is offset from the first instant by a first time offset, a function of a phase shift between the first and second bridge arms, and by a duration of a complete cycle;
• the third instant of the cycle is shifted from the first instant by a second time shift as a function of the first time shift and a first dead time;
• the fourth instant of the cycle is shifted from the first instant by a third time shift which is a function of the duration of a half-cycle and of a second dead time;
• the fifth instant of the cycle is shifted from the first instant by a fourth time shift which is a function of the duration of a complete half-cycle;
• the sixth instant of the cycle is shifted from the first instant by a fifth time shift depending on the phase shift and the duration of a complete half-cycle;
• the seventh instant of the cycle is shifted from the first instant by a sixth time shift depending on the phase shift and the duration of a complete half-cycle and the first dead time;
• the eighth instant of the cycle is shifted from the first instant by a seventh time shift as a function of the duration of a complete cycle and of the second dead time.
• the phase shift Ph between the first and second bridge arms is determined as a function of the ratio between the number of turns Np of the primary coil and the number of turns Ns of the secondary coil and of the ratio between the output voltage V or t between the output terminals of the secondary circuit and the input voltage V in . between the input terminals of the primary circuit.
• the phase shift is defined by the relation: [Math 4]
• the duration T of a complete cycle is a predetermined constant.
• said first dead time corresponding to both a time interval between the second instant t 2 and a time where the diode of switch C becomes conductive, and at a time interval between the sixth instant t 7 and a time when the diode of switch D becomes conductive.
• the first dead time t dead_C_D is adjusted to guarantee gentle switching of the switches of the second bridge arm, from the moment when the injection current has reached the predetermined minimum injection current.
• said second dead time corresponds to the time interval between the instants t 4 and t 5 , and also to the time interval between t 9 and t-io.
• the second dead time t dead_A_B is determined as a function of the capacitance C res of the capacitor arranged in parallel between the respective terminals of each of the first, second, third, and fourth switches and of the inductance of L k leak from the primary coil of the primary circuit.
• the second dead time t dead_A_B is determined by the relation:
• the first dead time t dead_A_B is determined by the relation:
• the first time shift between t 0 and t 2 is determined by the relationship:
• the third time shift between t 0 and t 4 is determined by the relation: [Math 10]
• the fourth time shift between t 0 and t 6 is determined by the relationship:
• the fifth time shift between t 0 and t 7 is determined by the relation: [Math 12]
• the sixth time offset between t 0 and t 8 is determined by the relation:
• the seventh time shift between t 0 and t 9 is determined by the relation:
• the invention also relates to a converter comprising a primary circuit and a secondary circuit, the converter being configured to convert an input voltage between two input terminals of the primary circuit into an output voltage between the output terminals of the secondary circuit, the primary circuit comprising:
• first bridge arm formed by a first switch and a second switch, the first and the second switch being connected in series between the input terminals of the primary circuit, a first midpoint of the first bridge arm designating a connection point intermediate between the first switch and the second switch;
• a third bridge arm formed by a fifth switch and a sixth switch, the fifth and the sixth switch being connected in series between the input terminals of the primary circuit, a third midpoint of the third bridge arm designating a connection point intermediate between the fifth switch and the sixth switch, the third bridge arm being connected in parallel with the first and second bridge arms between the input terminals of the primary circuit;
• Each of the first, second, third, fourth, fifth and sixth switches being associated with a diode connected to the terminals of said first, second, third, fourth, fifth and sixth switch;
• the invention comprises one or more of the following characteristics, alone or in a technically acceptable combination.
• the secondary circuit comprises:
• the secondary circuit further comprises a capacitor disposed between the output terminals of the secondary circuit.
• FIG. 2 is a timing diagram representing the evolution of the state of the components of the circuit shown in FIG. 1, and the evolution of currents and voltages between different points of the circuit.
• FIG. 3.1 is a schematic representation of part of the electrical circuit of Figure 1, active during a portion of the operating cycle of the circuit, said portion of the cycle being between the times t 3 and t 3inj of the time axis of the timing diagram of FIG. 2.
• FIG. 3.2 is a schematic representation of part of the electrical circuit of Figure 1, active during a portion of the operating cycle of the circuit, said portion of the cycle being between the times t 3inj and t 4 of the time axis of the timing diagram in figure 2.
• FIG. 3.3 is a schematic representation of a part of the electrical circuit of FIG. 2, active during a portion of the operating cycle of the circuit, said portion of the cycle being between the times t 4 and t 5 of the time axis of the timing diagram in figure 2.
• FIG. 3.4 is a schematic representation of part of the electrical circuit of Figure 1, active during a portion of the operating cycle of the circuit, said portion of the cycle being between the times t 8 and t 8inj of the time axis of the timing diagram of Figure 2.
• FIG. 3.5 is a schematic representation of part of the electrical circuit of FIG. 1, active during a portion of the operating cycle of the circuit, said portion of the cycle being between the times t 8inj and t 9 of the time axis of the timing diagram in figure 2.
• FIG. 3.6 is a schematic representation of a part of the electrical circuit of FIG. 2, active during a portion of the operating cycle of the circuit, said portion of the cycle being between the times t 9 and t 10 of the time axis of the timing diagram in figure 2.
• FIG. 4 is a schematic representation of the steps of the method according to the invention.
• FIG. 5 is a schematic representation of a second embodiment of the secondary circuit according to the invention.
• FIG. 6 shows a third embodiment of the secondary circuit according to the invention, with in Figure 6a a first schematic representation of said third embodiment, and in Figure 6b a second equivalent schematic representation of said third embodiment.
• FIG. 7 is a schematic representation of a fourth embodiment of the secondary circuit according to the invention.
• FIG. 1 is an equivalent electric diagram of a converter 1 according to one embodiment of the invention.
• the diagram in figure 1 shows two parts 2, 3.
• the first part 2 comprises a first portion 2 ′ of the primary circuit and a secondary circuit 2 ′′.
• the first portion of the primary circuit 2 ′ comprises two input terminals E1, E2 configured to receive an input voltage V in . It also includes a first pair of switches A, B connected in series, in other words as a bridge arm between the two input terminals E1, E2, as well as a second pair of switches C, D connected in series, otherwise said as a bridge arm between the two input terminals E1, E2.
• the first pair of switches A, B, and the second pair of switches C, D thus form two bridge arms, both connected in parallel between the two input terminals E1, E2.
• Each bridge arm comprises a midpoint PAB, PCD at a connection point located between the two switches of said bridge arm.
• the midpoints PAB, PCD of each bridge arm are connected by a primary coil coupled to a secondary coil of the secondary circuit 2 ".
• Said primary coil is characterized by a leakage inductance L k ; it receives between its terminals, connected to the points medium PAB, PCD, a primary voltage V p determined in particular by the open or closed state of switches A, B, C and D.
• a parallel capacitor is arranged so as to connect the respective terminals of each of said switches A, B, C, D.
• the capacitance of said parallel capacitor is greater than the intrinsic capacitance, linked to the composition of the transistors, of each switch A, B, C,
• the second part 3 of the diagram describes the second portion 3 of the primary circuit, complementary to the first portion 2 ′ of the primary circuit, so that, according to the embodiment of the invention described here, the primary circuit comprises the second portion 3 which will now be described, coupled to the first portion 2 'described above.
• Said second portion 3 of the primary circuit comprises a pair of injection switches E, F in series, in other words as a bridge arm, between the two input terminals E1, E2.
• the pair of injection switches E, F thus form a third bridge arm, connected in parallel between the two input terminals E1, E2.
• Said third bridge arm comprises a midpoint PEF at a connection point situated between the two injection switches E, F of said third bridge arm.
• This midpoint PEF and the midpoint PAB of one of the two bridge arms described above are electrically connected by an injection circuit characterized by its injection inductance L inj .
• a diode inherent in the construction of the switch, is present in parallel with the switches A, B, C, D, E, F, in which, the cathode of the diode is electrically connected to the drain, or to the collector of the switch and the anode of the diode is electrically connected to the source, or to the emitter of the switch.
• This diode is intrinsic to metal-oxide gate field effect transistors, otherwise called MOSFETs according to the acronym; a diode is added in the case of the use of bipolar transistors with insulated gate, otherwise called IGBT according to the English acronym.
• the recombination charges of the diode must be negligible compared to the charges corresponding to the capacities of said parallel capacitor.
• Silicon carbide (SiC) or galium nitrite (GaN) diodes are suitable for this invention, according to those skilled in the art. More generally, an SiC MOSFET transistor, or a GaN high mobility electron transistor, otherwise called HEMT according to the English acronym, or a fast IGBT transistor with an SiC diode in parallel, according to the preceding description, characterized by a high recombination speed of minority carriers, are suitable for switches A, B, C, D, E, F. The diode in parallel with the switches, conducts spontaneously, that is to say when the electric potential of its anode becomes superior (typically +0.5 Volt), at its cathode. The control of switches A, B, C, D, E, F is used to short-circuit this diode.
• each switch A, B, C, D, E, F comprises, according to an equivalent circuit diagram of said switch, a "perfect" switch A, B, C, D, E, F and a diode, intrinsic or added.
• the term switch will designate the perfect switch, forming said switch with the diode, intrinsic or added, depending on the embodiments.
• setting a switch to ON corresponds to setting the corresponding perfect switch to ON, said setting to ON of the perfect switch which can occur when the corresponding diode is already conducting, so that the switch, formed by the perfect switch and the corresponding diode, is already partly closed.
• the assembly formed by the first portion 2 ′ of the primary circuit, coupled as indicated above to the second portion 3 of the primary circuit constitutes the primary circuit 3 ′ of the converter 1.
• Said primary circuit thus formed receives between these input terminals E1, E2 an input voltage V in , transformed into a primary voltage V p , determined in particular by the state of the switches A, B, C and D, at the terminals of the primary coil.
• Said primary coil is magnetically coupled to a secondary coil of secondary circuit 2 "which will now be described.
• the terminals of said secondary coil are connected in parallel, on the one hand by a fourth bridge arm formed by a fourth pair of switches SR1, SR2, with common sources or with common anode in the case of using only two diodes.
• a fifth bridge arm formed by a pair of inductors L1, L2 arranged in series between the terminals of the secondary coil.
• a midpoint PLIL2 of the fifth bridge arm, located at the connection point between the two inductors L1, L2, and a midpoint P SR1SR2 of the fourth bridge arm, located at the connection point between the two switches SR1, SR2, are directly and respectively electrically connected to the output terminals S1, S2 of the converter 1.
• a capacitor is placed between said output terminals S1, S2.
• the function of the secondary circuit 2 "can be achieved according to at least one other embodiment, as illustrated in FIGS. 5, 6 and 7, as follows:
• each switch A, B, C, D, E, F is configured to be controlled by a control unit not shown in FIG. 1.
• each switch A, B, C, D, E, F is configured to receive a signal from the control unit; depending on the signal received, the switch is either on, i.e. lets current flow, in other words is closed, or the switch is blocking, i.e. does not pass current, in other words is open.
• the switch when the switch is on, it will be described as being on ON, and when the switch is blocking, it will be described as being on OFF.
• the converter 1 is configured to transform an input voltage V in between the input terminals E1, E2 of the primary circuit 3 ', into an output voltage V out between the output terminals S1 S2 of the secondary circuit, according to a method who go now be described, with reference to the timing diagram of FIG. 2, which represents the evolution as a function of time of the state of switches A, B, C, D, E, F of the primary circuit of converter 1, and the evolution as a function of time of the currents and voltages between the terminals of the various components of the primary and secondary circuits.
• the switches, currents and voltages considered are represented along the vertical axis of the timing diagram of figure 2, and the different instants t 0 , t 0end , t 1 , t 2 , t 3 , t 3inj t 4 , t 5 , t 6 , t 6end , t 7 , t 8 , t 8inj t 9 , tio, of an operating cycle of the converter 1 are shown on the horizontal axis.
• control unit is configured so that, during an operating cycle of the converter 1, the control unit of the converter 1 successively controls the carrying out of the following steps 101 to 113 of the method 100, schematically represented in FIG. 4: - 101: set the first switch A to ON, at a first instant t 0 ;
• - 103 set the third switch C to ON, at a third instant t 3 of the cycle;
• - 104 set the first switch A to OFF, at a fourth instant t 4 of the cycle;
• - 105 set the second switch B to ON, at the fifth instant t 6 of the cycle;
• - 106 set the third switch C to OFF, at a sixth instant t 7 of the cycle; - 107: set the fourth switch D to ON, at a seventh instant t 8 of the cycle;
• - 108 set the second switch B to OFF, at an eighth instant t 9 of the cycle
• - 109 set the sixth switch F to ON at a first injection instant t 3inj between the third instant t 3 and the fourth instant t 4 so that an injection voltage applies between the poles of the injection inductance L inj for a duration t cmd_inj , until the fourth instant t 4 of the cycle, and that at the fourth instant t 4 of the cycle an injection current l Linj circulates in the injection inductor L inj , said injection current l Linj being greater than a predetermined minimum current; - 110: set the sixth switch F to OFF at the fourth instant t 4 ; - 111: set the fifth switch E to ON at a second injection instant t 8inj between the seventh instant t 8 and the eighth instant tg so that an injection voltage applies between the poles of the inductor injection L inj during the duration t cmd_inj until the eighth instant t 9 of the cycle, and so that
• - 112 set the fifth switch E to OFF at the eighth instant tg; - 113: repeat steps 101 to 112 of the cycle from a ninth instant t 10 .
• the instant t 0 is thus both the end of a previous cycle, and the start of the next cycle of the operation of the converter 1.
• the order of presentation of steps 101 to 113 of the steps does not correspond to the order according to which said steps follow each other in time.
• the order of temporal succession of the steps is determined by the instants which define each step and according to the chronology illustrated in FIG. 2.
• a chopping period T, or duration T of a complete cycle is also used, said duration T being a predetermined constant, and a second dead time t dead_C_D, said second dead time corresponding both to a time interval between t 2 and a time when the diode of switch C becomes conductive, and at a time interval between t 7 and a time when the diode of switch D becomes conductive, the second dead time being adjusted to guarantee switching soft of the bridge arm C, D, from the moment when the injected current I inj , flowing in L K during this phase, is sufficient to ensure smooth switching.
• phase shift between the bridge arms A, B and C, D is defined by the relation:
• t mort_C_D [C res -V in ] / (I Ltcom ). (N s / N p ) with the I Ltcom current defined by:
• I Ltcom (I L1 + I L2 ) / 2 where I L1 is the current in induction L1 at time t 2 and I L2 is the current in induction L2 at time t 7
• the instants of switching to ON of the injection switches E, F are respectively the second instant and first instant of injection t 8inj , t 3inj ; the time during which these injection switches E, F are ON must allow the injection inductance L inj to be precharged to the desired injection current level L Linj.
• the injection current level l Linj must make it possible to compensate for the lack of inductive energy available with the leakage inductance L K.
• the level of the critical current l LK in the leakage inductance L K is that defined for the injection activation criterion, multiplied by a margin coefficient to be adjusted if necessary to guarantee smooth switching.
• the margin coefficient Kmarge is dimensioned so that the diode B, in parallel with the transistor B, conducts during the time interval between the instants t5 to t6, thus guaranteeing the soft switching.
• the gate voltage of transistor B can be suitably applied at t6, i.e. transistor B closes while the voltage between the drain and the source is negative corresponding to the conduction threshold voltage of the diode B, in parallel with transistor B.
• the voltage before the closing of the transistor is -0.5 Volt, that is to say very close to 0. It is the soft switching when a transistor B is turned ON.
• Kmarge 1.2.
• the level of the critical current l LK in the leakage inductance L K is defined so as to cancel the voltage at the terminals of switch B (respectively A), therefore at the terminals of the parallel capacitor placed between the terminals of switch B (respectively A), between ts and t 6 where switch B can be turned to ON favorably (respectively at the start of the cycle, between the end of a previous cycle and the start of the next cycle where switch A can be put to ON favorably).
• Cancellation is naturally achieved when the inductive energy of the circuit is sufficient to fully transfer the capacitive energy, i.e. cancel the voltage across switch B (respectively A) and establish the voltage across switch A ( respectively B).
• the injection inductance Linj precharged beforehand to a certain level of injection current l Linj during the so-called freewheeling phase which precedes the fourth instant t4 (respectively, the eighth instant t9).
• the inductive energy stored in the injection inductor L inj is added to the inductive energy of the leakage inductor L K on opening, ie at the switch A (respectively switch B) to OFF to discharge the parallel capacitor of switch B (respectively the parallel capacitor of switch A) and charge the parallel capacitor of switch A (respectively the parallel capacitor of switch B).
• the condition for activating the current injection results from the comparison between inductive energy and capacitive energy, defined below.
• the parallel capacitors installed in parallel with the switches A, B, C and D each have a capacitance C res of much greater value than the parasitic capacitances of the components. We can therefore neglect the capacitive energies of the components.
• the capacitive energy to be considered is thus defined by the formula:
• the value of the inductance of the leakage inductance L k of converter 1 deliberately high to reduce the overvoltages linked to the recovery currents of the rectifier diodes SR1, SR2 of the secondary stage, makes the contribution negligible. from the energy of the magnetizing inductance of converter 1 to the inductive energy of the circuit.
• the current in the leakage inductance L k of converter 1, at time t4 (respectively t9) is between the image of the maximum current and the image of the average current in L1 (respectively L2, L1 and L2 being identical ).
• L1 the image of the average current in L1 (respectively L2, L1 and L2 being identical ).
• the inductive energy to be considered is defined by the formula:
• L K , Ns, Np and Cres are fixed and known quantities of the circuit, Vin is measured and does not depend on the output power. Only read, measured by the control unit of converter 1, depends on the output power.
• the preparation for the injection of the current begins with the setting on ON of the switch E at a first instant of injection t 8inj as illustrated on the diagram of the corresponding equivalent circuit shown in figure 3.5, the objective being to preload the injection inductor L inj with an injection current l Linj of the same sign as the current l LK seen from the midpoint PAB of the bridge arm A, B, both positive currents according to the sign conventions adopted.
• the time period between an instant t 10 and the instant t 0 end constitutes a phase of return to the rest state, said instant t 0 end being the moment when the current s' cancels in injection induction.
• the freewheeling diode of switch F and switch A being both on, the voltage across the injection inductor L inj is V in , which increases its current linearly up to its cancellation, leading to blocking of the freewheeling diode of switch F.
• the converter 1 implemented for example on a 10kW, 700Vin / 110VDCout battery charger operated with a power range of between 100% and 0.4% of its nominal power.
• the arrangements described above thus make it possible to operate at a very low load. without causing thermal and electrical stresses on the power semiconductors A and B.
• the peak currents of IL1 and IL2 were sized by the value of L1 and L2, so that the energies 1 ⁇ 2.L1. [IL1. (Ns / Np)] 2 and 1 ⁇ 2.L2. [IL2. (Ns / Np)] 2 respectively in t2 and t7 are much greater than Vin 2 .Cres.
• [L LK ] 2 in t2 and in t7 is much less than 1 ⁇ 2.L1.
• a fourth bridge arm can then be added with a second Linj inductor in PCD, to ensure the smooth switching of switches C and D.
• the current injection technique can also be used in Dual Active Bridge (DAB) applications to ensure smooth switching of low load power switches according to the same sequencing described in figure 2.
• DAB Dual Active Bridge

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• Dc-Dc Converters (AREA)

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• 2020
  • 2020-01-16 FR FR2000401A patent/FR3106457B1/fr active Active
• 2021
  • 2021-01-07 EP EP21704848.7A patent/EP4115512A1/de active Pending
  • 2021-01-07 WO PCT/FR2021/050020 patent/WO2021144521A1/fr unknown
  • 2021-01-07 US US17/793,594 patent/US20230139340A1/en active Pending

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