Classifications

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Definitions

• the present invention relates to an electronic system adapted to be attached to a printed circuit, the printed circuit can then be mounted in an electronic device, for example, a smart phone.
• an electronic system may comprise several electronic chips which are mounted in a housing to form an interface between the electronic chips and the printed circuit, known to those skilled in the art under its English designation "Printed Circuit Board” (PCB) .
• PCB printed Circuit Board
• the housing has connection ports.
• the patent application US2016 / 0064342 discloses a system comprising an electronic chip, comprising connectors, which is positioned on a lower support with the connectors placed upwards.
• the lower bracket has metal connection ports.
• a metallic redistribution layer is placed on the connectors of the electronic chip to form a system. Through vias connect the redistribution layer to the connection ports to allow the system to form an interposer between a printed circuit and an auxiliary system.
• Such a system requires many steps of realization (creation of vias, etc.), which increases its cost.
• the redistribution layer has a large thickness and requires many preparation steps before it can be connected to the electronic chip, which has disadvantages.
• the invention relates to an electronic system comprising a front surface, the electronic system comprising:
• a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of internal connection ports
• each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component being positioned facing the lower redistribution layer on the side of the ports; internal connections,
• the electronic components can be conveniently and losslessly connected to each other.
• the connection ports of the system are easily configurable and the system can be directly mounted on an integrated circuit.
• Such a system can advantageously receive electronic components of different types and connect them conveniently.
• the lower redistribution layer makes it possible to offer great flexibility in the arrangement of the connection ports of the system, that is to say, the lower connection ports of the lower layer.
• the invention relates to an electronic system comprising a front surface, the electronic system comprising:
• a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of internal connection ports forming the connection ports of the system, the lower redistribution layer being formed by a plurality of interconnections made by metal deposition,
• each electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component being positioned facing the lower redistribution layer on the side of the internal connection ports,
• the electronic component (3) to the internal connection ports of the lower redistribution layer the plurality of interconnections being made by metal deposition in openings formed in a layer of photoresist, said openings defining the shape of the three-dimensional interconnections , and
• the three-dimensional interconnections extend only in the bottom of the openings formed in the photoresist layer.
• the ends of the three-dimensional interconnections are located at different vertical distances.
• the system comprises a plurality of vertically assembled electronic components to form a stack.
• all the connectors of the electronic components are connected to the connection ports optimally with a small footprint.
• the electronic components have the same orientation in the stack.
• the electronic component comprises raised conductive pads on the connectors of said electronic component.
• Such elevation studs make it possible to vertically shift the connectors relative to the front surface of the electronic component.
• the conductive pads extend in vertical projection from the front surface of the electronic component.
• elevation pads make it possible to improve the compatibility with the interconnections or to offset the position of the connectors in order to limit the risk interference between the three-dimensional interconnections and the electronic component.
• the reported elevation pads are formed prior to the step of making three-dimensional interconnection.
• the elevation pads make compatible the three-dimensional interconnections with the connectors of the electronic component by forming a compatible metal interface.
• the electronic system comprises:
• a first stack of electronic components forming a lower subsystem, the rear surface of an electronic component of which belongs to the front surface of the lower subsystem,
• an elevation redistribution layer formed between the lower subsystem and the upper subsystem so as to connect them.
• An overall electronic system formed of a plurality of subsystems which are vertically stacked together is advantageously formed.
• the elevation redistribution layer makes it possible to connect the connection ports of the lower subsystem with those of the upper subsystem.
• the electronic system comprises a plurality of upper subsystems, two adjacent upper subsystems being connected by an elevation redistribution layer.
• the electronic system comprises a plurality of upper subsystems, two adjacent upper subsystems being connected by an elevation redistribution layer.
• the invention relates to a method for manufacturing an electronic system comprising:
• the lower connection ports of the system are made conveniently accessible.
• the system can thus be directly mounted on an integrated circuit.
• Such a system can advantageously receive electronic components of different types and connect them conveniently.
• the lower redistribution layer makes it possible to offer great flexibility in the arrangement of the connection ports of the system, that is to say, the lower connection ports of the lower redistribution layer.
• the invention also relates to a method for manufacturing an electronic system comprising:
• a step of applying a sacrificial element to a support piece a step of producing a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of internal connection ports forming the connecting the system, the lower redistribution layer being formed by a plurality of interconnections made by metal deposition,
• each electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component; being positioned next to the lower redistribution layer on the side of the internal connection ports,
• the interconnections connecting the connectors of the electronic component to the internal connection ports of the lower redistribution layer are made in one go, during the same step.
• the three-dimensional interconnections extend only in the bottom of the openings formed in the photoresist layer.
• the ends of the three-dimensional interconnections are located at different distances.
• the method comprises a plurality of electronic component transfer steps and a plurality of three-dimensional redistribution layer production steps.
• the lower redistribution layer is planar.
• the method comprises a step of depositing a passivation layer so as to cover the surface of the lower redistribution layer and the electronic component while keeping the plurality of internal connection ports uncovered.
• the method comprises a plurality of steps of producing lower redistribution layers and passivation layers so as to make a stack of metal connections.
• a stack makes it possible to route a high density of electrical connections and to easily have the lower connection ports of the system.
• the sacrificial element is in the form of an adhesive film, in particular, double-sided.
• Such a sacrificial element is simple to manipulate for an operator.
• a double-sided adhesive film secures the support and the electronic components together temporarily during the production of the system.
• the sacrificial element is in the form of an adhesive resin layer.
• the sacrificial element is in the form of a non-adhesive polymer layer.
• the sacrificial element is configured to lose its adhesion characteristics from a predetermined temperature. Such a sacrificial element can be conveniently removed without mechanical action that can damage the system being made. In a preferred manner, the sacrificial element loses its adhesion characteristics from a temperature below 250 ° C., which avoids damage to the system during heating.
• the sacrificial element is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics.
• a sacrificial element of the type Brewer Science's "BrewerBond” ®, 3M “WSS” or Sekisui "SELFA” is particularly suitable.
• the sacrificial element is selected from Brewer Science's "ZoneBond” ®, “BrewerBond” ® and “WaferBond” ®, 3M “WSS” ®, Sekisui “SELFA” ®, and Revalpha® from Nitto.
• Such sacrificial elements have optimal characteristics for a reduced cost. It goes without saying that other trade names of other companies may also be appropriate.
• the sacrificial element allows the electronic system to take off by mechanical action without deterioration.
• a sacrificial element of the type "TM-X12" ® of Hitachi Chemicals is particularly suitable.
• lower connection ports extend below the electronic component.
• the lower connection ports are conveniently positioned and independent of the electronic component.
• the method comprises a step of producing an upper redistribution layer connected to connectors of said electronic component.
• the upper surface and the lower surface of the component allow a similar redistribution on each side of the electronic component, which facilitates the realization of a system with high integration density.
• the method comprises a step of deposition of at least one electronic component on the upper redistribution layer, each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component being positioned opposite the upper redistribution layer.
• Stacks of components can thus be mounted in stages thanks to the presence of the upper redistribution layer which makes it possible to offer easily accessible connection ports for connecting two different stacks with three-dimensional interconnections. We can thus form very complex and very dense systems.
• the method comprises a step of making an opening in the system so as to discover the front face of at least one electronic component having a sensor function.
• the method is compatible for the realization of a system having a sensor function.
• the method comprises a step of placing conductive beads on the lower connection ports of the lower redistribution layer.
• the method comprises at least two steps of depositing a passivation layer in order to protect the interconnections in the system.
• the method comprises at least two steps of producing a plurality of three-dimensional interconnections in order to form a plurality of superimposed redistribution layers. Complex redistributions can then be carried out in a practical way.
• the method comprises a step of producing a passivation layer prior to the lower redistribution layer.
• This passivation layer comprises openings for producing lower connection ports accessible for welding. It is thus possible to protect the lower redistribution layer and to improve the robustness and reliability of the electronic system.
• the method comprises a step of forming a three-dimensional passive component during the step of producing a plurality of three-dimensional interconnections.
• a three-dimensional passive element is preferably made in a single step, which accelerates the realization of the system.
• the method comprises a step of depositing a metal layer on the rear surface of at least one electronic component so as to improve the heat dissipation.
• the method comprises a step of transferring at least two superimposed electronic components to the lower redistribution layer and a step of connecting the connectors of said electronic components during step embodiment of a plurality of three-dimensional interconnections.
• Complex assemblies can advantageously be made in a system.
• an electronic system having heterogeneous electronic components based on three-dimensional interconnections is produced in a practical and inexpensive manner.
• Advantage is thus advantageously taken of the vertical dimension to increase the integration density.
• the lower redistribution layer facilitates the arrangement of the connection ports.
• at least one connector and at least one internal connection port of the lower redistribution layer are separated by a vertical distance greater than 10 ⁇ , preferably greater than 40 ⁇ , and three-dimensionally interconnected.
• the vertical direction is defined orthogonally to the horizontal direction along which the sacrificial element extends. Such spacing imposes significant technical constraints for the interconnection.
• At least one interconnection connecting at least one connector and at least one internal connection port, has a shape ratio greater than 2.5: 1, preferably greater than 5: 1, more preferably greater than 10: 1 for a vertical distance of between 10 ⁇ and 100 ⁇ . Beyond a vertical distance of ⁇ ⁇ , this aspect ratio is greater than 1 .5: 1, preferably greater than 3: 1, more preferably greater than 6: 1. As a reminder, the aspect ratio corresponds to the vertical distance traversed by the interconnection over its width.
• the method comprises a step of depositing a passivation layer so as to cover the surface of the lower redistribution layer and the electronic component while keeping the plurality of connectors of the electronic component and the internal connection ports uncovered.
• the passivation layer is deposited conformably, that is to say, with a variation in its thickness on the horizontal and / or vertical walls and / or undercut and / or undercut less than 50 %, preferably less than 25%.
• FIGS. 1A-1I are schematic representations of steps for producing a system according to the invention.
• FIG. 2 is a schematic representation of an electronic component
• FIG. 3 is a schematic representation of a system with connection balls integrated in a passivation layer
• FIG. 4 is a schematic representation of a system with two passivation layers
• FIG. 5 is a schematic representation of a system with two metal layers of three-dimensional interconnections
• FIG. 6 is a schematic representation of a system with an access opening to an electronic component having a sensor function
• FIGS. 7 and 8 show a system comprising a surface mounted component
• FIG. 9 represents a system comprising a three-dimensional passive component
• FIGS. 10 and 11 show several embodiments of com systems carrying a redistribution layer placed in the upper part so as to connect to other electronic components, and
• FIG. 1 2 is a schematic representation of the mounting of a system according to the invention on an integrated circuit.
• An electronic system comprising a plurality of electronic components adapted to be mounted on a printed circuit to form an electronic card.
• Such an electronic card can be mounted in all kinds of devices electronic devices, for example, a computer, a watch, a smart phone, a connected object, a garment, a portable equipment, etc.
• a "system in package” system is formed which comprises several electronic components.
• a system comprising conductive balls but it goes without saying that it is also possible to make a system of the type QFN or LGA whose connection ports extend in the same plane in the continuity of said system, that is to say, without being protruding.
• FIG. 1A there is shown a step of applying a sacrificial element 2 to a support piece 1.
• the support piece 1 is in the form of a flat surface based on silicon, glass, ceramic, metal, organic materials or any type of materials that can be used as a support.
• the support part 1 is preferably circular or rectangular, but it goes without saying that other shapes could be suitable.
• the support surface is greater than 2000 mm 2.
• the sacrificial element 2 has a dual function. It allows, on the one hand, to accurately and robustly position the lower redistribution layer 7 of the system during its production and, on the other hand, to be able to release it when the system is made. In other words, the sacrificial element 2 forms a temporary support for the lower redistribution layer 7 so that it is integrated in the system S.
• the sacrificial element 2 is in the form of a layer that is organic, inorganic, polymeric or metallic.
• the sacrificial element 2 may be deposited by centrifugal coating, by spraying, by lamination, by pressing, by growth or the like.
• the element sacrificial 2 is in the form of an adhesive film which is simple to handle, in particular double-sided.
• the sacrificial element 2 is configured to lose its adhesion characteristics from a predetermined temperature.
• a sacrificial element 2 of the "Revalpha" ® type from Nitto is particularly suitable.
• the sacrificial element 2 is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element 2 converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics.
• a sacrificial element 2 of the "BrewerBond” ® type of Brewer Science or “WSS” ® of 3M or “SELFA” ® of Sekisui is particularly suitable. More preferably, the sacrificial element 2 allows takeoff of the system by mechanical action without deterioration.
• a sacrificial element 2 of the "TM-X12" type of Hitachi Chemicals is particularly suitable.
• FIG. 1B there is shown a step of producing a plurality of interconnections made by metal deposition on the sacrificial element 2 in order to form a lower redistribution layer 7 defining a plurality of lower connection ports 71 connected to a plurality of internal connection ports 72.
• Such a redistribution layer 7 makes it possible to connect connection ports 71, 72 which are distant from each other in order to improve the integration.
• the lower redistribution layer 7 has lower connection ports 71 in contact with the sacrificial element 2 and internal connection ports 72, in the upper part, intended to connect with electronic components 3.
• the lower connection ports 71 form the connection ports of the system S.
• FIG. 1B there is shown a step of depositing a first passivation layer 4 so as to cover the lower redistribution layer 7 while forming openings 40, while now uncovered a plurality of internal connection ports 72 of FIG. the lower redistribution layer 7.
• the first passivation layer 4 may be composed of an organic or inorganic material, such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating material. It can be deposited by coating centrifugal, by spray, by lamination, by pressing, by growth, by printing (inkjet), by vacuum deposition or by any type of deposit known to those skilled in the art.
• the apertures 40 are made using a photolithography method or using a wet chemical etching or dry, plasma or laser. In a preferred manner, photosensitive materials are preferred in view of the advantages offered by the photolithography processes.
• the deposition of the first passivation layer 4 is optional, the electronic components 3 being able to be deposited directly on the lower redistribution layer 7.
• the method comprises a step of transferring at least one electronic component 3 to the first passivation layer 4.
• each electronic component 3 comprises a front surface 3A comprising a plurality of connectors 30 and a rear surface 3B opposite to the front surface 3A.
• the rear surface 3B of each electronic component 3 is devoid of connectors 30.
• the rear surface 3B of the electronic component 3 is positioned in contact with the first passivation layer 4, facing the lower redistribution layer 7.
• the components 3 are positioned outside the openings 40 of the first passivation layer 4 as shown in Figure 1 C.
• two electronic components 3 are positioned directly in contact with the first passivation layer 4 and are designated electronic components of rank 1.
• Other electronic components can be positioned in superposition on the electronic components 3 of rank 1, these electronic components 3 being designated electronic components of rank 2.
• the component 3 superimposed electronic has a rank n + 1.
• an electronic component of rank 2 is positioned on one of the electronic components of rank 1.
• the rear surface 3B of the electronic components 3 of rank 1 is positioned on the first passivation layer 4.
• the positioning of the electronic components 3 is preferably performed by a so-called "pick and place” transfer method.
• a layer of adhesive is applied between two superimposed electronic components 3.
• the adhesive layer is deposited between the rear surface 3B of the electronic component 3 of higher rank and the front surface 3A of the electronic component 3 of lower rank. Precise positioning ensures optimum interconnection.
• the total vertical thickness (electronic component (s) 3 and layer (s) of glue) is greater than ⁇ ⁇ , more particularly greater than 40 ⁇ .
• the flanks of the electronic components 3 can be straight, undercut and / or undercut. For the sake of clarity, only electronic components 3 having straight flanks have been used in the figures.
• the electronic system S comprises several electronic components 3 assembled vertically to form a stack.
• the electronic components 3 have the same orientation in the stack.
• the rear surface 3B of the electronic component 3 of higher rank is mounted on the front surface 3A of the electronic component 3 of lower rank. It goes without saying that the electronic system S could comprise a stack of a large number of electronic components 3 of different natures.
• each electronic component 3 of higher rank of a stack has dimensions smaller than the electronic component 3 of lower rank so as to form a stack facilitating the formation of three-dimensional interconnections between the various electronic components 3.
• the compactness and the Integration density is thus increased in a practical way.
• the stack is pyramidal or walking stairs. According to the latter case, it is possible to stack electronic components 3 having an identical size or electronic components 3 of larger size over smaller electronic components 3. It goes without saying that the electronic components 3 may have different dimensions. In the absence of a passivation layer 4, the electronic components 3 are transferred directly to the lower redistribution layer 7.
• the second passivation layer 4' is deposited in a compliant manner or One way to adapt the angle of the flanks of the electronic components 3.
• the second passivation layer 4 ' may be composed of an organic or inorganic material, such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating material. It can be deposited by centrifugal coating, by spray, by lamination, by pressing, by growth, by printing (inkjet), by vacuum deposition or by any type of deposit known to those skilled in the art.
• photosensitive materials are preferred in view of the advantages offered by the photolithography processes.
• the passivation layer 4 ' is deposited solely to cover the flanks of the electronic components 3 and a part of the surface of the electronic component 3, thus forming a sarcophagus around said electronic component 3.
• the openings 40 in the passivation layer 4 are directly accessible to the three-dimensional interconnections.
• the deposition of the second passivation layer 4 ' may not be applied, thus reducing the time and cost of manufacture.
• This metal layer may be composed of one or more electrically conductive materials and / or semiconductors.
• the thickness of the photoresist layer may vary from at 700 ⁇ and the aspect ratio (resolution) from 0.5: 1 to 50: 1.
• a step of depositing a metal layer by electrolysis or any other metal growth technique may be a step of depositing a metal layer by electrolysis or any other metal growth technique.
• the deposited metal may be copper, gold, silver, nickel, a metal alloy, or any other electrically conductive material.
• the lower connection ports 71 and the connectors 30 of the electronic components 3 are respectively interconnected by the redistribution layer formed by the three-dimensional interconnections 5 made by metal deposition and by the lower redistribution layer 7.
• the three-dimensional interconnections 5 are made in one and the same step, which provides a significant time saving.
• the number of connectors 30 interconnected depends on the degree of interaction between the two electronic components 3 in the electronic system S.
• the planar redistribution layer improves the routing between the electronic components 3 and the input ports / outputs of the system S, in particular, in case of high density of connectors 30.
• an encapsulation step 6 is represented so as to encapsulate the electronic components 3 and the interconnects 5.
• the encapsulation layer 6 is made of polymer, for example epoxy, and charged or not with particles such as silica, alumina, etc. but it goes without saying that other similar materials might be suitable.
• the encapsulation step is performed by screen printing, injection molding, transfer or by pressure. Such an encapsulation layer 6 advantageously makes it possible to improve the mechanical robustness as well as the reliability of the electronic system S.
• FIG. 1G there is shown a step of separating the systems S from the sacrificial element 2. The separation step depends on the nature of the sacrificial element 2.
• the separation step may be carried out by dissolving or etching, by sliding or by deactivating the sacrificial element 2 with the aid of a laser. , UV or by heating as in the case of the "Revalpha" ® Nitto.
• the assembly is heated to a temperature between 120 ° C and 250 ° C depending on the sacrificial element 2 used, which does not damage the system S.
• the system S comprises conductive balls 150 secured to the lower connection ports 71 of the system S to connect to a printed circuit.
• Such conductive balls 150 are known to those skilled in the art under their English name "micro-bump" and will not be presented in detail.
• the fastening could also be carried out without using conductive balls 150.
• the system S could be in the form of a QFN or LGA type housing having flat 71 lower connection ports.
• a cutting step so as to separate the electronic systems S so that they can be used individually. This produces electronic systems S which can be secured to a printed circuit by different techniques.
• the joining can be carried out with tin, alloys or conductive or insulating glues.
• FIGS. 3 to 11 Several other embodiments of an electronic system S according to the invention are shown with reference to FIGS. 3 to 11. For the sake of clarity and conciseness, the same or similar elements between the other embodiments are referenced with the same numerical reference, only the differences between the embodiments are presented in detail.
• the system S comprises a preliminary passivation layer 400 which is applied to the sacrificial element 2 before making the lower redistribution layer 7 After separating the sacrificial element 2, openings are formed in the lower surface of the system S so as to reach the lower connection ports 71 of the redistribution layer 7.
• This advantageously allows the assembly of conductive balls 150 in the layer preliminary passivation 400 in contact with the lower connection ports 71. This produces a system S comprising conductive balls 150 but whose thickness is reduced.
• a third passivation layer 4 can be applied after the completion of the interconnections 5 and before the encapsulation step, with reference to FIG. the stages of Deposition of the 4 ', 4 "passivation layers and deposition of three-dimensional interconnections 5, 5' can be repeated to meet the need for integration of high density systems S.
• superimposed redistribution layers are formed to allow complex links between a large number of connectors 30 and a large number of lower connection ports 71. This is particularly advantageous for routing a very large number of inputs / outputs, for separately integrating the power supply levels or for integrating a protective shield. the circuit of electromagnetic and electrostatic interference, etc.
• the electronic system S comprises at least one additional electronic element XI, for example a component of the "surface-mounted compound” type, which can be positioned in the system S after the realization of the three-dimensional interconnections (FIG. Figure 7) or before the realization of the three-dimensional interconnections 5 ( Figure 8).
• additional electronic element XI for example a component of the "surface-mounted compound” type, which can be positioned in the system S after the realization of the three-dimensional interconnections (FIG. Figure 7) or before the realization of the three-dimensional interconnections 5 ( Figure 8).
• the additional electronic element XI is thus disposed next to the stack of the electronic components 3. The losses are then reduced.
• the additional electronic element XI is secured before the realization of the three-dimensional interconnections 5, it is the three-dimensional interconnections 5 that make the connection possible, which limits the number of manufacturing steps of the system S.
• the electronic system S comprises one or more three-dimensional passive components X2 which are preferably simultaneously realized at the three-dimensional interconnections 5. The losses are then reduced and the manufacture quick and easy.
• the electronic component 3 comprises raised conductive pads reported on the connectors 30 of said electronic component 3.
• Such elevation pads allow to vertically shift the connectors 30 relative to the front surface 3A of the electronic component 3.
• the conductive pads extend in vertical projection from the front surface 3A of the electronic component 3.
• Such elevation pads make it possible to improve the compatibility with the interconnections 5 or to shift the position of the connectors 30 to limit the risk of interference between the three-dimensional interconnections 5 and the electronic component 3.
• reported elevation pads are formed prior to the three-dimensional interconnection realization step.
• the elevation pads make it possible to make the three-dimensional interconnections 5 compatible with the connectors 30 of the electronic component 3 by forming a compatible metal interface.
• FIG. 10 there is shown a system comprising an upper redistribution layer 7 'created on one or more electronic components 3 of the system S so as to allow the assembly of additional electronic components on the upper face of the system S.
• the upper redistribution layer 7 'is planar is carried out during the same step of realization as the plurality of three-dimensional interconnections 5 as presented above.
• the system S comprises an upper redistribution layer 7 'created above the electronic components 3 on which a first electronic component X3 is mounted via conductive balls 150' and a second electronic component X4. via micro-welded wires.
• a mixed vertical integration can be achieved, which offers great design flexibility.
• a system S may be made comprising a plurality of subsystems SS1, SS2 separated by one or more elevation redistribution layers 7.
• the elevation redistribution layer 7 "is created between a lower subsystem SS1 comprising one or more electronic components 3 and an upper subsystem SS2 comprising one or more electronic components 3.
• the elevation redistribution layer 7 makes it possible to form an electronic system S comprising a stack of subsystems SS1, SS2 each comprising a stack of electronic components 3 as previously described
• the elevation redistribution layer 7 "fulfills the function of the lower redistribution layer 7 when one wants to form an upper subsystem SS2 on a lower subsystem SS1.
• the lower subsystem SS1 is formed as previously taught with reference to FIG. 1, then the elevation redistribution layer 7 "is formed and the upper subsystem SS2 is formed using the elevation redistribution layer. 7 "instead of the lower redistribution layer 7. This forms an electronic system S in elevation called" Build-up ".
• the elevation redistribution layer 7 can be carried out in one or more steps, in this example it is carried out in a first step of three-dimensional interconnection realization and a second step of realization of a planar redistribution layer.
• the elevation redistribution layer 7 " is larger than the surface of the highest electronic component 3 of the lower subsystem SS1 so as to cooperate optimally with the lowest electronic component of the upper subsystem. SS2.
• the elevation redistribution layer 7 “advantageously makes it possible to form the bond between the layers.For preference and according to the need of the system, a passivation layer is deposited below and / or above the redistribution layer of the layer. 7 "elevation. Openings are made in this layer to provide the electrical connections between the three-dimensional interconnects 5 and the elevation redistribution layer 7 ".
• the electronic system S can be connected to a printed circuit 9 by connecting the conductive balls 150 to the tracks of the printed circuit 9.
• the presence of a lower redistribution layer 7 advantageously makes it possible to offer a great freedom for the positioning of the conductive balls 150 in order to adapt to all the constraints of the printed circuit 9.
• the method of manufacture requires only a small number of technological steps to achieve multiple electronic systems S simultaneously, which reduces the time and cost of manufacture.
• the topology can be optimized to improve the electrical and thermal performance and to meet the needs of applications with a large number of inputs / outputs and / or incorporating sensors.
• the three-dimensional integration, using a single layer of metallization or by integrating several layers of metal, provides optimal miniaturization without degrading the functions.
• the various exemplary embodiments have been described for electronic components in the form of electronic chips. Nevertheless, it is recalled that other types of electronic components may be suitable.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Ceramic Engineering (AREA)
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• Production Of Multi-Layered Print Wiring Board (AREA)
• Parts Printed On Printed Circuit Boards (AREA)
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• 2017
  • 2017-08-08 FR FR1757588A patent/FR3070091B1/fr active Active
• 2018
  • 2018-08-08 US US16/637,717 patent/US11133264B2/en active Active
  • 2018-08-08 EP EP18748943.0A patent/EP3665720A1/de active Pending
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