EP3408870A1 - Photovoltaic cell and process for manufacturing a photovoltaic cell - Google Patents
Photovoltaic cell and process for manufacturing a photovoltaic cellInfo
- Publication number
- EP3408870A1 EP3408870A1 EP17706414.4A EP17706414A EP3408870A1 EP 3408870 A1 EP3408870 A1 EP 3408870A1 EP 17706414 A EP17706414 A EP 17706414A EP 3408870 A1 EP3408870 A1 EP 3408870A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- walls
- silicon
- junction
- cells
- buffer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 84
- 239000010703 silicon Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 83
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 27
- 239000000377 silicon dioxide Substances 0.000 claims description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims description 21
- 239000003989 dielectric material Substances 0.000 claims description 17
- 239000011347 resin Substances 0.000 claims description 16
- 229920005989 resin Polymers 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 description 21
- 238000000137 annealing Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052716 thallium Inorganic materials 0.000 description 2
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 2
- 239000006243 Fine Thermal Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000012056 semi-solid material Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
- H01L31/1852—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0475—PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0687—Multiple junction or tandem solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the field of the invention is that of photovoltaic cells and photovoltaic cell manufacturing processes. STATE OF THE PRIOR ART
- III-V material is an alloy of one or more elements of column III of the Mendeleev table with one or more elements of column V of the Mendeleev table, excluding III-V materials containing nitrogen. , boron, thallium or bismuth. This layer of III-V material generally forms a p-n junction on the silicon cell.
- the epitaxy of a layer of III-V material on a silicon layer poses numerous problems, in particular because of the mesh parameter mismatch between these two materials.
- the difference in mesh parameter between the III-V material and the silicon is about 4%, which creates dislocations in the III-V material with density greater than 10 6 cm ⁇ 2 .
- the III-V material and the silicon have very different thermal expansion coefficients, which can cause the layer of III-V material to crack. This phenomenon is named in the English language literature "epilayer cracking".
- the metal grid is located only above the walls so that it does not cover the pn junctions. It therefore does not create shading so that the photovoltaic efficiency of the cell thus formed is improved.
- the mechanical resistance to the collapse of the walls of such a structure is better and therefore allows a better active surface ratio on inactive surface, minimizing the thickness of the walls. A search to minimize the thickness of these walls aims to increase the yield.
- the photovoltaic cell may also have one or more of the following features taken individually or in any technically possible combination.
- each cell contains at least two pn junctions, which increases the efficiency of the photovoltaic cell.
- the pn junction being deposited on the buffer layer, the pn junction comprising a semi-solid material; conductor having a mesh parameter different from that of the substrate, the buffer layer having a mesh parameter identical to that of the pn junction deposited on this buffer layer;
- the method therefore makes it possible to grow pn junctions on a silicon substrate having a mesh parameter different from that of the substrate by minimizing the density of defects in these pn junctions and by optimizing the performance of the photovoltaic cell thus formed.
- the method according to the second aspect of the invention may also have one or more of the following features taken individually or in any technically possible combination.
- the method further comprises the following steps:
- the method comprises a step of depositing a conductive transparent oxide layer interposed between the walls and the metal gate.
- the step of forming the network of walls comprises the following steps:
- the network of walls can thus be easily manufactured by using the upper part of the silicon substrate. The network of walls thus formed is then firmly attached to the silicon substrate.
- the method may comprise an anisotropic etching step of the silicon dioxide layer deposited at the bottom of the cells. This step makes it possible to obtain cells whose bottom consists of silicon. The silicon bottom will then serve as a basis for the epitaxial growth of the buffer layer.
- the method further comprises a step of annealing the silicon substrate so as to prepare the silicon surface at the bottom of the cells.
- the method further comprises an oxidation step, preferably less than 10 nm, followed by deoxidation. This eliminates the silicon damaged in the cavity bottom by the preceding etching step.
- the annealing is preferably carried out at a temperature between 750 ° C and 1100 ° C, and more preferably at a temperature of between 850 ° C and 1100 ° C.
- the annealing is preferably carried out under a hydrogen atmosphere.
- the step of etching the silicon substrate so as to form a network of silicon walls comprises the following steps:
- the method further comprises a step of thinning the silicon walls, the step of thinning the silicon walls comprising the following steps:
- this step also makes it possible to obtain very thin walls, and therefore an important space available for the pn junctions. In addition, it allows to precisely and reproducibly control the width of the walls obtained.
- FIG. 3 an enlargement of a portion of the substrate of Figures 1 h and 2h;
- the method comprises a step 102 for forming a resin mask 3 on the oxide layer 2.
- the resin mask 3 comprises the pattern that one wishes to obtain for the wall network. dielectric material.
- the resin mask 3 has a square or hexagonal section pattern. This pattern comprises openings 4 of width L between 1 ⁇ and 5 ⁇ . These openings 4 are delimited by walls 5 of width between 0.2 ⁇ and 2 ⁇ , and preferably between 0.5 ⁇ and 1 ⁇ .
- the pattern is preferably aligned with the crystallographic directions ⁇ 1 10> of the substrate.
- the method then comprises a step 103 for transferring the pattern of the resin mask 3 into the oxide layer 2 and then into the substrate 1.
- the oxide layer 2 and the substrate 1 are etched.
- the pattern is first transferred into the oxide layer 2 which will be consumed less quickly than the resin mask 3.
- the etching of the substrate can therefore continue even if the resin mask 3 is totally consumed. . Indeed, during this step, the resin mask 3 may be partially or completely consumed.
- the oxide mask may also be partially consumed.
- This etching step 103 makes it possible to form cells 6 in the substrate 1.
- the cells 6 are separated by silicon walls 7.
- the method may then comprise a step of thinning the resulting silicon walls.
- the silicon walls 7 may be partially oxidized so as to form on their surface a layer of silicon dioxide.
- This layer of silicon dioxide is then etched selectively with respect to the silicon.
- This selective etching can be performed by wet etching or hydrofluoric acid vapor. Silicon walls of selected width are thus obtained.
- This thinning step can be repeated several times in order to precisely refine the silicon walls 7. It is indeed advantageous to reduce the width of the walls in order to maximize the area of the cells 6, and therefore, the efficiency of the photovoltaic cell for the same surface unit of the substrate. Indeed, the area occupied by the silicon dioxide walls is lost for photovoltaic conversion.
- the method then comprises a step 104 of oxidation of the silicon walls 7 so as to form walls of silicon dioxide 8 (S1O2).
- This oxidation can be obtained by annealing in an oxygen atmosphere.
- the oxidation of the walls can be partial and in this case, there remains a silicon core in the walls, or total and in this case, all the silicon initially present in the walls is oxidized.
- a layer 9 of silicon dioxide may be formed on the bottom 10 of the cells 6.
- the method may comprise a step 105 of anisotropic etching of the layer 9 of silicon dioxide so as to eliminate this layer 9 of silicon dioxide located at the bottom of the cells.
- the bottom 10 of the cells 6 is made of silicon.
- the process may then include a step of improving the quality of the silicon at the bottom of the cells 6.
- This step makes it possible to prepare the silicon surface present at the bottom of the cells 6 in order to optimize the conditions of the epitaxial growth.
- the impurities present at the bottom of the cells can be removed by wet chemical cleaning or dry plasma.
- This etching step can potentially reduce the width of the walls 8 of silicon dioxide (Si0 2 ).
- the area of silicon damaged by etching can also be removed by a fine thermal oxidation, ie less than 10 nm of formed SiO 2 , followed by a wet chemical deoxidation of the thin oxide layer. formed.
- the damaged silicon in the cavity bottom is eliminated thanks to this sequence.
- the annealing is preferably carried out at a temperature between 750 ° C and 1100 ° C.
- the annealing is preferably carried out at a pressure of between 5 and 760 Torr. Indeed, the silicon crystal present at the bottom of the cells may have been damaged during the step 103 of etching of the silicon walls.
- This annealing step in a hydrogen atmosphere makes it possible to repair the silicon crystal so as to optimize the conditions of the epitaxial growth that will be carried out thereafter.
- This annealing step in a hydrogen atmosphere can also reduce the lateral dimensions of the walls 8 of silicon dioxide (Si0 2 ).
- the method then comprises a step 106 of epitaxial growth of a buffer layer B in each cell 6.
- This buffer layer B has the same mesh parameter as the pn junction which will be deposited on this cell.
- the buffer layer B may thus be a layer of the same semiconductor material as the pn junction which will be deposited on this buffer layer B.
- the buffer layer B may also be a germanium layer, especially when the first pn junction J1 which is deposited on the buffer layer is a layer of GaAs.
- the buffer layer B may also be a layer of AlAs, InP, SiGe.
- the method then comprises a step 107 of epitaxially growing at least a first pn junction J1 on the buffer layer B.
- This first pn junction J1 is a layer of a semiconductor material a lower portion 13 is doped by a first doping and an upper portion 14 is doped by a second doping.
- the lower portion 13 may be p-doped and the upper portion 14 may be n-doped or vice versa.
- the semiconductor material has a mesh parameter different from the silicon mesh parameter.
- the semiconductor material is preferably a III-V material.
- a III-V material is an alloy of one or more elements of column III of the Mendeleev table with one or more elements of column V of the Mendeleev table, excluding III-V materials containing nitrogen. , boron, thallium or bismuth.
- the III-V material may thus be one of the following: GaAs, GaAsP, InP, GalnP, AIGaAs, GalnAsP, GalnAs.
- the cells 6 of square or hexagonal section allow to confine the defects in the buffer layer B in both directions of the growth plane, and they therefore allow to obtain layers of material III-V crystallographic qualities compatible with the realization of a photovoltaic cell.
- the method may also comprise a step 108 of epitaxially growing a second pn junction J2 on the first pn junction J1.
- the second pn junction J2 is a layer of a semiconductor material of which a lower part 15 is doped by a first doping and an upper part 16 is doped by a second doping.
- the lower part 15 may be p-doped and the upper part 16 may be n-doped or vice versa.
- the semiconductor material preferably has the same mesh parameter as that of the first pn junction J2. If this is not the case, a second buffer layer is preferably formed between the first pn junction J1 and the second pn junction J2 as will be seen in the following.
- the semiconductor material is also preferably a III-V material.
- This material may especially be one of the following: GaAs, GaAsP, InP, GalnP, AIGaAs, GalnAsP, GalnAs.
- the method is therefore particularly advantageous because it makes it possible to form multi-junctions of good crystallographic quality by epitaxial growth.
- the process can for example allow to form in each cell 6 a first pn junction J1 GaAs deposited on the silicon substrate and a second pn junction GalnP J2 deposited on the first junction pn.
- the buffer layer B may be GaAs or germanium.
- Between each junction J is also a tunnel diode made by epitaxy of a very fine pn junction. The presence of this diode, necessary for the operation of the cell, is not presented in the diagrams for the sake of clarity.
- the method then comprises a step 109 for producing a metal grid 11.
- This metal grid is called "front metal grid”.
- an upper end of the network of walls of dielectric material is etched so as to form trenches 12 between the pn junctions J2 of adjacent cells 6.
- the metal grid 1 1 is then deposited in these trenches 12 and only in these trenches 12.
- all the walls 8 of dielectric material are not etched but only a part of them. Thus only the walls 8 on which the metal grid 1 1 will be deposited are etched. Indeed, the metal grid 1 1 is not deposited on all the walls 8 so as not to create a short circuit.
- FIG 3 shows an enlargement of a sectional view of a portion of a cell 6 of Figure 1j.
- each trench 12 has a depth P t chosen so that the metal gate 1 1 is in contact only with the upper part 16 of the pn junction J2 to avoid short circuits.
- each trench 12 has a depth P t less than or equal to the thickness edopage of this doped part n.
- the method then comprises a step of producing a rear metal gate (not shown).
- the cells of Figures 2a to 2j have a square section.
- the cells of these figures are aligned along a first axis X and along a second axis Y.
- the cells could also be displaced in one of the two directions X or Y.
- the cells are no longer aligned in one of the two directions, which allows the walls of dielectric material better resist the mechanical and thermal stresses encountered during the manufacturing process.
- the cells could have a hexagonal shape section instead of having a square section as shown in FIGS. 2a to 2j and 4.
- the square section cells allow for better epitaxial growth. quality in the cells. Hexagonal section cells have better mechanical strength.
- each cell could comprise a stack comprising:
- At least one first pn junction having a mesh parameter identical to the first mesh parameter ai;
- a second buffer layer B2 having a second parameter of mesh 2 different from the first parameter of mesh a ⁇ ;
- At least one second pn junction having a mesh parameter identical to the second mesh parameter a 2 .
- FIG. 6 represents a photovoltaic cell according to one embodiment of the invention in which each cell contains a stack comprising:
- a third pn junction J3 having a mesh parameter identical to the second mesh parameter a 2 ;
- a fourth pn junction J4 having a mesh parameter identical to the second mesh parameter a 2 .
- FIG. 7 represents the evolution of the mesh parameter through a cross section made in one of the cells of this photovoltaic cell.
- the substrate could also comprise a transparent conductive oxide layer 17 deposited on the walls 8 and on the pn junction J2 on the surface of the cells 6 so as to promote electrical contact between the metal grid 1 1 and the pn junction J 2 .
- the metal grid 17 is always located at the walls 8 in order to avoid shading, but a transparent conductive oxide layer 17 is interposed between the walls 8 and the metal grid 17.
- the metal grid 17 is therefore aligned with at least a part of the walls.
- the metal grid 17 is only located above the walls.
- the metal gate is therefore located above any pn junction.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Life Sciences & Earth Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1650749A FR3047354B1 (en) | 2016-01-29 | 2016-01-29 | PHOTOVOLTAIC CELL AND METHOD OF MANUFACTURING PHOTOVOLTAIC CELL |
PCT/EP2017/051884 WO2017129810A1 (en) | 2016-01-29 | 2017-01-30 | Photovoltaic cell and process for manufacturing a photovoltaic cell |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3408870A1 true EP3408870A1 (en) | 2018-12-05 |
Family
ID=55451479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP17706414.4A Withdrawn EP3408870A1 (en) | 2016-01-29 | 2017-01-30 | Photovoltaic cell and process for manufacturing a photovoltaic cell |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP3408870A1 (en) |
FR (1) | FR3047354B1 (en) |
WO (1) | WO2017129810A1 (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008124154A2 (en) * | 2007-04-09 | 2008-10-16 | Amberwave Systems Corporation | Photovoltaics on silicon |
KR101093588B1 (en) * | 2007-09-07 | 2011-12-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Multi-junction solar cells |
US8274097B2 (en) * | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
EP2528087B1 (en) * | 2008-09-19 | 2016-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
-
2016
- 2016-01-29 FR FR1650749A patent/FR3047354B1/en not_active Expired - Fee Related
-
2017
- 2017-01-30 WO PCT/EP2017/051884 patent/WO2017129810A1/en active Application Filing
- 2017-01-30 EP EP17706414.4A patent/EP3408870A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
WO2017129810A1 (en) | 2017-08-03 |
FR3047354A1 (en) | 2017-08-04 |
FR3047354B1 (en) | 2018-05-18 |
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