EP3369115A1 - Transistor a effet de champ a rendement et gain optimise - Google Patents
Transistor a effet de champ a rendement et gain optimiseInfo
- Publication number
- EP3369115A1 EP3369115A1 EP16790546.2A EP16790546A EP3369115A1 EP 3369115 A1 EP3369115 A1 EP 3369115A1 EP 16790546 A EP16790546 A EP 16790546A EP 3369115 A1 EP3369115 A1 EP 3369115A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- sub
- buffer layer
- effect transistor
- stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 34
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
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- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
Definitions
- the present invention relates to high-mobility electronic field effect transistors referred to as HEMT transistors, which stands for the High Electron Mobility Transistor.
- the present invention relates, more particularly, to the stacks from which the HEMT transistors used as a low noise or power amplifier are manufactured, as a switch or as an oscillator and covering the frequency range typically between 1 MHz and 100 GHz.
- FIG. 1 schematically represents a section of the structure of a conventional elementary HEMT transistor system, in an Oxz plane, produced on a substrate 11.
- an insulating or semiconductor substrate 11 is used, comprising, for example, silicon (Si), silicon carbide (SiC) or sapphire (Al 2 O 3 ), on which an Emp stack is made according to the axis.
- a first layer 12, referred to as a buffer layer, or more commonly known as the "buffer”, has a wide band gap, referred to as a large gap semiconductor material comprising a material comprising a binary compound such as GaN or a ternary compound of III element nitride, called III-INI, such as AIGaN, or more specifically Al x Gai- x N.
- a second layer has a greater forbidden band than that of the buffer layer 12.
- This layer comprises a material based on quaternary compound, ternary or binary element III nitride, called III-INI, to base of Al, Ga, In or B.
- the barrier layer 13 comprises Al x Ga 1-x N or ⁇ 1- ⁇ ⁇ ⁇ ⁇ , or a sequence
- the forbidden band widths of Al x Ga 1-x N and ln 1-X AI X N vary from 3.4eV (GaN) to 6.2eV (AlN) and from 0.7eV (InN) at 6.2eV (AIN), respectively.
- the thickness of the barrier layer 13 is typically between 5 nm and 40 nm, the thickness of the buffer layer 12 is typically between 0.2 ⁇ and 3 ⁇ .
- the buffer layer 12 and the barrier layer 13 are conventionally made by MOVPE, an acronym for "Metalorganic Vapor Phase Epitaxy", in the English language, or organometallic vapor phase epitaxy, in the French language, or MBE acronym for "Molecular Beam Epitaxy", in English, or molecular beam epitaxy, in French.
- MOVPE Metalorganic Vapor Phase Epitaxy
- MBE MBE acronym for "Molecular Beam Epitaxy” in English, or molecular beam epitaxy, in French.
- the junction between the buffer layer 12 and the barrier layer 13 constitutes a heterojunction 15 which also extends in the Oxy plane.
- the origin O of the Oxyz mark is chosen in this plane.
- An HEMT transistor conventionally comprises a source S, a drain D and a gate
- the gate G is deposited between the source S and the drain D and makes it possible to control the transistor.
- the current between the source S and the drain D is modulated by the electrostatic action of the gate G, conventionally of Schottky type or of MIS type, acronym of metal / insulator / semiconductor, on the two-dimensional electron gas 9, called 2DEG for "Two-Dimensional Electron Gas" located in the vicinity of the heterojunction 15.
- the voltage V G s applied between the gate G and the source S controls the current flowing in the transistor.
- These electrons are movable in the plane Oxy ⁇ and have a high electron mobility, typically greater than 1000 cm 2 / Vs. In normal operation of the transistor these electrons can not circulate in the z direction because they are confined in the potential well forming in the Oxy plane in the vicinity of the heterojunction 15.
- the electron gas 9, confined in what is called the channel of the transistor, is therefore able to carry a current l D s flowing between the drain D and the source S.
- a potential difference V DS is applied between the source S and the drain D, with typically a source S connected to ground, and the value of the current I DS is a function of the applied voltage V GS between the gate G and the source S.
- the transconductance g m of a transistor is defined as the ratio between the current IDS and the voltage V G s. In other words, the transconductance reflects the variation of the drain current as a function of the polarization of the grid VGS J to Vos constant.
- the gain of the transistor is connected to its transconductance. This gain will be higher as its transconductance g m will be large to transform a weak signal applied to the gate G to a stronger signal recovered on the drain D.
- Figure 2 shows the distribution of charges in the vicinity of the heterojunction 15.
- the materials of the family of III-N are strongly electronegative.
- positive fixed electric charges ⁇ + or negative ⁇ - of piezoelectric nature appear at the interface as shown in FIG. 2.
- the resulting fixed surface electrical charge attracts mobile charges: electrons when it is positive as in figure 2 or holes when it is negative. It is these mobile charges em that create a current when a voltage is applied between the drain D and the source S.
- GaN is a semiconductor which, under usual growth conditions, is doped with donor (N) type impurities, typically nitrogen vacancies. This type of defects does not make it possible to obtain effective confinement of the electrons in the channel when the voltage applied to the drain of the transistor becomes too large, typically greater than 10 V, and when the length of the gate Lg becomes too short, typically less than 0.25 ⁇ .
- the electrons then circulate in the buffer layer 12, which causes:
- the region 1 on which the transconductance gm is defined and on which the graphical representation of l D s as a function of V G s associated with the curve Log (l D s) f (V G s) has a substantially linear portion.
- Region 2 corresponds to the zone preferentially used for switching applications, and in particular the zone on which the transfer characteristic of a transistor is defined. It defines the inverse of the slope below the SS threshold.
- Region 3 corresponds to an asymptotic zone in which the leakage current can be defined.
- AV DS constant high, for example 20V, and for a short grid less than 0.25 ⁇ , for example.
- the curve 31 has a high transconductance g m , the inverse of the slope below the SS threshold close to its ideal value of 60mV / decade at ambient temperature and a low leakage current, typically less than ⁇ ⁇ / mm.
- a first solution is to dope P the "buffer" comprising GaN or Al x Gai- x N by introducing acceptor-type impurities, for example by modifying epitaxial conditions or by adding impurities of acceptor type during the growth of the layer.
- the density of impurities introduced in the entirety of buffer layer 12 "buffer” is optimized to obtain the desired transistor behavior.
- the compatible impurities are mainly carbon and iron but may also be magnesium, beryllium or zinc or any impurities known to be an accepting center in GaN.
- an excess of P-type impurities over N-type impurities of 16 cm -3 to 17 cm- 3 makes it possible to maintain the inverse of the slope below the threshold at a value of less than 150 mV / decade for a maximum operating voltage V DS of 50V and a gate length Lg of 0.15 ⁇ .
- These impurities, however, are deep centers.
- a deep center is an impurity whose energy level is more than 2 to 3 times the thermal activation energy (3/2 k b * T) of the minimum of the conduction band for an N-type impurity. or the maximum of the valence band for a P type impurity.
- the thermal activation energy is of the order of 40 meV.
- a center will therefore be considered as deep when it is located at more than 100 meV of one of these extrema, which is the case for the GaN doped with acceptor type impurity.
- These centers are negatively charged when the transistor is energized and as they are deep do not discharge at operating frequencies higher than MegaHertz. This has the effect of reducing the moving load present in the conductive channel, which reduces the current and increases the access resistance. It follows that this approach has the main disadvantage in addition to generating dispersion, reduce the efficiency of the transistor and the power it can emit. This performance degradation is more pronounced than the voltage V DS of the transistor is high, typically greater than 20 V. This reduction in the mobile charge, called current collapse in English, is illustrated in FIG. 4.
- the buffer layer of the GaN transistor is doped P uniformly at a value of 5. 10 17 atoms / cm 3 .
- a second solution is to provide a composite buffer GaN / Al vering x x N for example, as illustrated in Figure 5, with the GaN channel.
- the negative piezoelectric charge occurring at the 50 GaN / Al x GaI interface. x N creates a potential barrier for confining the electrons in the channel.
- a few percent of aluminum in the Al 2 O 3 N layer, typically 3% to 10%, is required to obtain good electron confinement for a maximum operating voltage of 20V to 40V and a gate length of less than 20%. 0.25 ⁇ .
- the thermal conductivity of Al x Ga 1-x N is less than that of GaN by a factor of between 3 and 5 for the aluminum levels necessary for good electron confinement.
- the thermal resistance of the transistor is thus strongly degraded, multiplied by 2 to 3, and the power that can be emitted reduced by a factor of 1.5 to 3 depending on the applications targeted with this solution.
- a third solution consists in introducing into the buffer layer 12 the fixed negative electric charge which is just necessary to obtain good transfer characteristics at the desired operating voltages and frequencies.
- the control of the quantity of charges and their position in relation to the 9 electron gas provides a good confinement of electrons in the channel without creating undesirable trapping phenomena that lead to a degradation of linearity or, in other words, dispersive effects and a decrease in available power and yield, without degrading the thermal conductivity of the "buffer" for example in GaN.
- FIG. 6 illustrates a stack 10 for a high electron mobility field effect transistor (HEMT) according to this third solution of the prior art.
- the stack 10 is made from a conventional substrate 11 for this type of component.
- the stack 10 comprises a plurality of layers in a plane xy perpendicular to a z axis.
- the stack 10 comprises a buffer layer 12 comprising a first so-called "large gap” semiconductor material such as AIGaN, and more specifically, Al x Ga 1-x N, with x typically between 0 and 35. %.
- the buffer layer 12 of the stack comprises a zone Vf comprising fixed negative charges located at a specific location of the buffer layer 12.
- Non-mobile charges are non-mobile charges (mobile charges in this context mean electrons or holes), the term mobile being understood in the usual sense in the field of semiconductor physics.
- the area Vf extending along the xy plane is located at a distance d from the heterojunction and has a thickness t.
- Figure 7 describes, more precisely, the distribution and nature of the charges in the stack.
- the fixed character of a load is symbolized by a rectangular-shaped acronym surrounding this load, while the moving character is symbolized by an oval-shaped acronym.
- a surface density ⁇ + of fixed positive charges 71 is present in the vicinity of the heterojunction 15, and mobile negative charges em also located in the vicinity of the heterojunction 15 constitute the bidimensional electron gas 9 at the origin of the operation of the HEMT transistor.
- the surface density of electrons em in the channel is typically about 0.5x10 13 to 3x10 13 cm- 2 .
- the fixed negative electrical charges 70 located in the buffer layer 12 are obtained from acceptor-type impurities introduced into the buffer layer 12, such as carbon, iron, magnesium atoms or any type of known impurities. to be an accepting center in GaN or AIGaN.
- An object of the invention is in particular to propose a transistor intended for fast switching applications (envelope modulation), amplification of microwave power signal having good thermal conductivity and whose configuration of the buffer layer is independent of Terms of use.
- a field effect transistor comprising a stack along an axis z comprising:
- barrier layer comprising a first semiconductor material
- the buffer layer comprising a second semiconductor material comprising a binary or ternary or quaternary nitride compound
- the stack further comprises a first sub-layer separating the two-part buffer layer and comprising a third material comprising a binary or ternary or quaternary nitride compound, such that the difference in spontaneous and piezoelectric polarization coefficients between the second material and the third material induced at a first interface between the first portion of the buffer layer and the first underlayer, a first surface-fixed electrical charge generating an electric field directed along the z-axis and oriented towards the first interface so as to allow the confinement of the gas two-dimensional in the channel, the distance between the heterojunction and the first interface between the first portion of the buffer layer and the first sub-layer being between one third of the length of the grid in the direction Ox perpendicular to the direction of the stack Oz of the transistor and two gate lengths, the thickness of the first sub-layer along the z axis being less than a threshold value.
- the two-dimensional gas is an electron gas, the fixed surface electrical charge induced at the first interface between the first portion of the buffer layer and the first sub-layer being negative, thus generating an electric field oriented towards the first underlayer. which confines the electrons in the channel.
- the first sub-layer comprises Al x 1 Ga (1 x 1 ) N, being greater than x + 15%, x being the aluminum content of the buffer layer and Xi being the aluminum content of this first sub-layer. -layer.
- the buffer layer further comprises a second sublayer located between the first sublayer and the second portion of the buffer layer, the second sublayer comprising rAl x 2 Ga (1 ⁇ 2 ) N, and x 2 being less than or equal to x + 15% and greater than or equal to x, where x is the aluminum from the buffer and x 2 layer content being the aluminum content of the second sub-layer, with excess negative fixed electric charges in a second interface from the heterojunction between the first and the second sub-layer, a second positive surface and fixed electrical charge, in absolute value, to the first surface-fixed electrical charge of the first interface.
- the thickness of the second sublayer in the direction of the stack is greater than or equal to 100 nm.
- the second sub-layer of AIGaN has an aluminum concentration gradient increasing in the direction of the stack and oriented towards the heterojunction, the concentration of aluminum x 2 at the interface between the sub-layers 19 and 12b being between x and x + 15%.
- the association of a second sub-layer comprising AIGaN makes it possible in particular to avoid the formation of an electron gas in the vicinity of the second interface between the first sublayer and the second portion of the buffer layer.
- the second sub-layer further comprises acceptor-type impurities so as to compensate for the N-type doping induced by the aluminum concentration gradient of the second sub-layer.
- the acceptor-type impurities introduced into the second sublayer are carbon or iron, beryllium or magnesium or beryllium or any type of impurity known to be an accepting center in GaN or AIGaN.
- An appropriate location of a thin layer of material generating a negatively charged interface, or in other words, the sum of the surrounding charges is negative, allows the confinement of mobile negative electric charges in the channel of the transistor.
- FIG. 1 already cited schematically represents a section of the structure of a conventional HEMT transistor
- FIG. 2 already cited represents the distribution of the charges in the vicinity of the heterojunction of the conventional HEMT transistor
- FIG. 3 already quoted represents schematically the characteristic current / voltage curves of a HEMT transistor having a good and a bad "pinch"
- FIG. 4 already mentioned, schematically illustrates the behavior of an HEMT transistor, according to the known art, having a dispersion in current
- FIG. 5 already cited schematically illustrates a stack of a transistor, according to the known art, having a composite buffer layer
- FIG. 6, already mentioned illustrates a stack for a field effect transistor according to a prior art
- FIG. 7 already mentioned describes more precisely the structure of the charges in the stack according to a prior art
- FIG. 8 represents the charge distribution within a GaN crystal
- FIG. 9 illustrates two wurtzite crystalline structures of GaN
- FIG. 10 illustrates a transistor, according to one aspect of the invention
- FIG. 11 represents a transistor according to another aspect of the invention
- FIG. 12 illustrates an example of a profile of the percentage of aluminum in the AIGaN of the stack, according to the invention.
- Three variants of the aluminum concentration profile of the layer 19 are represented (the concentration of aluminum at the interface between the sub-layers 16 and 19 being greater than or equal to the concentration of aluminum at the interface between the underlays 19 and 12b),
- the principle of the invention consists in the confinement of mobile charges circulating in the channel based on the intrinsic properties of the materials of the stack and not on the addition of fixed charges (in the form of impurities) depending on the conditions of the use of the transistor.
- the effects of polarization appear when the atoms of a crystal form dipoles which orient themselves partially or completely under the action of an electric field or not.
- the polarization charges result from two mechanisms: spontaneous polarization and piezoelectric polarization.
- the spontaneous polarization results from the differences of electronegativity of the different atoms in contact and the piezoelectric polarization results from the mechanical stresses.
- spontaneous polarization is meant the polarization of a molecule, not subjected to an electric field, based on the differences of electronegativity of the atoms that make up the molecule.
- the invention is based on the exploitation of these 2 polarizations (spontaneous and piezoelectric) which are specific to this family of materials (family of III-N: association of elements of column III of Mendeleyev's table and nitrogen eg BN, GaN, AlN, InN, for binary compounds, AIGaN, InAIN, InGaN, BGaN for ternary compounds, InGaAIN for quaternary compounds for example).
- Figure 8 illustrates the charge distribution within a GaN crystal.
- gallium atoms are less electronegative than those of nitrogen, respectively 1, 6 eV and 3 eV, the electrons of the covalent bonds between these atoms have a greater probability of being closer to the nitrogen atoms. Thus, the negative charge appears around these atoms and a positive charge around the gallium atoms.
- the final distribution of the charges within a crystal results from the summation of the different contributions P1, P2, P3, P4.
- the resultant of the polarizations ⁇ , ⁇ P3, P noted P ⁇ r, is opposed to Pl. Calculations have shown that the contribution of PI is greater than the resulting contribution Pr, and thus the final spontaneous polarization, is in the same direction and sense as ⁇ T.
- a positive charge is on the surface and a negative charge of the same size is formed on the substrate side.
- the charge distribution is reversed in the case of a wurtzite face-Ga structure, as shown in Figure 9.
- the electronegativity of the aluminum atoms being lower than that of the nitrogen atoms, the direction and direction of the electric field resulting from the spontaneous polarization are identical in the AIGaN layer and in the GaN layer.
- FIG. 10 represents a transistor comprising a stack, according to one aspect of the invention.
- the stack 10 comprises a substrate 11, it also comprises a barrier layer 13 comprising a first semiconductor material comprising a binary compound, such as AIN, or ternary such as AIGaN or ⁇ , and more specifically, Al x G1- x N or Nn y AI 1-y N with x typically between 15% and 35%, or quaternary of BAIGaN nitride or InGaAIN.
- AIN binary compound
- ternary such as AIGaN or ⁇
- the stack 10 has a heterojunction 15 between the buffer layer 12 and the barrier layer 13 and a two-dimensional electron gas 9 located in an xy plane perpendicular to the z axis and in the vicinity of the heterojunction 15, according to the conventional structure of a stack for HEMT transistor.
- the buffer layer 12 further comprises a first sublayer 16, separating the buffer layer 12 into two parts 12a and 12b.
- the first sub-layer 16 is located at a distance of between one third of the length of the grid Lg and twice the length of the grid Lg.
- the thickness of the first portion 12a of the buffer layer 12a is between one third of the length of the gate Lg and twice the length of the gate Lg of the transistor.
- the buffer layer 12 comprises gall-GaN nitride Ga-face and the first sublayer 16 comprises TA ⁇ Ga ⁇ N, the x1 content of aluminum being greater than x + 15%, the thickness t of the first sub-layer 16 in the direction of the stack 10 being less than 20 nm.
- Other materials could be considered.
- gallium-indium nitride InGaN is not a good candidate. Indeed, it is difficult to grow InGaN comprising more than a few percent of indium with a satisfactory crystalline quality.
- the growth of InGaN is carried out at a temperature which is 200 ° C lower than that required for the growth of GaN. Also, it is difficult subsequently to grow on a layer of InGaN a compound such as GaN with good crystalline quality without degrading the quality of the InGaN layer.
- This solution makes it possible in particular to limit the thermal degradation of the transistor to a value of less than 2 ° C / mm / W and does not generate a frequency dispersion of the transconductance (due to the use in the state of the prior art of centers deep to introduce negative charges into the buffer layer 12).
- the two-dimensional gas 9 of electrons is then confined in the channel, the mobile charges do not spread inside the first part of the buffer layer 12a.
- channel By channel is meant a layer having a thickness of less than about 10 nm located on the surface of the buffer layer 12 in the vicinity of the heterojunction 15.
- the small thickness of Al x 1 Ga 1-x 1 N of the first sub-layer 16 limits the increase of the thermal resistance of the transistor to a value of less than 2 ° C / mm / W.
- FIG. 11 illustrates this aspect of the invention.
- the stack 10 comprises, as in FIG. 10, a buffer layer 12 separated in two parts 12a and 12b by a first sub-layer 16.
- the stack 10 further comprises a second sub-layer 19 comprising rAl x2 G1- x2 N, the aluminum content x 2 being less than x + 15%.
- FIG. 12 illustrates profiles P1, P2 and P3 of aluminum concentration of the stack.
- the first sub-layer 16 of small thickness, typically less than 20 nm, comprises a high aluminum content so as to improve the confinement of the electrons in the channel in the vicinity of the heterojunction 15.
- the Aluminum content on profile P1 has a decreasing linear gradient, the aluminum content being between x + 0 and x + 15%.
- the P2 and P3 profiles show other decreasing changes in the aluminum content on the second sub-layer 19.
- the impurities introduced into the second sub-layer 19 are iron or carbon or magnesium or beryllium or any atom known to be an accepting center in GaN or AIGaN.
- the impurity concentration introduced is greater than or equal to the doping induced by this concentration gradient. This concentration must be greater than or equal to the sum of the spontaneous and piezoelectric charges induced by the concentration gradient, divided by the thickness of the AIGaN layer 19.
- the first sublayer 16 is located 100 nm from the heterojunction 15 and has a thickness t1 of 5 nm.
- each of the characteristics 61, 62, 63 and 64 corresponds to a transistor whose first sub-layer 16 has different aluminum contents, respectively 25, 30, 35 and 40%.
- the inverse of the slope below the SS threshold of each of the characteristics is of the order of 70mV per decade, close to its ideal value (60mV / decade at ambient temperature). This value of 70mV / decade is maintained over five decades of current when the aluminum content is 40% which makes it possible to have a leakage current of less than ⁇ / mm and is of real interest for applications for which the consumption electric is an important criterion.
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Abstract
Description
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR1502296A FR3043251B1 (fr) | 2015-10-30 | 2015-10-30 | Transistor a effet de champ a rendement et gain optimise |
PCT/EP2016/075971 WO2017072249A1 (fr) | 2015-10-30 | 2016-10-27 | Transistor a effet de champ a rendement et gain optimise |
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EP3369115A1 true EP3369115A1 (fr) | 2018-09-05 |
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EP16790546.2A Withdrawn EP3369115A1 (fr) | 2015-10-30 | 2016-10-27 | Transistor a effet de champ a rendement et gain optimise |
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US (1) | US20180308966A1 (fr) |
EP (1) | EP3369115A1 (fr) |
JP (1) | JP2018536285A (fr) |
CN (1) | CN108475696A (fr) |
FR (1) | FR3043251B1 (fr) |
WO (1) | WO2017072249A1 (fr) |
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CN109742072B (zh) * | 2019-01-04 | 2019-08-16 | 苏州汉骅半导体有限公司 | 集成增强型和耗尽型的hemt及其制造方法 |
US11101378B2 (en) | 2019-04-09 | 2021-08-24 | Raytheon Company | Semiconductor structure having both enhancement mode group III-N high electron mobility transistors and depletion mode group III-N high electron mobility transistors |
FR3098810B1 (fr) * | 2019-07-18 | 2021-10-15 | Commissariat Energie Atomique | Liaison mécanique pour dispositif MEMS et NEMS de mesure d'une variation de pression et dispositif comprenant une telle liaison mécanique |
US11545566B2 (en) * | 2019-12-26 | 2023-01-03 | Raytheon Company | Gallium nitride high electron mobility transistors (HEMTs) having reduced current collapse and power added efficiency enhancement |
US11362190B2 (en) | 2020-05-22 | 2022-06-14 | Raytheon Company | Depletion mode high electron mobility field effect transistor (HEMT) semiconductor device having beryllium doped Schottky contact layers |
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US6624452B2 (en) * | 2000-07-28 | 2003-09-23 | The Regents Of The University Of California | Gallium nitride-based HFET and a method for fabricating a gallium nitride-based HFET |
JP2005086102A (ja) * | 2003-09-10 | 2005-03-31 | Univ Nagoya | 電界効果トランジスタ、及び電界効果トランジスタの作製方法 |
JP5334149B2 (ja) * | 2006-06-02 | 2013-11-06 | 独立行政法人産業技術総合研究所 | 窒化物半導体電界効果トランジスタ |
JP5130846B2 (ja) * | 2006-10-30 | 2013-01-30 | 株式会社デンソー | 熱伝導性絶縁材料及びその製造方法 |
JP5487631B2 (ja) * | 2009-02-04 | 2014-05-07 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
JP2010238752A (ja) * | 2009-03-30 | 2010-10-21 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP5670427B2 (ja) * | 2009-04-08 | 2015-02-18 | エフィシエント パワー コンヴァーション コーポレーション | GaNバッファ層におけるドーパント拡散変調 |
US8742459B2 (en) * | 2009-05-14 | 2014-06-03 | Transphorm Inc. | High voltage III-nitride semiconductor devices |
JP5624940B2 (ja) * | 2011-05-17 | 2014-11-12 | 古河電気工業株式会社 | 半導体素子及びその製造方法 |
CN102646700B (zh) * | 2012-05-07 | 2015-01-28 | 中国电子科技集团公司第五十五研究所 | 复合缓冲层的氮化物高电子迁移率晶体管外延结构 |
CN102969341A (zh) * | 2012-11-09 | 2013-03-13 | 中国电子科技集团公司第五十五研究所 | 组分渐变AlyGa1-yN缓冲层的氮化物高电子迁移率晶体管外延结构 |
US9553183B2 (en) * | 2013-06-19 | 2017-01-24 | Infineon Technologies Austria Ag | Gate stack for normally-off compound semiconductor transistor |
KR20150085724A (ko) * | 2014-01-16 | 2015-07-24 | 엘지전자 주식회사 | 질화물 반도체 소자 및 그 제조 방법 |
US9960262B2 (en) * | 2016-02-25 | 2018-05-01 | Raytheon Company | Group III—nitride double-heterojunction field effect transistor |
-
2015
- 2015-10-30 FR FR1502296A patent/FR3043251B1/fr active Active
-
2016
- 2016-10-27 US US15/769,708 patent/US20180308966A1/en not_active Abandoned
- 2016-10-27 EP EP16790546.2A patent/EP3369115A1/fr not_active Withdrawn
- 2016-10-27 CN CN201680077236.2A patent/CN108475696A/zh active Pending
- 2016-10-27 JP JP2018522143A patent/JP2018536285A/ja active Pending
- 2016-10-27 WO PCT/EP2016/075971 patent/WO2017072249A1/fr active Application Filing
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US20180308966A1 (en) | 2018-10-25 |
FR3043251A1 (fr) | 2017-05-05 |
WO2017072249A1 (fr) | 2017-05-04 |
JP2018536285A (ja) | 2018-12-06 |
FR3043251B1 (fr) | 2022-11-11 |
CN108475696A (zh) | 2018-08-31 |
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