EP3229221B1 - Vorrichtung und verfahren zum testen einer physisch unklonbaren funktion - Google Patents
Vorrichtung und verfahren zum testen einer physisch unklonbaren funktion Download PDFInfo
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- EP3229221B1 EP3229221B1 EP16305419.0A EP16305419A EP3229221B1 EP 3229221 B1 EP3229221 B1 EP 3229221B1 EP 16305419 A EP16305419 A EP 16305419A EP 3229221 B1 EP3229221 B1 EP 3229221B1
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/577—Assessing vulnerabilities and evaluating computer system security
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
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Definitions
- the invention generally relates to the field of data and device securing, and in particular to methods and devices for testing a physical Unclonable function implemented in a device.
- Integrated circuits generally contain secret data such as security keys and secret functions.
- secret data such as security keys and secret functions.
- different types of attacks can be implemented against integrated circuits from the outside to try to access such data, such as side-channel attacks, electro-migration (such as power consumption, electromagnetic emissions, operations duration, etc.), imaging, fault injection, etc.
- PUFs Physical unclonable Functions
- a PUF is a physical entity which is embodied in a physical structure which is the same in each physical instantiation of the physical entity and which generates a specific output when provided with an input.
- the value of the specific output is specific to each instantiation of the physical entity embodied within a device.
- a PUF thus also ensures that the PUF value knowledge of one device does not jeopardize all fabricated devices.
- a PUF takes advantage of the variance of conditions in the manufacturing process of many identical devices.
- a PUF can be incorporated in a CMOS integrated circuit. To some extent, a PUF may be considered as the analog of a fingerprint of the device.
- a PUF can be used in various contexts (e.g. authentication of chips or goods it is attached to, generation of cryptographic keys or seeds of PRNG, etc).
- the physical structure that contains the PUF consists of at least one random component.
- the output of PUF for a given input is obtained by submitting the input to the physical system in the form of a stimulus, and mapping the behavior that occurs as a result of an interaction between the stimulus and the physical system to an output.
- a PUF reflects the condition changes in the manufacturing process of otherwise identical structures.
- Conventional PUFs include "silicon PUFs" which are fabricated in the same material and through the same process as electronic circuits. This allows embedding PUFs very close to parts of the circuit which process and transmit information. Silicon PUFs are located very close to the cryptographic modules and are thus difficult to tamper with.
- Some PUFs known as "strong" PUFs, have an input and reply differently for each input.
- Most silicon PUFs are well suited to be strong, since it can have the necessary logic to present the input to the PUF as it awaits it.
- An input that a strong PUF accepts is generally referred to as a "challenge” or challenge signal.
- a challenge is represented by a vector of bits.
- the output of a PUF is generally referred to as a “response” or “response signal”.
- a PUF is thus a physical function which maps a digital "Challenge” to a digital "Response”.
- a response to a given reference challenge is also referred to as an "identifier”.
- a pair comprising a challenge and the corresponding response of a PUF is referred to as a challenge-response pair.
- a PUF thus implements a set of challenge-response pairs (CRPs) such that separate logically-identical devices produce different CRPs, unpredictable even to the designer.
- CRPs challenge-response pairs
- a challenge-response pair CRP is coupled to a unique physical device (hence, the "unclonable" property of a PUF).
- PUF functions allow identification of objects using their intrinsic physical properties.
- a PUF determines an associated response value for a predefined challenge value on the basis of the physical properties of the object.
- To authenticate an object i.e. identify the object as the original object, one approach consists in comparing the similarity of the available response values for given challenges, if challenge-response pairs CRPs are known, and the response values provided by the object to be authenticated for these challenges.
- PUFs can be also used for on-chip determination of a cryptographic key, or for generating a unique identifier such as a cryptographic key for cryptographic purposes.
- the quality of a PUF device may be related to a number of properties or metrics such as:
- the second type of test is of major importance because:
- An “Online” test refers to a test carried out in the field, on the final product using the PUF.
- An “Embedded” test refers to a test that is computable on the PUF without external connection (which would otherwise be considered a "backdoor”).
- a PUF is implemented from a unique model and should be manufactured such as every instance of a PUF is different after fabrication.
- Each instance of a PUF features a behavior which is very little correlated with the other instances of the PUF belonging to a same batch.
- a small correlation can exist for PUFs which are fabricated close one to each other, but the correlation decreases with the distance. This is due to the working factor of PUFs. Indeed, PUFs rely on small technological variations between instances, which are responsible for the unique behavior of each instance.
- the typical distance of correlation is of the order of a few microns at most and the typical size of a PUF instance is rather of the order of several microns, even in very deep submicron CMOS processes.
- Embodiments of the invention allows for testing uniqueness and randomness of a PUF without a need to test all the PUF instances of the PUF batch from which the PUF originates.
- PUF instance also referred to as a PUF "instantiation”
- the PUF instance belonging to a given batch of PUFs, which obviates the need for testing the other PUF instances of the batch.
- Figure 1 represents a system 100 for testing the uniqueness of a PUF instance 10.
- the PUF instance is embedded in a device 12, such as an integrated circuit.
- the system 100 comprises a testing device 11 for testing the uniqueness of the PUF instance belonging to a PUF batch 20 comprising a set of PUF instances, without a need to access all the PUF instances of the batch.
- the device 12 may comprise one or more PUF instances, including other PUF instances belonging to the same batch 20 as the PUF instance being tested.
- the other PUF instances embedded in the device 12 and belonging to the same batch will be referred to hereinafter as "neighboring" PUF instances.
- Each PUF instance 10 to be tested by the testing system 100 is configured to produce a measurable output when queried with a certain input. It should be noted that a PUF as such is not a "function" in the mathematical sense. Indeed, an input to a PUF may have more than one possible output. However, the number of possible answers to a given challenge is limited and is desirably equal to only one for a PUF of fair enough reliability. A PUF rather designates a process performed by or acting upon a particular (physical) system.
- An input applied to the PUF 10 is referred to as a "challenge”.
- the output produced by the PUF 10 is referred to as "a response”.
- the pair formed by an applied challenge and the corresponding measured response is referred to as a challenge-response pair or "CRP”.
- CRP challenge-response pair
- the relation between challenges and responses generated by a particular PUF 10 is referred to as the CRP behavior of the PUF.
- the PUF 10 may be operated according to two phases:
- the challenges applied to the PUF 10 and the responses obtained as the result of the application of the challenge may comprise bit strings.
- decoding and quantization steps may be applied to apply analog physical stimuli as challenges and derive the response from measures of the analog effects thus obtained.
- a same challenge applied to the PUF 10 does not necessarily produce the same response, giving rise to an intra-distance between the PUF responses. This may result from random noise, environmental factors (e.g. temperature or supply voltage in case of a PUF on an integrated circuit).
- a delay PUF is a PUF that accepts many challenges. For example, in a delay PUF, the delay is controlled by the challenge bits thus providing a huge number of challenge combinations.
- delay PUFs comprise PUFs such as Arbiter PUFs RO-PUFs or Loop PUF.
- a memory PUF is associated with a limited number of different challenges.
- a memory PUF can be a SRAM PUF.
- the memory addresses can be used as challenges.
- the invention may also be applied to a so-called “composite” PUF or a combination of several memory PUFs.
- the PUF 10 may belong to the category of "weak” PUFs or "strong” PUFs.
- a "weak” PUFs possesses some internal, unclonable physical disorder, and possess some form of challenge-response mechanism that exploits this disorder.
- a Weak PUF has got very few, fixed challenges, and in certain cases only one challenge per PUF instance.
- the challenge-response interface (or the challenge-response mechanism, respectively) of a Weak PUF may be be access-restricted.
- Adversaries cannot access to the Weak PUF's responses, even if they hold physical possession of the PUF-carrying hardware.
- Weak PUFs can be implemented either using special purpose integrated circuits designed to be sensitive to variation, or by using the intrinsic variation present in all existing circuits.
- SRAM PUFs are example of weak PUFs exploiting the inherent threshold variation of the cross-coupled inversors making up the SRAM cells.
- a "strong” PUF derives a more complex challenge-response behavior from the physical disorder present in the PUF.
- a strong PUF comprises many elements (physical components) involved in the generation of a response, and there is a very large number of possible challlenges that can be applied to the PUF.
- a strong PUF has the following features:
- a "weak PUF” (e.g., SRAM-PUF, butterfly PUF, etc) represents a collection of elements, which can be each addressed individually.
- the challenge of a weak PUF thus represents the address of the memory point, and the response is the contents of the memory point at powerup.
- a “strong PUF” is also made up of several elements, which are nonetheless not meant to be accessed independently. Indeed, the strong PUF is unique via an aggregated behavior of its elements, such as the total delay difference.
- the PUF 10 is based on an internal structure which is different depending on the type of PUF and which reacts to the challenges to produce a response.
- the internal structure of the PUF may comprise repeated patterns (referred to hereinafter as "PUF elements") each pattern including a set of physical components.
- FIG. 2 is a block diagram of the testing system 100 according to certain embodiments.
- the testing device 11 may be arranged adjacent to the device 12 embedding the PUF.
- the testing device may be implemented in a distant server connected to the device 12 embedding the PUF instance through a computer network, the server being configured to receive requests for testing PUF instances from one or more client devices.
- the internal structure of the PUF instance 10 to be tested may be a circuitry comprising a set of PUF elements that contribute to a PUF response to application of at least one bit of a challenge to the PUF.
- the PUF elements satisfy a predefined pattern (same pattern for all the PUF elements), each PUF element comprising a set of physical components defined by the pattern.
- the assembly of the PUF elements in the PUF instance may differ. For example:
- Each challenge applied to the PUF 10 comprises a set of bits (or "string of bits").
- Each PUF element is controlled by at least one input bit represented by a bit of the challenge being applied to the PUF.
- the PUF elements of a PUF instance are configured to perform a same function in response to such inputs being applied to the PUF elements.
- the number of PUF elements is equal to the number of bits comprised in the challenge (in other words, a bit position in the challenge is associated with a PUF element, the bit at this bit position being input to the PUF element as a control bit).
- the PUF testing device 11 may comprise:
- a conversion unit 111 may be further used to render the identifiers acquired from the PUF elements of the PUF instance reliable.
- the randomness test application unit 112 may further take into account other identifiers acquired from neighboring PUF instances 13 within the group of identifiers.
- the uniqueness of the PUF instance may be assessed from said PUF uniqueness indicator.
- the inventors have found out that it is possible to efficiently test the randomness and uniqueness properties of a PUF instance 10 belonging to a PUF batch 20 comprising a set of PUF instances by testing the PUF elements comprised in each PUF instance 10.
- the embodiments of the present invention exploits the fact that PUF elements are likely to be more correlated than two distinct PUF instances due to the spatial distance (inter-distance) introduced during the PUF manufacturing process.
- the PUF might not be unique due to “correlations" between PUF instances. Those correlations can be due to at least:
- the first kind of correlation (due to architectural bias) generally exists whichever the fabrication place and time.
- the second kind of correlation (due to transistor characteristic dispersion) is reduced with space.
- Two neighboring elements are more correlated than two chips on the same wafer, which are themselves more correlated than two chips on two different wafers. Therefore, by considering a PUF instance 10 as a batch of "elementary 1-bit PUFs", it has been found out that the local measure of uniqueness and randomness as achieved by the invention reveals the architecture bias, if any, and a worst case estimation of the correlation due to small technological dispersion. It should be noted that even if the estimation of uniqueness and randomness within one PUF is a pessimistic estimation, it provides a conservative estimation that warranties the uniqueness and randomness of the PUF.
- FIG. 3 is a flowchart depicting the testing method implemented by the testing device 11.
- the testing method enables testing uniqueness and randomness of a PUF instance 10 belonging to a PUF batch 20, without a need to access to the other PUF instances of the batch.
- identifiers of the PUF elements of the PUF instance 10 may be determined from the output of each PUF element in response to the application of one or more bits of at least one challenge.
- the identifiers of the PUF elements 100 of the PUF instance 10 may be determined from the elementary responses generated at each PUF element output in response to one or more challenges applied to the PUF instance 10.
- Step 300 may be implemented in different ways depending on the PUF type.
- the uniqueness of the PUF elements may be assessed by applying a statistical randomness test to a group of identifiers comprising the identifiers of PUF elements acquired in step 300.
- the statistical randomness test may be chosen in a group consisting of an entropy test and a Maurer universal statistical test.
- Such statistical randomness tests may be configured to detect a wide gamut of statistical defects within a distribution.
- Values of L, Q, K may be chosen as described in U. M. Maurer, « A Universal Statistical Test for Random Bit Generators",Journal of Cryptology. Vol. 5, No. 2, 1992, pp. 89-105 .: we can quote the paper ".
- the test parameters L, Q and K may be advantageously chosen as follows:
- a PUF uniqueness indicator may be returned as a result of the statistical test applied in step 304.
- the PUF uniqueness indicator may be a bit value which may take a first value or a second value.
- the PUF uniqueness indicator may be assigned a first value (for example "0") in step 307, if the test of block 306 failed, i.e. at least one identifier among the identifiers acquired from the PUF elements is redundant (redundancy detected). Otherwise, the PUF uniqueness indicator may be assigned a second value (for example "1") in step 308, if the test of block 306 succeeded, i.e. no redundancy has been detected among the identifiers acquired from the PUF elements (the identifiers acquired in step 300 are thus considered as unique within the considered group of identifiers).
- the PUF uniqueness indicator indicates that a redundancy has been detected within the PUF element identifiers comprised in the group of PUF elements (PUF uniqueness indicator assigned to the first value)
- the worst situation is detected as regards the entropy of PUF, which means that the PUF is dubious.
- the testing method may trigger an action in response to the PUF uniqueness indicator being assigned the first value (redundancy detected).
- Such action may be chosen in a group consisting of a revocation of said PUF, a disablement of said PUF, an emission of a notification, or an emission of an alert message.
- the device 12 carrying the PUF may be thus able to report to an administrator system that a security event occurs. Such information may be used by the administrator system or a network operator to decide which "counter-action" is to be taken. For instance, the devices in the vicinity of the compromised PUF can be disabled or have their security awareness level increased.
- the testing method may comprise a further step 301 of detecting errors generated during the step of acquiring the identifiers of said PUF elements and correcting the errors. This ensures the reliability of the acquired identifiers. Reliability can be assessed by repeatedly measuring identifiers under the same challenge, and checking that they are the same most of the time.
- the testing method may further comprise a step 303 of acquiring the identifiers of the PUF elements of neighboring PUFs, that is PUFs which are located in the vicinity of said PUF in the same device or a neighboring device. Such PUF element identifiers are then added to the group of PUF identifiers on which the statistical randomness test is applied in step 304.
- Step 300 of acquiring the identifiers of the PUF elements may be implemented in different ways depending on the type of the PUF.
- auxiliary components such as hardware components may be used in the PUF instance to determine the elementary response of each PU element in response to a challenge applied to the PUF instance.
- the auxiliary components may be reading components for reading the output (elementary response) of each PUF element in response to an applied challenge.
- Step 300 of acquiring the identifiers of the elements of the PUF instance 10 may then be implemented by reading the identifier of each PUF element of the PUF according to a given access mode (also referred as reading mode).
- the reading mode may be selected in a group consisting of a sequential mode for sequentially reading the identifiers and a parallel access mode for reading in parallel the identifiers.
- the auxiliary components used to read the PUF outputs may be arbiters configured to bypass all pairs of delay element.
- the auxiliary components may be read components originally implemented in the PUF to read the outputs of the PUF elements in order to form the PUF response to the challenge.
- such auxiliary components may be inserted within the PUF instance at the time of manufacturing the PUF instance, even if such read elements are not required for the operation of the PUF as such.
- the auxiliary components will be used to read the elementary response of each PUF element in order to determine the identifier of the PUF element from the read output.
- a temporal access may be used for requesting the PUF with a first challenge, the "digital response" being equal to the comparison between the first challenge and a second challenge at a distance 1 of the first challenge.
- Such temporal access may be available in some strong PUFs such as a loop-PUF (LPUF) for example.
- LPUF loop-PUF
- Figure 4 is a flowchart illustrating the step of acquiring the PUF elements of the PUF (step 301), using auxiliary components for determining the PUF element identifiers using temporal access, according to certain embodiments.
- the step of acquiring the identifiers of the PUF elements of a strong PUF 10 may comprise, for each PUF element:
- the number of iterations may be predefined or selected. The number of iterations may depend on the entropy of the PUF element identifier. Indeed, the size of the identifier (in bits) bounds its entropy. For example, for cryptographic applications, a size of 128 bits (symmetric cryptography) or 256 bits (asymmetric cryptography on elliptic curves) may be typically required.
- the challenge may comprise a set of bits while the bit response at the output of each PUF element is a one-bit response.
- the identifier of a given PUF element may be determined in step 404 by aggregating the bit responses iteratively read at the PUF element output, as a result of the different challenges applied.
- the bit response read at the output of each PUF element is a one-bit response
- the number of bits forming the identifier may be equal to the number of iterations.
- an identifier for each PUF element may be generated from the bit responses obtained at the output of each PUF element by applying iteratively a number of challenge values to the PUF.
- bit responses of one or more PUF elements may be determined in parallel for each applied challenge to generate in parallel the identifiers of the PUF elements.
- the bit responses of one or more PUF elements may be determined sequentially.
- the bit responses of the PUF elements comprised in the PUF instance 10 may be stored in a same data structure indexed by a first index representing the index of the PUF element and a second index representing the index of the challenge applied.
- a different data structure may be used to store the bit responses of each PUF element for the different challenges applied to the PUF instance 10.
- each PUF instance 10 may be further controlled by a test mode input which may receive a first value to activate the test of the PUF and a second value to activate the functional operation of the PUF.
- the test mode input may be shared by each PUF element of the PUF.
- Figure 5 illustrates an exemplary application of the invention to an arbiter PUF 10, according to certain embodiments.
- An Arbiter PUF 10 extracts the device-specific variation as delay differential between two logic paths 101 and 102.
- the arbiter PUF 10 comprises chain of PUF elements 50-j which are delay elements defining the two logic paths and a main arbiter unit 104 (also referred to hereinafter as "arbiter” or “main arbiter”).
- the arbiter 104 may be implemented for example as a latch or a flip-flop having a D port and a clock port.
- the arbiter PUF 10 has a multiple bit input on which is applied one or more challenges C 1 ... C i ... C n and compute a one-bit output Y based on the relative delay difference between the two paths 101 and 102.
- the delays of the two logic paths 101 and 102 are affected by the intrinsic device-specific variation, and therefore the Arbiter PUF 10 is expected to output unique identifiers to the device 12 on which it is implemented.
- the input bits determine the delay of the paths by controlling the PUF elements 50-j, each PUF element comprising a pair of multiplexer-based components.
- Stimuli are simultaneously input to the upper and lower logic path 101 and 102 and the challenge is input as a selection signal to the arbiter PUF 10.
- the stimuli travel through a set of PUF elements 50-j in the paths 101, 102 according to the input challenge defined by the sequence of bits C 1 ... C i ... C n , the PUF elements 50 having the same pattern.
- Each PUF element 50-j of the arbiter-PUF is controlled by a bit C i of the challenge applied to the PUF 10.
- FIG. 6 represents a PUF element of an arbiter-PUF according to certain embodiments.
- each PUF elements C i comprise an upper component d ( C i ) arranged in the upper path 101 and a lower d ( C ' i ) arranged in the lower path 102, the upper and lower components being chained by pairs:
- each PUF element 50-j may comprise switching unit 52 such as multiplexers or selectors controlled by the same input C i corresponding to the i - th bit of the challenge.
- switching unit 52 such as multiplexers or selectors controlled by the same input C i corresponding to the i - th bit of the challenge.
- the following description will be made with reference to switching units implemented as multiplexers for illustrative purpose only. Accordingly, for each i - th PUF element 50-j, the outputs ( y i , y' i ) are connected to inputs ( x i, x' i ) .
- each PUF element 50-j may further comprise buffers 51.
- Each PUF element works a switching unit controlled by the input C i . If the input control bit C i is zero, one of the inputs of the multiplexer 52 of each component d ( C i ) or d '( C i ), such as the 0-input, may be selected: the two delay signals then pass through the zero entry. Otherwise, the other input of the multiplexers 52 is selected such that the top and bottom signals are switched.
- the arbiter unit 104 determines which signal is faster at the end of the path. If the fastest signal between the output of the upper component d ( C i ) and the output of the lower component d ( C' i ) is y n , the arbiter unit 104 (which receives the signals y' n and y n as inputs) may deliver 1 : the PUF 10 then outputs a response equal to 1. Otherwise, if y' n is the fastest signal, the arbiter unit 104 may deliver a response equal to 0 : the PUF then outputs a response 0.
- the PUF-arbiter 10 may comprise at least one auxiliary component 105 arranged upstream each component d ( C i ) and d ( C' i ).
- the auxiliary component 105 may be configured to select one input among the main input x i of the component (respectively x ' i for the lower component) and an auxiliary input test_in i (respectively test_in' i for the lower component) depending on a control input test_mode.
- An auxiliary output test_out i (respectively test_out' i for the lower component) may be connected at the output of each paired-component d ( C i ) and d ( C ' i ) for collected the one-bit response obtained in the test mode and bypassing the other PUF elements 50-j in such test mode.
- the auxiliary components 105 arranged in the two paired components d ( C i ) and d ( C ' i ) of each PUF element 50-j of the chain are accordingly configured to enable injection of the rising edge in the auxiliary input test_in i at the upper component d ( C i ), and in the auxiliary input test_in' i at the lower component d ( C ' i ) of the PUF-element 50-j depending on the value of the test mode.
- the test mode signal test_mode may be shared by the paired components d ( C i ) and d ( C' i ) and configured to activate a mode between a test mode in which the PUF is to be tested and a functional PUF mode in which the PUF instance may operate conventionally. Accordingly, if the value of the test mode signal is the value that activates the test mode, the auxiliary input test_in i (respectively test_in' i ) is input to the auxiliary component 105 of each paired component d ( C i ) (respectively d ( C' i )) instead of the main input x i (respectively x ' i for the lower component).
- the main input x i (respectively x ' i ) is input to the auxiliary component 105 of each paired component d ( C i ) (respectively d ( C ' i )).
- the PUF can then operate according its conventional operation mode.
- the auxiliary components of the PUF instance 10 can further comprise additional arbitrating components for arbitrating between the auxiliary output test_out i of the upper component d ( C i ) and the auxiliary output test_out' i of the lower component.
- the arbitrating components may comprise the main arbiter 104 and the following auxiliary components :
- Each auxiliary selector 106 or 107 may be controlled by an index input shared by both auxiliary selectors 106 and 107 and representing the index of the PUF element to be tested. If an index i is selected by the index input in the test mode (the test_mode input has a value that activate the test mode of the PUF), the auxiliary selectors 106 and 107 select respectively the auxiliary outputs test_out i and test_out' i of the paired components of the i - th PUF element. The arbiter 104 may then determine a one-bit response for the i - th PUF element by determining which signal is faster between the signal output at test_out i and the signal output at test_out' i .
- test mode input test_mode has a value that activates the functional mode of the PUF
- the arbiter operates as conventionally using the main outputs y n and y' n of the upper and lower components of the last PUF element in the chain to provide the challenge response of the PUF.
- the auxiliary components of the PUF instance 10 can further comprise elementary arbiters 106 for arbitrating between the auxiliary output test_out i of the upper component d ( C i ) and the auxiliary output test_out' i of the lower component.
- the elementary arbiter 106 associated with each PUF element may be configured to determine determines which signal is faster between the signal output at test_out i and the signal output at test_out' i .
- Each elementary arbiter may be implemented for example as a latch having a latch data input D and a clock C data input.
- a one bit response is read at the output of the elementary arbiter 106 associated with the i - th PUF-element 50-j (step 402 of figure 4 ). More specifically, if the fastest signal between the auxiliary output test_out i of the upper component d ( C i ) and the auxiliary output test_out' i of the lower component d ( C ' i ) is test_out i (auxiliary output of the upper component d ( C i )), the elementary arbiter 106 may deliver 1 as the one-bit response. Otherwise, if the fastest signal between test_out i and test_out' i is test_out' i (auxiliary output of the lower component d ( C' i )), the elementary arbiter 106 may deliver 0 as the one-bit response.
- challenge values may be applied iteratively to the i - th PUF element, and at each iteration the one bit response may be read.
- the one-bit responses obtained for the different challenge values applied to the PUF in the test mode may be stored in a data structure.
- the one-bit responses obtained for the i - th PUF element may be aggregated or combined when a predefined or selected number of challenges have been applied to generate an identifier of the i - th PUF element (step 404 of figure 4 ).
- the testing device 11 of the testing system is configured to acquire the identifiers of the PUF elements of neighboring PUF instances of the same PUF batch 20 that are implemented on the same device 12
- the PUF instance being tested may acquire identifiers of PUF elements of the neighboring PUF instances using an exchange protocol such as for example the Diffie-Hellman protocol.
- the testing device may then acquire the identifiers to constitute the group of identifier to be tested using the randomness test from the PUF instance directly (step 304 of figure 3 ).
- the neighboring PUF may transmit the identifiers of their PUF elements directly to the testing device 11.
- testing device 11 is implemented in the form of a server connected to each PUF instance via a network 60 as depicted in figure 8
- the testing device may be configured to acquire identifiers of PUF elements of other PUF instances of the same batch 20 whether implemented in the same device 12 or in another device.
- Figure 8 shows an exemplary implementation of the testing system 100 in which the testing device 11 is configured to acquire the identifiers of the PUF elements of additional PUF instances of the same PUF batch 20.
- the testing device 11 may be implemented in the form of a server connected to each PUF instance via a network 60 as depicted in figure 8 , the PUF instances may also comprise other PUF instances of the same batch 20 whether implemented in the same device 12 or in another device.
- the server may include a user interface for entering request for testing a particular PUF batch 20, the batch being identified by a batch number.
- the testing device may then acquire the identifiers of PUF elements of the PUF instances corresponding to the batch number which are connected thereto
- the network may be any suitable network such as the Internet, a local area network (LAN), a wide area network (WAN) and/or other such types of communication networks.
- each PUF instance returns K identifiers and N PUF instances are used to form the group of tested identifiers
- the number of identifiers of the group of identifiers to which the randomness test is applied may be augmented to kxN.
- the identifiers acquired from the other PUF instances may be added in the group of identifiers to which the randomness test is applied (as described with reference to step 304 of figure 3 ).
- the identifiers acquired from each PUF instance may be tested separately by the randomness test application unit (i.e the randomness test is applied to groups of identifiers, the identifier of each group corresponding to one PUF instance).
- Embodiments of the present invention enable testing the randomness/unpredictability property (property that PUFs responses are not predictable) and the uniqueness property (property that instances of PUFs differ) of a PUF batch by testing the PUF elements that are comprised in at least a single PUF instance of the PUF batch or in a limited number of PUF instances.
- the testing method invention may be implemented online, i.e. in situations where the PUF instances are implemented in a device by switching the operation of the PUF into a test mode.
- Embodiments of the present invention may be carried out in the field, on the device embedding the PUF (integrated circuit, final product, etc.).
- the testing system 100 may be implemented without requiring external connections that create "backdoor”.
- the testing method may be implemented during the life cycle of a PUF instance, such as for examples:
- the testing device 11 may be implemented on one or more computing devices or systems, referred to collectively as a computer such as computer 70.
- the computer 70 may include a processor 71, a memory 72, a mass storage memory device 75, an input/output (I/O) interface 77, and a Human Machine Interface (HMI) 78.
- the computer 70 may also be connected to one or more devices 11 embedding at least one PUF instance and be operatively coupled to one or more external resources via the network 60 and/or I/O interface 77.
- External resources may include, but are not limited to, servers, databases, mass storage devices, peripheral devices, cloud-based network services, or any other suitable computing resource that may used by the computer 70.
- the processor 71 may include one or more devices that manipulate signals (analog or digital) based on operational instructions that are stored in the memory 72, such as microprocessors, micro-controllers, digital signal processors, microcomputers, central processing units, etc.
- Memory 72 may include a single memory device or a plurality of memory devices including, but not limited to, read-only memory (ROM), random access memory (RAM), volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache memory, or any other device capable of storing information.
- Processor 71 may execute instructions directly or under the control of an operating system 75 that resides in memory 72.
- the operating system 75 may manage computing resources so that computer program code embodied as one or more computer software applications, such as an application 74 residing in memory 72, may have instructions executed by the processor 71.
- One or more data structures 72 may also reside in memory 72, and may be used by the processor 71, operating system 75, and/or application 74 to store or manipulate data.
- the data structures 72 may include data structures for storing identifiers of the PUF elements acquired from a PUF instance 10 of a given PUF batch 20.
- the I/O interface 77 may provide a machine interface that operatively couples the processor 71 to other devices and systems, such as the network 60 and/or external resource 42.
- the HMI 78 may be operatively coupled to the processor 32 of computer 30 in a known manner to allow a user of the computer 30 to interact directly with the computer 30.
- the HMI 78 may include any suitable audio and visual indicators capable of providing information to the user (video and/or alphanumeric displays, a touch screen, a speaker, etc.) and input devices and controls capable of accepting commands or input from the user and transmitting the entered input to the processor 70.
- the methods described herein can be implemented by computer program instructions supplied to the processor of any type of computer to produce a machine with a processor that executes the instructions to implement the functions/acts specified herein.
- These computer program instructions may also be stored in a computer-readable medium that can direct a computer to function in a particular manner. To that end, the computer program instructions may be loaded onto a computer to cause the performance of a series of operational steps and thereby produce a computer implemented process such that the executed instructions provide processes for implementing the functions/acts specified herein.
- testing system and method described herein may be implemented by various means in hardware, software, or a combination thereof.
- Figure 8 shows an exemplary implementation of the testing system 100 in which the testing device 11 is configured to acquire the identifiers of the PUF elements of additional PUF instances of the same PUF batch 20.
- the testing device 11 may be implemented in the form of a server connected to each PUF instance via a network 60 as depicted in figure 8 , the PUF instances may also comprise other PUF instances of the same batch 20 whether implemented in the same device 12 or in another device.
- the server may include a user interface for entering request for testing a particular PUF batch 20, the batch being identified by a batch number.
- the testing device may then acquire the identifiers of PUF elements of the PUF instances corresponding to the batch number which are connected thereto
- the network may be any suitable network such as the Internet, a local area network (LAN), a wide area network (WAN) and/or other such types of communication networks.
- each PUF instance returns K identifiers and N PUF instances are used to form the group of tested identifiers
- the number of identifiers of the group of identifiers to which the randomness test is applied may be augmented to kxN.
- the identifiers acquired from the other PUF instances may be added in the group of identifiers to which the randomness test is applied (as described with reference to step 304 of figure 3 ).
- the identifiers acquired from each PUF instance may be tested separately by the randomness test application unit (i.e the randomness test is applied to groups of identifiers, the identifier of each group corresponding to one PUF instance).
- Embodiments of the present invention enable testing the randomness/unpredictability property (property that PUFs responses are not predictable) and the uniqueness property (property that instances of PUFs differ) of a PUF batch by testing the PUF elements that are comprised in at least a single PUF instance of the PUF batch or in a limited number of PUF instances.
- the testing method invention may be implemented online, i.e. in situations where the PUF instances are implemented in a device by switching the operation of the PUF into a test mode.
- Embodiments of the present invention may be carried out in the field, on the device embedding the PUF (integrated circuit, final product, etc.).
- the testing system 100 may be implemented without requiring external connections that create "backdoor”.
- the testing method may be implemented during the life cycle of a PUF instance, such as for examples:
- the testing device 11 may be implemented on one or more computing devices or systems, referred to collectively as a computer such as computer 70.
- the computer 70 may include a processor 71, a memory 72, a mass storage memory device 75, an input/output (I/O) interface 77, and a Human Machine Interface (HMI) 78.
- the computer 70 may also be connected to one or more devices 11 embedding at least one PUF instance and be operatively coupled to one or more external resources via the network 60 and/or I/O interface 77.
- External resources may include, but are not limited to, servers, databases, mass storage devices, peripheral devices, cloud-based network services, or any other suitable computing resource that may used by the computer 70.
- the processor 71 may include one or more devices that manipulate signals (analog or digital) based on operational instructions that are stored in the memory 72, such as microprocessors, micro-controllers, digital signal processors, microcomputers, central processing units, etc.
- Memory 72 may include a single memory device or a plurality of memory devices including, but not limited to, read-only memory (ROM), random access memory (RAM), volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache memory, or any other device capable of storing information.
- Processor 71 may execute instructions directly or under the control of an operating system 75 that resides in memory 72.
- the operating system 75 may manage computing resources so that computer program code embodied as one or more computer software applications, such as an application 74 residing in memory 72, may have instructions executed by the processor 71.
- One or more data structures 72 may also reside in memory 72, and may be used by the processor 71, operating system 75, and/or application 74 to store or manipulate data.
- the data structures 72 may include data structures for storing identifiers of the PUF elements acquired from a PUF instance 10 of a given PUF batch 20.
- the I/O interface 77 may provide a machine interface that operatively couples the processor 71 to other devices and systems, such as the network 60 and/or external resource 42.
- the HMI 78 may be operatively coupled to the processor 32 of computer 30 in a known manner to allow a user of the computer 30 to interact directly with the computer 30.
- the HMI 78 may include any suitable audio and visual indicators capable of providing information to the user (video and/or alphanumeric displays, a touch screen, a speaker, etc.) and input devices and controls capable of accepting commands or input from the user and transmitting the entered input to the processor 70.
- the methods described herein can be implemented by computer program instructions supplied to the processor of any type of computer to produce a machine with a processor that executes the instructions to implement the functions/acts specified herein.
- These computer program instructions may also be stored in a computer-readable medium that can direct a computer to function in a particular manner. To that end, the computer program instructions may be loaded onto a computer to cause the performance of a series of operational steps and thereby produce a computer implemented process such that the executed instructions provide processes for implementing the functions/acts specified herein.
- testing system and method described herein may be implemented by various means in hardware, software, or a combination thereof.
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Claims (16)
- Verfahren zum Prüfen der Einmaligkeit eines PUF-(Physisch Unklonbare Funktion)-Stapels, der einen Satz von PUF-Instanzen umfasst, wobei das Verfahren in einem Gerät (12) implementiert wird, wobei das Verfahren das Prüfen der Einmaligkeit des PUF-Stapels durch Prüfen einer zu dem PUF-Stapel gehörenden PUF-Instanz umfasst, wobei die PUF-Instanz zum Empfangen mindestens einer Eingabe ("Challenge"), wobei jede Eingabe einen Satz von Bits umfasst, und zum Erzeugen eines Satzes von Antworten konfiguriert ist, wobei jede Antwort mindestens ein Bit umfasst und einer Eingabe entspricht, wobei die PUF-Instanz eine Schaltung umfasst, die einen Satz von PUF-Elementen (50) einschließt, die wiederholten Mustern entsprechen, wobei jedes Muster einen Satz von physischen Komponenten einschließt, wobei jedes PUF-Element durch mindestens ein Eingangsbit gesteuert wird, das mindestens einem Bit der Eingabe entspricht, wobei der Schritt des Prüfens der PUF-Instanz Folgendes umfasst:- Anwenden mindestens eines Bits der Eingabe auf die PUF-Instanz;- Bestimmen von Kennungen für mindestens einige der PUF-Elemente, wobei die Kennung jedes PUF-Elements aus der von dem PUF-Element als Reaktion auf das mindestens eine Bit der Eingabe ausgegebenen Antwort bestimmt wird, wobei die von dem PUF-Element ausgegebene Antwort mittels zum Lesen der Antwort ausgelegter Hilfskomponenten gelesen wird, wobei der Schritt des Bestimmens von Kennungen für mindestens einige der PUF-Elemente das Lesen des Ausgangs der mindestens einigen PUF-Elemente gemäß einem Leseprotokoll umfasst;- Anwenden einer statistischen Zufälligkeitsprüfung auf eine Gruppe von Kennungen, die mindestens einige der für die PUF-Elemente bestimmten Kennungen umfasst, was einen Prüfindikator ergibt,wobei dem Prüfindikator ein erster Wert zugewiesen wird, wenn in dem Schritt des Anwendens einer statistischen Zufälligkeitsprüfung festgestellt wird, dass mindestens eine PUF-Kennung innerhalb der Gruppe von PUF-Elementekennungen redundant ist, wobei das Verfahren ferner einen Schritt des Auslösens einer Aktion als Reaktion darauf umfasst, dass dem Prüfindikator der erste Wert zugewiesen wird.
- Verfahren nach Anspruch 1, wobei das Leseprotokoll aus einer Gruppe bestehend aus einem sequentiellen Leseprotokoll und einem parallelen Leseprotokoll ausgewählt wird.
- Verfahren nach Anspruch 2, wobei der Schritt des Bestimmens der Kennung jedes PUF-Elements Folgendes umfasst:- iteratives Anwenden eines Satzes von Eingaben und Lesen der von dem PUF-Element als Reaktion auf jede Eingabe ausgegebenen Antwort;- Bestimmen der Kennung der PUF-Kennung aus den Antworten.
- Verfahren nach Anspruch 3, wobei die von dem PUF-Element ausgegebene Antwort mindestens ein Bit umfasst und der Schritt des Bestimmens der Kennung der PUF-Kennung aus den Antworten das Aggregieren mindestens einiger der für den Satz von Eingaben gelesenen Antworten umfasst.
- Verfahren nach einem der Ansprüche 3 und 4, wobei das Verfahren ferner das Speichern der am Ausgang jedes PUF-Elements gelesenen Antworten in einer Datenstruktur umfasst.
- Verfahren nach einem vorherigen Anspruch, wobei die PUF eine Arbiter-PUF ist, die einen Satz von PUF-Elementen (50) umfasst, wobei jedes PUF-Element ein Verzögerungselement mit gepaarten Komponenten ist, wobei jede gepaarte Komponente mindestens eine Schalteinheit (52) mit einem Haupteingang zum Empfangen eines Signals umfasst, wobei die gepaarten Komponenten einen Steuereingang gemeinsam nutzen, der das mindestens eine Bit der mit dem PUF-Element assoziierten Eingabe empfängt, wobei die gepaarten Komponenten der Arbiter-PUF zwei logische Pfade als Reaktion auf eine Eingabe definieren, wobei die PUF ferner eine Hauptarbitereinheit (104) am Ende der logischen Pfade zum Vergleichen der analogen Zeitdifferenz zwischen den beiden logischen Pfaden und zum Erzeugen eines digitalen Ausgangs in Abhängigkeit von den Zeitdifferenzen umfasst, wobei die PUF ferner Hilfskomponenten zum Erzeugen eines Bitwertes durch Bestimmen umfasst, welches Signal zwischen den beiden an den gepaarten Komponenten jedes PUF-Elements ausgegebenen Signalen schneller ist, wobei die Antwort am Ausgang des PUF-Elements gleich dem Bitwert ist.
- Verfahren nach Anspruch 6, wobei die Hilfskomponenten ferner mindestens einen Selektor umfassen, der zum Auswählen der Ausgänge der gepaarten Komponenten eines ausgewählten PUF-Elements und zum Übertragen der Ausgänge in einem Prüfmodus zu der Arbitereinheit konfiguriert ist.
- Verfahren nach Anspruch 7, wobei der mindestens eine Selektor durch ein Indexbit gesteuert wird, wobei das Indexbit einen Wert hat, der den Index des gewählten PUF-Elements repräsentiert.
- Verfahren nach Anspruch 8, wobei die Hilfskomponenten ferner einen Satz von elementaren Arbitrierungseinheiten (108) umfassen, wobei jede elementare Arbitrierungseinheit am Ausgang eines PUF-Elements angeordnet und zum Empfangen der Ausgänge der gepaarten Komponenten des PUF-Elements in einem Prüfmodus und zum Erzeugen des Bitwertes konfiguriert ist.
- Verfahren nach einem vorherigen Anspruch, wobei das Verfahren ferner das Erkennen von beim Erfassen der Kennungen der PUF-Elemente entstehenden Fehlern und das Korrigieren der Fehler umfasst.
- Verfahren nach einem vorherigen Anspruch, wobei das Verfahren ferner das Bestimmen der Kennungen benachbarter PUF-Elemente einer oder mehrerer PUF-Instanzen des PUF-Stapels (20) umfasst, die sich in der Nähe der PUF in dem Gerät befinden, wobei die Gruppe von PUFs ferner die Kennungen der benachbarten PUF-Elemente umfasst.
- Verfahren nach Anspruch 11, wobei die Kennungen benachbarter PUF-Elemente gemäß einem Diffie-Hellman-Protokoll zur PUF-Instanz übertragen werden.
- Verfahren nach einem vorherigen Anspruch, wobei die mindestens eine statistische Zufälligkeitsprüfung aus einer Gruppe bestehend aus einer Entropieprüfung und einer Maurer-Prüfung ausgewählt wird.
- Verfahren nach einem vorherigen Anspruch, wobei die Aktion aus einer Gruppe bestehend aus einem Rückruf der PUF, einer Deaktivierung der PUF, einer Ausgabe einer Benachrichtigung oder einer Ausgabe einer Warnmeldung ausgewählt wird.
- Computerprogramm, das Befehle zum Ausführen der Schritte des Verfahrens nach einem der Ansprüche 1 bis 14 umfasst, wenn das Computerprogramm auf einem geeigneten Computergerät ausgeführt wird.
- System, das eine integrierte Schaltungsanordnung, die eine physisch unklonbare Funktion (PUF) implementiert, und ein Prüfgerät zum Prüfen der Einmaligkeit eines PUF-(Physisch Unklonbare Funktion)-Stapels mit einem Satz von PUF-Instanzen umfasst, wobei das Prüfgerät so konfiguriert ist, dass es die Einmaligkeit des PUF-Stapels durch Prüfen der zum PUF-Stapel gehörenden PUF-Instanz prüft, wobei die PUF-Instanz konfiguriert ist zum Empfangen mindestens einer Eingabe ("Challenge"), wobei jede Eingabe einen Satz von Bits umfasst, und zum Erzeugen eines Satzes von Antworten, wobei jede Antwort mindestens ein Bit umfasst und einer Eingabe entspricht, wobei die PUF-Instanz eine Schaltung umfasst, die einen Satz von PUF-Elementen einschließt, die wiederholten Mustern entsprechen, wobei jedes Muster einen Satz von PUF-Elementen von physischen Komponenten einschließt, wobei jedes PUF-Element durch mindestens ein Eingangsbit gesteuert wird, das mindestens einem Bit der Eingabe entspricht, wobei das Prüfgerät so konfiguriert ist, dass es mindestens ein Bit der Eingabe auf eine PUF-Instanz anwendet, wobei das Prüfgerät Folgendes umfasst:- eine Kennungserfassungseinheit (110), konfiguriert zum Bestimmen von Kennungen für mindestens einige der PUF-Elemente, wobei die Kennung jedes PUF-Elements aus der von dem PUF-Element als Reaktion auf das mindestens eine Bit der Eingabe ausgegebenen Antwort bestimmt wird, wobei die von dem PUF-Element ausgegebene Antwort mittels Hilfskomponenten gelesen wird, die zum Lesen der Antwort ausgelegt sind, wobei das Bestimmen von Kennungen für mindestens einige der PUF-Elemente ein Lesen des Ausgangs der mindestens einigen PUF-Elemente gemäß einem Leseprotokoll umfasst;- eine Zufälligkeitsprüfungsanwendungseinheit (112), konfiguriert zum Anwenden einer statistischen Zufälligkeitsprüfung auf eine Gruppe von Kennungen, die mindestens einige der für die PUF-Elemente bestimmten Kennungen umfasst, was einen Prüfindikator ergibt, wobei der Prüfindikator einem ersten Wert zugewiesen wird, wenn bei der Anwendung einer statistischen Zufälligkeitsprüfung festgestellt wird, dass mindestens eine PUF-Kennung in der Gruppe von PUF-Elementekennungen redundant ist, wobei das System zum Auslösen einer Aktion als Reaktion darauf konfiguriert ist, dass dem Prüfindikator der erste Wert zugewiesen wird.
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US20170295026A1 (en) | 2017-10-12 |
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