EP3176669A1 - Schaltkreis zur erzeugung einer referenzspannung - Google Patents

Schaltkreis zur erzeugung einer referenzspannung Download PDF

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Publication number
EP3176669A1
EP3176669A1 EP16200987.2A EP16200987A EP3176669A1 EP 3176669 A1 EP3176669 A1 EP 3176669A1 EP 16200987 A EP16200987 A EP 16200987A EP 3176669 A1 EP3176669 A1 EP 3176669A1
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Prior art keywords
transistor
transistors
circuit
type
node
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EP16200987.2A
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English (en)
French (fr)
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EP3176669B1 (de
Inventor
Anthony Quelen
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • the present application relates to the field of electronic systems in general, and more particularly relates to a reference voltage generation circuit.
  • a reference voltage generation circuit is used to generate, from a continuous supply voltage of the system, a continuous reference voltage independent of the fluctuations of the supply voltage and independent temperature variations.
  • a circuit is generally integrated in a semiconductor chip which may be an autonomous chip or which may comprise other circuits intended to implement other functions of the system.
  • a lower reference voltage typically less than 1 V, for example a voltage of the order of 0.9 V.
  • circuits however, have various disadvantages.
  • these circuits are relatively sensitive to manufacturing process variations, and therefore have a relatively low intrinsic accuracy.
  • two separate circuits produced by the same method can, because of process dispersions, generate distinct reference voltages.
  • the variability of the reference voltage as a function of the manufacturing process variations is moreover sought and exploited to characterize and compensate for the process dispersions.
  • an embodiment provides a reference voltage generation circuit realized in FDSOI technology, comprising: a first circuit for generating a CTAT type bias current; a second PTAT voltage generating circuit having a first branch having first and second transistors in series, the front face gates of the first and second transistors being connected to the conduction node of the second transistor opposite the first transistor; a third diode-mounted transistor having a conduction node connected to a supply node of the output voltage of the second circuit and whose other conduction node is a supply node of the reference voltage; and an imposing current mirror, in the third transistor on the one hand and in the first branch on the other hand, currents proportional to the bias current, in which the first and second transistors are of the LVT type, and the third transistor is RVT type.
  • the first transistor has a first front gate gate oxide thickness
  • the second and third transistors have a second gate oxide thickness of the front face greater than the first thickness
  • the first, second and third transistors are NMOS transistors, the drain of the first transistor being connected to the source of the second transistor, the drain of the second transistor being connected to the gates of the first and second transistors, and the source the third transistor being connected to a supply node of the output voltage of the second circuit.
  • the second circuit further comprises a second branch comprising fourth and fifth transistors in series, the front face gates of the fourth and fifth transistors being connected to the conduction node of the fifth transistor opposite to the fourth transistor, and the conduction node of the fourth transistor opposite the fifth transistor being connected to the midpoint of the series association of the first and second transistors.
  • the current mirror imposes in the second branch a current proportional to the bias current.
  • the midpoint of the series association of the fourth and fifth transistors constitutes a node for supplying the output voltage of the second circuit.
  • the fourth and fifth transistors are NMOS transistors, the drain of the fourth transistor being connected to the source of the fifth transistor, and the drain of the fifth transistor being connected to the gates of the fourth and fifth transistors.
  • the fourth and fifth transistors are both of the RVT type or both of the LVT type.
  • the first circuit comprises sixth and seventh current-mirror transistors, and an eighth transistor connected in series with the seventh transistor, the sixth and seventh transistors being of same type LVT or RVT and having the same front gate gate oxide thickness, and the sixth transistor having a channel width to channel length ratio greater than that of the seventh transistor.
  • the eighth transistor is of the LVT type.
  • the sixth, seventh and eighth transistors are of the NMOS type.
  • the eighth transistor has its front face gate connected to the supply node of the reference voltage.
  • connection is used to denote a direct electrical connection, without intermediate electronic component, for example by means of one or more conductive tracks, and the term “coupled” or the term “connected”, for designate either a direct electrical connection (meaning “connected”) or a connection via one or more intermediate components (resistor, diode, capacitor, etc.).
  • the figure 1 is an electrical diagram of an example of an embodiment of a reference voltage generating circuit.
  • the circuit of the figure 1 is based on MOS transistors in FDSOI technology (from the English "Fully Depleted Semiconductor On Insulator” - fully depletable semiconductor on insulator). More particularly, the MOS transistors of the circuit of the figure 1 are made in and on a semiconductor-on-insulator structure comprising a stack of a semiconductor substrate coated with a layer of a dielectric material, this layer itself being coated with a semiconductor layer. Each transistor comprises an insulated conductive gate, called a front face gate, coating the face of the semiconductor layer opposite to the dielectric layer. The channel forming region of the transistor is located under the front face gate in the semiconductor layer.
  • the source and drain regions of the transistor are, for example, implanted regions formed in the semiconductor layer, on either side of the channel forming region.
  • the source and drain regions are respectively P-type doped for a P-channel transistor (PMOS) and N-doped for an N-channel transistor (NMOS).
  • the substrate region below the dielectric layer, opposite the channel forming region of the transistor, is referred to as the backplane gate, and may be biased to control the threshold voltage of the transistor.
  • RVT of the English "Regular Voltage Threshold”
  • LVT of English “Low Voltage Threshold”
  • the RVT transistors have a higher threshold voltage than the LVT transistors.
  • the doping of the substrate region in contact with the dielectric layer, with respect to the channel forming region of the transistor (corresponding to the front grid) is used. back of the transistor).
  • the LVT transistors comprise a well of the same type of conductivity as the source and drain regions of the transistor, extending in the substrate, under the dielectric layer, facing the channel forming region of the transistor
  • the RVT transistors comprise a well of conductivity type opposite to that of the source and drain regions, extending in the substrate, under the dielectric layer, facing the channel forming region of the transistor.
  • the LVT or RVT behavior of the transistors can be obtained by playing on a parameter other than the doping of the substrate region located under the channel forming region of the transistor, for example by playing on the doping of the gate front face of the transistor.
  • each of the four types of transistors mentioned above namely the NMOS LVT type, the NMOS RVT type, the PMOS LVT type and the PMOS RVT type
  • SO and DO respectively, corresponding to oxide or insulator front different.
  • the SO (single oxide) type transistors have a first front gate gate oxide thickness
  • the (double oxide) type DO transistors have a second upper front gate gate oxide thickness. at the first thickness, for example twice the first thickness.
  • the circuit of the figure 1 comprises terminals or nodes VDD and VSS for applying a supply voltage V SUPPLY , and a terminal or a node REF for supplying a reference voltage V REF .
  • the VDD node is intended to receive the high potential of the supply voltage V SUPPLY
  • the VSS node is intended to receive the low potential of the supply voltage V SUPPLY .
  • the reference voltage V REF supplied on the node REF is referenced with respect to the node VSS, which corresponds for example to the ground of the circuit.
  • the circuit of the figure 1 comprises a circuit 101 for generating a bias current I CTAT type (English “Complementary To Absolute Temperature”), that is to say, whose intensity decreases when the temperature increases.
  • the current I is generated from a gate-source voltage difference between two transistors N1 and N2 of the same type but having different dimensions. This difference of gate-source voltages is applied across a transistor N3 operating in linear mode to generate the current I.
  • the transistors N1, N2 and N3 are NMOS transistors.
  • Transistors N1 and N2 are for example both LVT transistors.
  • transistors N1 and N2 are both RVT transistors.
  • Transistors N1 and N2 are for example both thick oxide (DO).
  • the transistor N3 is, for example, a NMOS LVT thick oxide (DO) transistor.
  • the ratio K N1 between the channel width W N1 and the channel length L N1 of the transistor N1 is different from the ratio K N2 between the channel width W N2 and the channel length L N2 of the transistor N2.
  • the ratio K N1 is smaller than the ratio K N2 so that, in operation, the gate-source voltage the transistor N1 is greater than the gate-source voltage of the transistor N2.
  • the transistors N1 and N2 are mounted in a current mirror. More particularly, the transistor N1 has its front face gate connected to its drain and its source connected to the VSS node. The front face gate of transistor N2 is connected to the front face gate of transistor N1.
  • the source of transistor N2 is connected to node VSS via transistor N3. More particularly, the drain of the transistor N3 is connected to the source of the transistor N2, and the source of the transistor N3 is connected to the node VSS. In this example, the front face gate of the transistor N3 is connected to the output node REF of the circuit.
  • the polarization current generation circuit 101 comprises a PMOS transistor P1 connecting the drain of the transistor N1 to the node VDD, and a PMOS transistor P2 connecting the drain of the transistor N2 to the node VDD.
  • the transistor P1 has its drain connected to the drain of the transistor N1, and the transistor P2 has its drain connected to the drain of the transistor N2.
  • the transistor P1 has its source connected to the VDD node, and the transistor P2 has its source connected to the VDD node.
  • Transistors P1 and P2 are mounted in current mirror. More particularly, the transistor P1 has its front face gate connected to the front face gate of the transistor P2, and the transistor P2 has its front face gate connected to its drain.
  • Transistors P1 and P2 are for example both RVT transistors. Alternatively, the transistors P1 and P2 are both LVT transistors. Transistors P1 and P2 are for example both thick oxide (DO).
  • the circuit of the figure 1 further comprises a circuit 103 for generating a voltage V of the type PTAT (of the English “Proportional To Absolute Temperature”), that is to say whose value increases when the temperature increases.
  • V of the type PTAT of the English “Proportional To Absolute Temperature”
  • the circuit 103 comprises a first branch comprising a transistor N4 in series with a transistor N5, and a second branch comprising a transistor N6 in series. with an N7 transistor.
  • the transistors N4, N5, N6 and N7 are of the NMOS type.
  • the transistors N4 and N5 are, for example, respectively of the LVT type with thin oxide (SO) and of the LVT type with thick oxide (DO).
  • the transistors N4 and N5 of the first branch are respectively of the LVT type with thin oxide (SO) and type RVT with thick oxide (DO).
  • the transistors N4 and N5 of the first branch are respectively of the RVT type with thin oxide (SO) and of the LVT type with thick oxide (DO).
  • the first branch is a so-called mixed oxide thickness branch (that is to say that its node-side transistor VSS, namely its transistor N4, is a thin-oxide transistor, and that its opposite transistor at the node VSS, namely its transistor N5, is a thick oxide transistor), of which at least one of the two transistors N4 and N5 is of the LVT type.
  • Transistors N6 and N7 are for example both RVT transistors. Alternatively, transistors N6 and N7 are both LVT transistors. Transistors N5 and N6 are thick oxide (DO) transistors. Thus, in this example, the second branch is a branch called thick oxide (that is to say that its two transistors N6 and N7 are thick oxide transistors), the two transistors N6 and N7 are of the same type either LVT or RVT.
  • thick oxide that is to say that its two transistors N6 and N7 are thick oxide transistors
  • the transistor N4 has its source connected to the node VSS and its drain connected to the source of the transistor N5.
  • the transistor N5 has its drain connected to its front face gate.
  • the front face gate of transistor N5 is further connected to the front face gate of transistor N4.
  • the transistor N6 has its source connected to the midpoint of the series association of the transistors N4 and N5, that is to say the source of the transistor N5 and the drain of the transistor N4.
  • the transistor N6 has its drain connected to the source of the transistor N7.
  • the transistor N7 has its drain connected to its front face gate.
  • the front face gate of transistor N7 is further connected to the front face gate of transistor N6.
  • the midpoint of the series association of the N6 and N7 transistors that is to say the source node of the transistor N7 or drain node of the transistor N6 constitutes the supply node of the output voltage V of the circuit 103 (referenced with respect to the node VSS).
  • the circuit 103 further comprises a PMOS transistor P3 connecting the drain of the transistor N5 to the node VDD, and a PMOS transistor P4 connecting the drain of the transistor N7 to the node VDD.
  • the transistor P3 has its drain connected to the drain of the transistor N5, and the transistor P4 has its drain connected to the drain of the transistor N7.
  • the transistors P3 and P4 each have their source connected to the VDD node.
  • Each of the transistors P3 and P4 is mounted to form a current mirror with the transistor P2. More particularly, the transistor P3 has its front face gate connected to the front face gate of the transistor P2, and the transistor P4 has its front face gate connected to the front face gate of the transistor P2.
  • Transistors P3 and P4 are for example both RVT transistors. Alternatively, transistors P3 and P4 are both LVT transistors. Transistors P3 and P4 are for example both thick oxide (DO).
  • the circuit of the figure 1 further comprises a diode-connected transistor N8, in which the CTAT-type bias current I is applied, and a conduction node of which receives the PTAT output voltage V of the circuit 103.
  • the transistor N8 is an NMOS transistor.
  • Transistor N8 is, for example, an RVT transistor, for example a thick oxide (DO) transistor.
  • the source of the transistor N8 is connected to the node supplying the output voltage V of the circuit 103, that is to say to the source node of the transistor N7 and the drain node of the transistor N6 in this example.
  • the drain of the transistor N8 is connected to its front face gate, and to the output node REF of the circuit of the figure 1 .
  • the circuit of the figure 1 further comprises a PMOS transistor P5 connecting the drain of the N8 transistor to the VDD node.
  • the transistor P5 has its drain connected to the drain of the transistor N8, and its source connected to the node VDD.
  • the transistor P5 is mounted to form a current mirror with the transistor P2. More particularly, the transistor P5 has its front face gate connected to the front face gate of the transistor P2.
  • the transistor P5 may be RVT type or LVT type.
  • transistor P5 is thick oxide (DO).
  • the transistors P1, P2, P3, P4 and P5 are for example identical, that is to say of the same type (RVT or LVT, of the same oxide thickness DO or SO) and of substantially the same dimensions.
  • a same bias current I flows in the branch comprising the transistors P1 and N1, and in the branch comprising the transistors P2, N2 and N3.
  • the internal resistance of the transistor N3 increases with the temperature more rapidly than the voltage PTAT seen by the transistor N3, so that the current I (which is the ratio of the voltage across the terminals of the transistor N3 by the internal resistance of the transistor N3) decreases. with the temperature.
  • the bias current I generated by the circuit 101 is copied in the branch comprising the transistors P3, N5 and N4, and in the branch comprising the transistors P4, N7 and N6.
  • a voltage v1 PTAT type is provided on the midpoint of the series association of transistors N4 and N5, and a voltage v2, also of type PTAT but of level greater than v1, is provided on the midpoint of the series association of N6 and N7 transistors.
  • the voltages v1 and v2 are referenced with respect to the VSS node.
  • the output voltage V of the circuit 103 is the voltage v2.
  • the bias current I generated by the circuit 101 is further copied into the branch comprising the transistors P5 and N8.
  • the output voltage V REF of the circuit of the figure 1 is equal to the sum of the gate-source voltage of the transistor N8 and the output voltage V of the circuit 103.
  • the current I tends to decrease, and the threshold voltage of the N8 transistor tends to decrease, which tends to lower the voltage V REF .
  • the output voltage V of the circuit 103 increases with the temperature, which makes it possible to maintain the voltage V REF relatively stable in temperature.
  • the supply voltage V SUPPLY and the dimensions of the transistors of the circuit of the figure 1 are preferably chosen so that, in operation, the transistors P1, P2, P3, P4, P5, N4, N5 and N8 are in the saturation regime, the transistors N1, N2, N6 and N7 are in the conduction regime under the threshold, and the transistor N3 is in linear mode.
  • all the NMOS transistors of the circuit of the figure 1 have their rear face grids connected to ground, that is to say to the VSS node, and all the PMOS transistors of the circuit have their rear face grids connected to the VDD node of application of the high supply potential of the circuit .
  • the described embodiments are however not limited to particular case.
  • all the transistors of the circuit of the figure 1 may have, in operation, their polarized rear face grids at the same reference potential different from the potential of the VSS or VDD node.
  • the distinct transistors of the circuit of the figure 1 may have, in operation, their polarized rear face grids at different potentials.
  • the figure 2 is a diagram illustrating the behavior of the circuit of the figure 1 .
  • the figure 2 represents the evolution as a function of the temperature, in a temperature range from -40 ° C to + 125 ° C, of the bias current I, in nanoamperes, voltages v1 and v2, in mV, and the voltage of output V REF , in mV of the circuit of the figure 1 .
  • the current I decreases substantially linearly with the temperature from a high value of the order of 20.2 nA for a temperature of -40 ° C to a low value of the order of 16.5 nA for a temperature of 125 ° C
  • the voltage v1 increases substantially linearly with temperature from a low value of the order of 172 mV for a temperature of -40 ° C to a high value of the order 215 mV for a temperature of 125 ° C
  • the voltage v2 increases substantially linearly with the temperature from a low value of the order of 280 mV for a temperature of -40 ° C to a high value of the order of 385 mV for a temperature of 125 ° C.
  • the reference voltage V REF evolves in a bell-shaped form between about 928 mV and 934 mV in the temperature range of -40 ° C to + 125 ° C.
  • the figure 3 represents the evolution of the output voltage V REF of the circuit of the figure 1 depending on the temperature, in the temperature range of -40 ° C to + 125 ° C, at the different limits of the variations of parameters of the manufacturing process, in the FDSOI manufacturing technology considered (here 28 nm FDSOI technology).
  • the figure 3 comprises an FSA curve corresponding to the case where the NMOS transistors are faster than normal and the PMOS transistors are slower than normal, an FFA curve corresponding to the case where the NMOS and PMOS transistors are faster than normal, an SFA curve corresponding to the case where the NMOS transistors are slower than normal and the PMOS transistors are faster than normal, an SSA curve corresponding to the case where the NMOS and PMOS transistors are slower than normal, and a TYP curve corresponding to the case where the NMOS and PMOS transistors have an average speed.
  • the vagueness of the circuit of the figure 1 Manufacturing dispersions are of the order of 5.5 mV at 25 ° C for a typical reference voltage of the order of 934 mV, which corresponds to an inaccuracy of 0.5% peak-to-peak.
  • the measurements carried out show that, at a given temperature, the ratio of the standard deviation of the distribution of the reference voltages supplied by the circuits of a batch representative of the manufacturing process variations, to the average reference voltage of the distribution , is of the order of +/- 0.1%.
  • the inventors have determined that the good intrinsic accuracy of the circuit of the figure 1 , that is to say the fact that the reference voltage delivered by the circuit is relatively little dependent on process variations, results mainly from the combination of a circuit 103 for generating a voltage V of the PTAT type, one of which first branch (transistors N4 and N5) is of mixed oxide thickness and comprises at least one transistor (N4 or N5) of type LVT, and a transistor N8 type RVT thick oxide to achieve the output stage of the circuit for generating the reference voltage V REF .
  • the choice of a transistor N3 of the LVT type in the second branch of the circuit 101 for generating the Polarization current I also contributes to increasing the intrinsic accuracy of the circuit.
  • an advantage of the circuit of the figure 1 is that the level of the reference voltage supplied can easily be adjusted to the design by varying the bias current I and the channel width to channel length ratio of the different transistors.
  • the reference voltage supplied by the circuit of the figure 1 may, if necessary, be set at a level close to the supply voltage V SUPPLY .
  • the minimum difference between the supply voltage V SUPPLY and the output voltage V REF corresponds to the minimum drain-source voltage necessary to obtain a good copy of the bias current I by the transistor P5, which can be the order of 200 mV.
  • the circuit of figure 1 comprising only MOS transistors, it requires only a small silicon area for its realization, and has a relatively low power consumption. Regarding the area occupied, a compromise may be chosen between the intrinsic accuracy and the silicon surface according to the needs of the application. Indeed, the higher the W * L surfaces of the MOS transistors of the circuit, the better the intrinsic accuracy of the circuit. With regard to consumption, an advantage of the circuit of the figure 1 That is, since the bias current I is of the CTAT type, the consumption of the circuit does not increase when the temperature increases.
  • circuit 101 for generating a polarization current I described in connection with the figure 1 .
  • circuit 101 may be replaced by any other circuit adapted to generate a bias current I of the CTAT type.
  • the circuit 101 may be replaced by a circuit adapted to generate a bias current I PTAT type.
  • the sizing of the transistors, and in particular the size of the transistor N8, can be adjusted to preserve a good temperature stability of the output voltage.
  • the use of a circuit 101 adapted to generate a bias current I CTAT type is preferable insofar as it limits the overall power consumption of the circuit.
  • circuit 103 for generating a voltage V of the PTAT type described in connection with the figure 1 is not limited to the example of circuit 103 for generating a voltage V of the PTAT type described in connection with the figure 1 .
  • the voltage V applied to the source of the transistor N8 is the voltage v1.
  • the N6 transistor located on the VSS node side can be replaced by a thin oxide transistor, the transistor N7 remaining a thick oxide transistor, and at least one of the two transistors N6 and N7 being an LVT type transistor, the other transistor can be LVT type or RVT.
  • each of the first (transistors N4 and N5) and second (transistors N6 and N7) branches of the circuit 103 is a mixed oxide thickness branch comprising at least one LVT type transistor (as described in the preceding paragraph), and the circuit 103 further comprises a third branch comprising a transistor N9 in series with a transistor N10.
  • transistors N9 and N10 are of NMOS type.
  • the third branch is a branch with thick oxide, that is to say that its two Transistors N9 and N10 are thick oxide (DO) transistors.
  • Transistors N9 and N10 are for example both RVT transistors or both LVT transistors.
  • the transistor N9 has its source connected to the midpoint of the series association of the transistors N6 and N7, that is to say the source of the transistor N7 and the drain of the transistor N6.
  • the transistor N9 has its drain connected to the source of the transistor N10.
  • the transistor N10 has its drain connected to its front face gate.
  • the front face gate of transistor N10 is further connected to the front face gate of transistor N9.
  • the midpoint of the series association of transistors N9 and N10 that is to say the source node of transistor N10 and drain of transistor N9, constitutes the supply node of output voltage V of circuit 103. (referenced to the VSS node).
  • the circuit 103 further comprises a PMOS transistor P6 connecting the drain of the transistor N10 to the VDD node.
  • the transistor P6 has its drain connected to the drain of the transistor N10 and its source connected to the node VDD.
  • Transistor P6 is mounted to form a current mirror with transistor P2. More particularly, the transistor P6 has its front face gate connected to the front face gate of the transistor P2.
  • the transistor P6 is for example RVT type.
  • the transistor P6 is of the LVT type.
  • the transistor P6 is for example thick oxide (DO).
  • Transistor P6 is for example identical to transistors P1, P2, P3, P4 and P5.
  • the diode-connected transistor N8 has its source connected either to the midpoint of the second branch, ie to the source node of the transistor N7 and to the drain of the transistor N6, but to the middle point of the third branch that is, the source node of transistor N10 and drain of transistor N9.
  • the bias current I generated by the circuit 101 is copied in the branch comprising the transistors P3, N5 and N4, in the branch comprising the transistors P4, N7 and N6, and in the branch comprising the transistors P6, N10 and N9.
  • a voltage v1 PTAT type is provided on the midpoint of the series association of transistors N4 and N5
  • a voltage v2, also PTAT but level higher than v1 is provided on the midpoint of the series association of the N6 and N7 transistors
  • a voltage v3 also PTAT but level higher than v2 is provided on the midpoint of the series association of N9 and N10 transistors.
  • the output voltage V of the circuit 103 is the voltage v3.
  • the operation of the circuit of the figure 4 is similar to that of the circuit of the figure 1 except that the output voltage V of the circuit 103 is higher than in the example of the figure 1 .
  • An advantage of the circuit of the figure 4 is that it has an intrinsic accuracy even better than that of the circuit of the figure 1 , i.e., a dependence of its output voltage V REF to the lower process variations than in the example of the figure 1 , in particular because of the increase of the value of the output voltage V of the circuit 103.
  • N9 and N10 are N-channel MOS transistors.
  • a similar (complementary) circuit can be obtained by inverting the conductivity types of all the transistors.

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EP16200987.2A 2015-11-30 2016-11-28 Schaltkreis zur erzeugung einer referenzspannung Active EP3176669B1 (de)

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FR1561551 2015-11-30

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EP3176669B1 EP3176669B1 (de) 2019-01-09

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109698688A (zh) * 2017-10-20 2019-04-30 立积电子股份有限公司 反相器
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CN109698688B (zh) * 2017-10-20 2022-11-11 立积电子股份有限公司 反相器
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