EP2831919A4 - Integration of non-volatile charge trap memory devices and logic cmos devices - Google Patents

Integration of non-volatile charge trap memory devices and logic cmos devices

Info

Publication number
EP2831919A4
EP2831919A4 EP13769241.4A EP13769241A EP2831919A4 EP 2831919 A4 EP2831919 A4 EP 2831919A4 EP 13769241 A EP13769241 A EP 13769241A EP 2831919 A4 EP2831919 A4 EP 2831919A4
Authority
EP
European Patent Office
Prior art keywords
integration
devices
charge trap
trap memory
volatile charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13769241.4A
Other languages
German (de)
French (fr)
Other versions
EP2831919A1 (en
Inventor
Krishnaswamy Ramkumar
Fredrick Jenne
Sagy Levy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/436,878 external-priority patent/US8871595B2/en
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Priority to EP16188153.7A priority Critical patent/EP3229276A1/en
Publication of EP2831919A1 publication Critical patent/EP2831919A1/en
Publication of EP2831919A4 publication Critical patent/EP2831919A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40117Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923Programmable transistors with more than two possible different levels of programmation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0676Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
EP13769241.4A 2012-03-31 2013-03-18 Integration of non-volatile charge trap memory devices and logic cmos devices Withdrawn EP2831919A4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP16188153.7A EP3229276A1 (en) 2012-03-31 2013-03-18 Integration of non-volatile charge trap memory devices and logic cmos devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/436,878 US8871595B2 (en) 2007-05-25 2012-03-31 Integration of non-volatile charge trap memory devices and logic CMOS devices
PCT/US2013/032777 WO2013148393A1 (en) 2012-03-31 2013-03-18 Integration of non-volatile charge trap memory devices and logic cmos devices

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP16188153.7A Division EP3229276A1 (en) 2012-03-31 2013-03-18 Integration of non-volatile charge trap memory devices and logic cmos devices

Publications (2)

Publication Number Publication Date
EP2831919A1 EP2831919A1 (en) 2015-02-04
EP2831919A4 true EP2831919A4 (en) 2016-03-23

Family

ID=49261111

Family Applications (2)

Application Number Title Priority Date Filing Date
EP16188153.7A Pending EP3229276A1 (en) 2012-03-31 2013-03-18 Integration of non-volatile charge trap memory devices and logic cmos devices
EP13769241.4A Withdrawn EP2831919A4 (en) 2012-03-31 2013-03-18 Integration of non-volatile charge trap memory devices and logic cmos devices

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP16188153.7A Pending EP3229276A1 (en) 2012-03-31 2013-03-18 Integration of non-volatile charge trap memory devices and logic cmos devices

Country Status (6)

Country Link
EP (2) EP3229276A1 (en)
JP (1) JP6465791B2 (en)
KR (2) KR102256421B1 (en)
CN (1) CN104350603B (en)
TW (1) TWI582854B (en)
WO (1) WO2013148393A1 (en)

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* Cited by examiner, † Cited by third party
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US9218978B1 (en) * 2015-03-09 2015-12-22 Cypress Semiconductor Corporation Method of ONO stack formation
KR102394938B1 (en) * 2015-05-21 2022-05-09 삼성전자주식회사 Semiconductor devices and methods of manufacturing semiconductor devices
JP2017050537A (en) 2015-08-31 2017-03-09 株式会社半導体エネルギー研究所 Semiconductor device
CN106887409B (en) * 2015-12-15 2020-02-21 上海新昇半导体科技有限公司 Complementary nanowire semiconductor device and manufacturing method thereof
US9704995B1 (en) * 2016-09-20 2017-07-11 Advanced Micro Devices, Inc. Gate all around device architecture with local oxide
JP2017028307A (en) * 2016-10-05 2017-02-02 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method
US10468530B2 (en) * 2017-11-15 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with source/drain multi-layer structure and method for forming the same
US10699960B2 (en) * 2018-06-27 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for improving interlayer dielectric layer topography
CN109473341A (en) * 2018-11-16 2019-03-15 扬州扬杰电子科技股份有限公司 A kind of processing technology of low-angle oxide layer step
GB2591472B (en) 2020-01-28 2022-02-09 X Fab France Sas Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized mosfet and SONOS co-integration
CN112233974A (en) * 2020-10-26 2021-01-15 广州粤芯半导体技术有限公司 Method for preventing side erosion in wet etching and method for forming trench gate
CN112635487B (en) * 2020-12-17 2024-06-04 长江存储科技有限责任公司 Semiconductor device, method for manufacturing semiconductor device, mask plate system

Citations (2)

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US20060115978A1 (en) * 2004-11-30 2006-06-01 Michael Specht Charge-trapping memory cell and method for production
US20080293207A1 (en) * 2007-05-25 2008-11-27 Koutny Jr William W C Integration of non-volatile charge trap memory devices and logic cmos devices

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KR100881201B1 (en) * 2003-01-09 2009-02-05 삼성전자주식회사 Memory device having side gate and method of manufacturing the same
JP4242822B2 (en) * 2004-10-22 2009-03-25 パナソニック株式会社 Manufacturing method of semiconductor device
US7473589B2 (en) * 2005-12-09 2009-01-06 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
JP2006294756A (en) * 2005-04-07 2006-10-26 Canon Inc Method of manufacturing semiconductor device
US7514323B2 (en) * 2005-11-28 2009-04-07 International Business Machines Corporation Vertical SOI trench SONOS cell
US8772858B2 (en) * 2006-10-11 2014-07-08 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
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US20060115978A1 (en) * 2004-11-30 2006-06-01 Michael Specht Charge-trapping memory cell and method for production
US20080293207A1 (en) * 2007-05-25 2008-11-27 Koutny Jr William W C Integration of non-volatile charge trap memory devices and logic cmos devices

Non-Patent Citations (1)

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Title
See also references of WO2013148393A1 *

Also Published As

Publication number Publication date
TW201347048A (en) 2013-11-16
KR20200012038A (en) 2020-02-04
EP2831919A1 (en) 2015-02-04
KR20150011792A (en) 2015-02-02
JP2015516679A (en) 2015-06-11
TWI582854B (en) 2017-05-11
KR102256421B1 (en) 2021-05-26
WO2013148393A1 (en) 2013-10-03
CN104350603A (en) 2015-02-11
KR102072181B1 (en) 2020-03-02
JP6465791B2 (en) 2019-02-06
EP3229276A1 (en) 2017-10-11
CN104350603B (en) 2017-09-15

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