EP2159920B1 - Parallele Kodierung von Quasi-Zyklischen Kodes - Google Patents

Parallele Kodierung von Quasi-Zyklischen Kodes Download PDF

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EP2159920B1
EP2159920B1 EP09251850.5A EP09251850A EP2159920B1 EP 2159920 B1 EP2159920 B1 EP 2159920B1 EP 09251850 A EP09251850 A EP 09251850A EP 2159920 B1 EP2159920 B1 EP 2159920B1
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Prior art keywords
combinatorial
circuit
symbols
coefficients
generator polynomials
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EP2159920A2 (de
EP2159920A3 (de
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Hiroyuki Yamagishi
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Definitions

  • the present invention relates to a coding apparatus and method and, more particularly, to a coding apparatus and method that are configured to lower the processing load associated with coding and speed up the processing associated with coding.
  • the LDPC (Low Density Parity Check) code ( R. G. Gallager, "Low-density parity-check codes,” IRE Trans. Inform. Theory, vol. IT-8, pp. 21-28, Jan. 1962 .) has been receiving attention as an error correction code.
  • the LDPC code is advantageous in that code design is facilitated by providing a particular regularity to a parity check matrix of LDPC code and a circuit for coding and decoding by use of that regularity can be easily configured.
  • studies have been being made on many LDPC codes that uses the regularity having a cyclic structure. (For example, refer to Y. Kou, S. Lin, M. P. C.
  • Fossorier "Low-density parity-check codes based on finite geometries: a rediscovery and new results," IEEE Trans. Inform. Theory vol. 47, no. 7, pp. 2711-2736, Nov. 2001 . and M. Noda, "Designing a self-orthogonal quasi-cyclic code with extended minimum Hamming distance,” Proc. 4th Int. Sympo. Turbo Codes and Related Topics, Apr. 2006 .)
  • each sub matrix of 6-by-2 divided by lines is obtained by cyclically shifting down the immediately left-side sub matrix by one row. For example, "1 0" of row 1, column 1 and row 1, column 2 are shifted to row 2, column 3 and row 2, column 4 and "1 0" of row 2, column 1 and row 2, column 2 are shifted to row 3, column 3 and row 3, column 4.
  • the sub matrix on the immediately left side is cyclically shifted down by one row.
  • Non-Patent Document 4 shows a configuration of a coding circuit that sequentially outputs parities from a K-stage cyclic shift register and two or more XOR circuits connected thereto.
  • Japanese Patent No. 4045872 (herein after referred to as Patent Document 1) shows a method of the coding to systematic codes by repetitively using p generator polynomials as another coding method quasi-cyclic codes.
  • q j (x p ) is a polynomial of x p
  • FIG. 2 shows an exemplary configuration of a parity generating circuit that satisfies the above-mentioned two generator polynomials.
  • the parity generating circuit 10 shown in FIG. 2 has input terminals 11, 12, flip-flops 13 through 17, output terminals 18, 19, AND circuits 20, 21, and adders 22 through 24.
  • parity generating circuit 10 With the parity generating circuit 10 shown in FIG. 2 , information bits a 1 , a 3 , a 5 , 0, 0, 0 are sequentially entered at the input terminal 11 and information bits a 0 , a 2 , a 4 , a 6 , 0, 0 are entered at the input terminal 12. From the output terminal 18, parity bits r 0 , r 2 , r 4 are sequentially outputted and, from the output terminal 19, parity bits r 1 , r 3 are sequentially outputted.
  • the parity generating circuit 10 initializes all flip-flops 13 through 17 to zero.
  • the information bits are entered in units of two bits with 0 added by the number of parities, during which a control signal is kept at 1.
  • the parities are sequentially outputted to the flip-flops 13 through 17, with the control signal being 0.
  • the coefficient of the generator polynomial corresponds to the place of 1.
  • FIG. 3 schematically shows a parity generating circuit configured to execute parallel processing on a p symbol basis.
  • FIG. 3 also schematically shows the parity generating circuit 10 shown in FIG. 2 .
  • a parity generating circuit 50 shown in FIG. 3 is configured by an (N-K)-stage register 51 and a combinatorial circuit 52.
  • the combinatorial circuit 52 of the parity generating circuit 50 shown in FIG. 3 is configured to obtain coefficients of sequential q j (x p ) from upper p symbols of the (N-K)-stage register 51 and subtract a value obtained by multiplying these p coefficients by the generator polynomial from a register output and new p information symbols, thereby using a subtraction result for a next register input value.
  • the operation clock of the circuit may be increased as one means. However, it is systematically difficult to increase the operation clock higher than 400 MHz for example.
  • a configuration may be considered in which parallel processing is executed in units of symbols that is a multiple of p.
  • a coding circuit for executing parallel processing in units of 2p symbols can be realized by stacking two parity generating circuits that execute the processing on a p symbol unit as shown in FIG. 2 .
  • FIG. 4 shows a parity generating circuit 100 that executes, in units of 4 bits, parallel processing of the 2-stage of the combinatorial circuit in the parity generating circuit 10 shown in FIG. 2 .
  • the parity generating circuit 100 shown in FIG. 4 is configured by input terminals 101 through 104, flip-flops 105 through 109, output terminals 110 through 113, AND circuits 114 through 117, and adders 118 through 127.
  • parity bits a 3 , 0, 0 are sequentially entered at the input terminal 101
  • information bits a 0 , a 4 , 0 are sequentially entered at the input terminal 102
  • information bits a 1 , a 5 , 0 are sequentially entered at the input terminal 103
  • information bits a 2 , a 6 , 0 are sequentially entered at the input terminal 104.
  • Parity bits r 0 , r 4 are outputted from the output terminal 110
  • parity bit r 1 is outputted from the output terminal 111
  • parity bit r 2 is outputted from the output terminal 112
  • parity bit r 3 is outputted from the output terminal 113.
  • the parity generating circuit 100 initializes all flip-flops 105 through 109 to 0.
  • the information bits are entered in units of four bits with 0 added by the number of parities, during which a control signal is kept at 1.
  • the parities are sequentially outputted to the flip-flops 105 through 109, with the control signal being 0.
  • FIG. 5 schematically shows a parity generating circuit 150 that executes, in units of 2p symbols, parallel processing of the 2-stage of the combinatorial circuit 52 in the parity generating circuit 50 shown in FIG. 3 using p generator polynomials.
  • the parity generating circuit 150 shown in FIG. 5 is configured by an (N-K)-stage register 151, a combinatorial circuit 152, and a combinatorial circuit 153.
  • the two connected combinatorial circuits 152 and 153 are the same in configuration as the combinatorial circuit 52 shown in FIG. 3 .
  • the first-stage combinatorial circuit 152 obtains coefficients of sequential q j (x p ) from the upper p symbols of the (N-K)-stage register 151.
  • the second-stage combinatorial circuit 153 obtains coefficients of sequential q j (x p ) from the upper p symbols in the output from the first-stage combinatorial circuit 152.
  • an increase in coding speed may demand an increase in the operation clock of the circuit.
  • a method may be considered in which parallel processing is executed in units of symbols of a multiple of p (processing is executed as a configuration of multiple stages).
  • processing is executed as a configuration of multiple stages.
  • the processing of the succeeding stage is executed after the processing of the preceding stage, so that, as the number of stages increases, the resultant delays are accumulated, thereby making it difficult to speed up the processing.
  • the present embodiment addresses the above-identified and other problems associated with related-art methods and apparatuses and solves the addressed problems by providing a coding apparatus and method that are able to speed up the processing of coding.
  • a coding apparatus and coding method in coding a quasi-cyclic code in which a given code word cyclically shifted by p symbols provides another code word, parallel processing is executed in units of mp (a multiple of p), mp generator polynomials are used, generator polynomials g j (x) are selected such that a coefficient of degree deg(g i (x)) of x becomes zero for all g i (x) lower in degree than that, and circuits in which these generator polynomials g j (x) are combined are connected with each other.
  • coding in an (N, K) quasi-cyclic code is executed, coefficients of q j (x mp ) that is a polynomial of x mp are sequentially obtained from upper mp symbols of an (N-K)-stage register, a value obtained by multiplying these mp coefficients by a generator polynomial is subtracted from a value made up of a register output and new mp information symbols, a value generated as a result of the subtraction is used for a next register input value, and the coefficients of q j (x mp ) are supplied to the combinatorial circuits of a plurality of stages.
  • the speed of the processing associated with coding can be increased.
  • Embodiments of the present invention relate to a coding apparatus. Before describing the configuration of the coding apparatus associated with embodiments of the present invention, the coding associated with embodiments of the present invention will be described.
  • code polynomial c(x) may be expressed by equation (5) below by use of mp generator polynomials.
  • g j (x) is written as a generator polynomial.
  • the coding of a quasi-cyclic code can be executed by obtaining a parity polynomial satisfying equation (6) below.
  • g j (x) is selected such that the coefficient of degree deg(g i (x)) of x becomes 0 for all g i (x) having degrees lower than that.
  • These generator polynomials provide equation (7).
  • g 0 (x) of this generator polynomial does not include terms x 7 , x 6 , x 5 , g 3 (x) does not include terms x 6 , x 5 , and g 2 (x) does not include term x 5 .
  • a parity generating circuit as shown in FIG. 8 may be configured. Before describing this parity generating circuit, a method of selecting the above-mentioned four generator polynomials will be explained.
  • Executing a row basic deformation on the parity check matrix shown in FIG. 1 provides matrix H 1 shown in FIG. 6A .
  • Paying attention to this matrix H' indicates that the right-side partial matrix (the partial matrix to the right of the vertical line shown in FIG. 6A ) is a unit matrix.
  • executing deformation such as transposition for example on the partial matrix to the left of the vertical line shown in FIG. 6A provides matrix G such as shown in FIG. 6B .
  • Matrix G is generally called a generator matrix.
  • matrix G shown in FIG. 6B indicates that the partial matrix to the left side (the partial matrix to the left side of the vertical line shown in FIG. 6B ) is a unit matrix. From such matrix G, a generator polynomial can be selected. A relation between matrix G and generator polynomial is as shown in FIG. 7 . For the convenience of description, row numbers and column numbers are given to matrix G in FIG. 7 .
  • Each column is indicative of a degree configuring a generator polynomial.
  • each element of column 12 is equivalent to degree 0 (x 0 ) configuring the generator polynomial
  • each element of column 11 is equivalent to degree 1 (x 1 ) configuring the generator polynomial
  • each element of column 10 is equivalent to degree 2 (x 2 ) configuring the generator polynomial
  • ... and each element of column 4 is equivalent to degree 8 (x 8 ) configuring the generator polynomial.
  • generator polynomials can be selected from matrix G with parity check matrix deformed. Namely, in the selection of generator polynomials, g j (x) is selected such that the coefficient of degree deg(g j (x)) of x becomes zero for all g j (x) lower in degree than that.
  • making the partial matrix to the left of matrix G be a unit matrix can prevent the overlapped use of higher degrees (5 through 8) in each generator polynomial, thereby enabling to configure the parity generating circuit as shown in FIG. 8 , eventually speeding up the coding processing.
  • a parity generating circuit 200 shown in FIG. 8 is configured by input terminals 201 through 204, flip-flops 205 through 209, output terminals 210 through 213, AND circuits 214 through 217, and adders 218 through 228.
  • the parity generating circuit 200 initializes all flip-flops 205 through 209 to 0.
  • the information bits are entered in units of four bits with 0 added by the number of parities, during which a control signal is kept at 1.
  • the parities are sequentially outputted to the flip-flops 205 through 209, with the control signal being 0.
  • the coefficient of the generator polynomial corresponds to the place of 1. This is because, as described above with reference to FIG. 6 and FIG. 7 , the generator polynomials (7) were selected from matrix G.
  • parity bits a 3 , 0, 0 are sequentially entered at the input terminal 201
  • information bits a 0 , a 4 , 0 are sequentially entered at the input terminal 202
  • information bits a 1 , a 5 , 0 are sequentially entered at the input terminal 203
  • information bits a 2 , a 6 , 0 are sequentially entered at the input terminal 204.
  • Parity bits r 0 and r 4 are sequentially outputted from the output terminal 210
  • parity bits r 1 is outputted from the output terminal 211
  • parity bit r 2 is outputted from the output terminal 212
  • parity bit r 3 is outputted from the output terminal 213.
  • a connection relation of the parity generating circuit 200 shown in FIG. 8 is as follows.
  • the input terminal 201 supplies data to the adder 218.
  • Data from the AND circuit 217 is also supplied to the adder 218.
  • the adder 218 adds the data from the AND circuit 217 and the data from the input terminal 201 and outputs a result to the adder 220.
  • the data from the AND circuit 216 is also supplied to the adder 220.
  • the adder 220 adds the data from the AND circuit 216 and the data from the adder 218 and outputs a result to the adder 226.
  • the data from the AND circuit 214 is also supplied to the adder 226.
  • the adder 226 adds the data from the AND circuit 214 and the data from the adder 220 and supplies a result to the flip-flop 205.
  • the input terminal 202 supplies data to the adder 225.
  • the data from the AND circuit 215 is also supplied to the adder 225.
  • the adder 225 adds the data from the AND circuit 215 and the data from the input terminal 202 and outputs a result to the adder 227.
  • the data from the input circuit 214 is also supplied to the adder 227.
  • the adder 227 adds the data from the AND circuit 214 and the data from the adder 225 and supplies a result to the flip-flop 208.
  • the input terminal 203 supplies data to the adder 222.
  • the data from the AND circuit 216 is also supplied to the adder 222.
  • the adder 222 adds the data from the AND circuit 216 and the data from the input terminal 203 and outputs a result to the flip-flop 207.
  • the input terminal 204 supplies data to the adder 221.
  • the data from the AND circuit 216 is also supplied to the adder 221.
  • the adder 221 adds the data from the AND circuit 216 and the data from the input terminal 204 and supplies a result to the adder 224.
  • the data from the AND circuit 215 is also supplied to the adder 224.
  • the adder 224 adds the data from the AND circuit 215 and the data from the adder 221 and supplies a result to the flip-flop 206.
  • the output from the flip-flop 205 is entered in the adder 219.
  • the data from the AND circuit 217 is also supplied to the adder 219.
  • the adder 219 adds the data from the AND circuit 217 and the data from the flip-flop 205 and outputs a result to the adder 223.
  • the data from the adder 216 is also supplied to the adder 223.
  • the adder 223 adds the data from the AND circuit 216 and the data from the adder 219 and output a result to the adder 228.
  • the data from the AND circuit 214 is also supplied to the adder 228.
  • the adder 228 adds the data from the AND circuit 214 and the data from the adder 223 and outputs a result to the flip-flop 209.
  • the output from the flip-flop 209 is outputted as a parity bit and supplied to the AND circuit 217.
  • the output from the flip-flop 208 is outputted as a parity bit and supplied to the AND circuit 216.
  • the output from the flip-flop 207 is outputted as a parity bit and supplied to the AND circuit 215.
  • the output from the flip-flop 206 is outputted as a parity bit and supplied to the AND circuit 214.
  • a control signal is supplied to the AND circuits 214 through 217, which output data with predetermined timings corresponding to the control signal. Namely, the AND circuit 214 outputs data to the adders 226 through 228, the AND circuit 215 output data to the adder 224 and the adder 225, the AND circuit 216 outputs data to the adders 220 through 223, and the AND circuit 217 outputs data to the adder 218 and the adder 219.
  • the above-mentioned novel configuration allows the reduction in delay. This will be described again with reference to FIG. 8 .
  • the portions enclosed by dashed lines are indicative of portions in which operations are executed on generator polynomials.
  • the portions enclosed by dashed lines are denoted by a first stage, a second stage, a third stage, and a fourth stage from top to down in FIG. 8 .
  • the first stage corresponds to an operation of generator polynomial g 0 (x)
  • the second stage corresponds to an operation of generator polynomial g 3 (x)
  • the third stage corresponds to an operation of generator polynomial g 2 (x)
  • the fourth stage corresponds to an operation of generator polynomial g 1 (x).
  • the parity generating circuit 200 shown in FIG. 8 is configured to be able to simultaneously get the outputs from the AND circuits 214 through 217 necessary for the computation of the generator polynomial of each stage. Consequently, the above-mentioned novel configuration allows the realization of parity generation with the delay time minimized.
  • FIG. 9 schematically shows a parity generating circuit configured to execute parallel processing on a 2p symbol basis by use of 2p generator polynomials.
  • a parity generating circuit 250 shown in FIG. 9 is configured by an (N-K)-stage register 251, a combinatorial circuit 252, and a combinatorial circuit 253.
  • N-K the number of bits
  • combinatorial circuits 252 and the combinatorial circuit 253, each executing p operations is shown in the combinatorial circuit 252 and the combinatorial circuit 253, each executing p operations.
  • the combinatorial circuit 252 are entered with 2p symbols and the inputs from the (N-K)-stage register 251.
  • the combinatorial circuit 252 is also entered with the register output of the most significant p symbol from the (N-K)-stage register 251.
  • the combinatorial circuit 253 is entered with the output from the combinatorial circuit 252 and the register outputs of p symbols from the upper p + 1 symbol to the 2p symbol from the (N-K)-stage register 251.
  • the combinatorial circuit 252 obtains coefficients of sequential q j (x 2p ) from the upper p symbols of the (N-K)-stage register 251, subtracts a value obtained by multiplying these p coefficients by a generator polynomial from a value made up of register outputs and new 2p information symbols, and outputs a result to the combinatorial circuit 253.
  • the combinatorial circuit 253 obtains coefficients of sequential q j (x 2p ) from p symbols of the (N-K)-stage register 251 and subtracts a value obtained by multiplying these p coefficients by a generator polynomial from the output of the combinatorial circuit 252.
  • the coefficient for use in the multiplication with a generator polynomial in the combinatorial circuit 153 of the second stage in the related art is based on the operation result of the combinatorial circuit 152 of the first stage, the connection of the combinatorial circuits 152 and 153 resulted in a large delay.
  • all the coefficients for use in the multiplication with generator polynomials can be simultaneously obtained from the register output, leading to a significant advantage of largely reduced delays.
  • a coding circuit based on mp generator polynomials is configured when parallel processing is executed in units of mp (a multiple of p) symbols. Then, each generator polynomial g j (x) is selected such that the coefficient of degree deg(g j (x)) of x is made zero for all g j (x) lower in degree than that. This configuration reduces the circuit delay as compared with the connection of combinatorial circuits by p polynomials, thereby speeding up the coding processing.

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Claims (3)

  1. Codierungsvorrichtung, die mit quasizyklischen Codes umgeht, bei denen ein zyklisch um p Symbole verschobenes gegebenes Codewort ein anderes Codewort bereitstellt, wobei
    Parallelverarbeitung in Einheiten von mp Symbolen ausgeführt wird, wobei mp ein Vielfaches von p und m ≥ 2 ist;
    mp Generatorpolynome verwendet werden; und
    die Generatorpolynome gj(x) aus verschiedenen Zeilen einer Generatormatrix G ausgewählt werden, die in Standardform vorliegt und durch Deformation einer Paritätsprüfmatrix H für die quasizyklischen Codes erhalten wird, und die Codierungsvorrichtung m kombinatorische Schaltungen (252, 253) umfasst, in denen diese Generatorpolynome gj(x) mit gespeicherten Koeffizienten von qj(xmp) verknüpft werden, wobei qj(xmp) ein Polynom von xmp ist, wobei eine erste der m kombinatorischen Schaltungen ausgelegt ist zum sequentiellen Erhalten von p Koeffizienten von qj(xmp) aus oberen p Symbolen eines (N-K)-stufigen Registers (251),
    Multiplizieren der p Koeffizienten mit ersten p der mp Generatorpolynome,
    Erhalten eines Ausgangswerts durch Subtrahieren der Ergebnisse der Multiplikationen von einem Wert, der aus einer Registerausgabe und neuen mp Informationssymbolen besteht, und jede der anderen m-1 kombinatorischen Schaltungen ausgelegt ist zum
    sequentiellen Erhalten von p Koeffizienten von qj(xmp) aus p Symbolen des (N-K)-stufigen Registers (251),
    Multiplizieren der p Koeffizienten mit nächsten p der mp Generatorpolynome,
    Subtrahieren der Ergebnisse der Multiplikationen von dem von einer vorhergehenden der kombinatorischen Schaltungen empfangenen Ausgangswert und
    Ausgeben eines Ergebnisses der Subtraktion an eine nächste der kombinatorischen Schaltungen als den Ausgangswert, wenn die kombinatorische Schaltung nicht die m-te kombinatorische Schaltung ist, oder an das (N-K)-stufige Register (251) als einen nächsten Registereingangswert, wenn die kombinatorische Schaltung die m-te kombinatorische Schaltung ist.
  2. Codierungsvorrichtung nach Anspruch 1, wobei sich höchste Grade jedes der Generatorpolynome gj(x) in jedem der Generatorpolynome nicht überlappen.
  3. Codierungsverfahren für eine Codierungsvorrichtung, die mit quasizyklischen Codes umgeht, bei denen ein zyklisch um p Symbole verschobenes gegebenes Codewort ein anderes Codewort bereitstellt, wobei
    Parallelverarbeitung in Einheiten von mp Symbolen ausgeführt wird, wobei mp ein Vielfaches von p und m ≥ 2 ist;
    mp Generatorpolynome verwendet werden; und
    die Generatorpolynome gj(x) aus verschiedenen Zeilen einer Generatormatrix G ausgewählt werden, die in Standardform vorliegt und durch Deformation einer Paritätsprüfmatrix H für die quasizyklischen Codes erhalten wird, und Codierung in m kombinatorischen Schaltungen (252, 253) der Codierungsvorrichtung, in denen diese Generatorpolynome gj(x) mit gespeicherten Koeffizienten von qj(xmp) verknüpft werden, wobei qj(xmp) ein Polynom von xmp ist, bei einer ersten der m kombinatorischen Schaltungen durchgeführt wird durch sequentielles Erhalten von p Koeffizienten von qj(xmp) aus oberen p Symbolen eines (N-K)-stufigen Registers (251),
    Multiplizieren der p Koeffizienten mit ersten p der mp Generatorpolynome,
    Erhalten eines Ausgangswert durch Subtrahieren der Ergebnisse der Multiplikationen von einem Wert, der aus einer Registerausgabe und neuen mp Informationssymbolen besteht, und bei jeder der anderen m-1 kombinatorischen Schaltungen durch
    sequentielles Erhalten von p Koeffizienten von qj(xmp) aus p Symbolen des (N-K)-stufigen Registers (251),
    Multiplizieren der p Koeffizienten mit nächsten p der mp Generatorpolynome,
    Subtrahieren der Ergebnisse der Multiplikationen von dem von einer vorhergehenden der kombinatorischen Schaltungen empfangenen Ausgangswert und
    Ausgeben eines Ergebnisses der Subtraktion an eine nächste der kombinatorischen Schaltungen als den Ausgangswert, wenn die kombinatorische Schaltung nicht die m-te kombinatorische Schaltung ist, oder an das (N-K)-stufige Register (251) als einen nächsten Registereingangswert, wenn die kombinatorische Schaltung die m-te kombinatorische Schaltung ist.
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Family Cites Families (17)

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Publication number Priority date Publication date Assignee Title
JPS63265363A (ja) 1987-04-23 1988-11-01 Hitachi Ltd 現金自動取引装置
JPH0445872A (ja) 1990-06-14 1992-02-14 Ichikoh Ind Ltd 熱硬化性樹脂の表面処理方法
IL101071A (en) * 1992-02-26 1997-09-30 Naan Irrigation Systems Drip irrigation apparatus
US5822336A (en) * 1996-11-14 1998-10-13 Quantum Corporation Modified reed solomon code selection and encoding system
US6058500A (en) * 1998-01-20 2000-05-02 3Com Corporation High-speed syndrome calculation
US7711763B2 (en) * 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
JP4045872B2 (ja) * 2001-07-18 2008-02-13 ソニー株式会社 符号化方法および符号化装置
US6978415B1 (en) * 2001-11-27 2005-12-20 Maxtor Corporation Variable redundancy cyclic code encoders
US7020826B2 (en) * 2002-01-23 2006-03-28 Thomson Licensing Intra-decoder component block messaging
CN100392986C (zh) * 2003-12-15 2008-06-04 联发科技股份有限公司 交叉循环码的编码方法与装置
JP4534128B2 (ja) * 2004-03-05 2010-09-01 ソニー株式会社 符号化方法および装置
JP2005340920A (ja) * 2004-05-24 2005-12-08 Samsung Yokohama Research Institute Co Ltd 信号処理装置、符号化方法および復号方法
US7617439B2 (en) * 2005-01-10 2009-11-10 Broadcom Corporation Algebraic construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices
JP4177824B2 (ja) * 2005-03-16 2008-11-05 株式会社東芝 符号化方法、復号化方法および符号化システム
US7617442B2 (en) * 2005-07-18 2009-11-10 Broadcom Corporation Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices
JP4856605B2 (ja) * 2006-08-31 2012-01-18 パナソニック株式会社 符号化方法、符号化装置、及び送信装置
JP4860644B2 (ja) 2007-02-09 2012-01-25 株式会社クラレ プラスチックレンズ

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JP4780158B2 (ja) 2011-09-28
US20100058150A1 (en) 2010-03-04
CN101662291A (zh) 2010-03-03
EP2159920A3 (de) 2010-06-02

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