EP2075909A2

EP2075909A2 - Current sampling method and circuit

Info

Publication number: EP2075909A2
Application number: EP08164529A
Authority: EP
Inventors: Nicola Bramante; Martin John Edwards; John Richard Ayres
Original assignee: TPO Displays Corp
Current assignee: TPO Displays Corp
Priority date: 2007-12-26
Filing date: 2008-09-17
Publication date: 2009-07-01
Also published as: EP2075909A3; US20090167364A1; TWI380031B; JP5175168B2; CN101470138B; CN101470138A; TW200928379A; JP2009159610A; US7791380B2

Abstract

In one example, a current sampling circuit comprises a current sampling transistor, a capacitor arrangement between the gate and source of the current sampling transistor and an amplifier provided in a feedback loop between the gate and source of the current sampling transistor. A switch controls the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement. The capacitor arrangement comprises a first capacitor circuit for sampling a gate source voltage in a first sampling phase and a second capacitor circuit, with the first and second capacitor circuits arranged for together sampling the gate source voltage in a second sampling phase. The operating point of the amplifier is shifted between the first and second phases based on the gate source voltage sampled in the first sampling phase.

This arrangement provides a coarse sampling phase, which is used to change the operating conditions of an amplifier used within the circuit. This means the amplifier can operate more efficiently in a subsequent fine tuning sampling phase.

Description

This invention relates to current sampling methods and circuits, particularly but not exclusively for capturing output signals from sensors which have a current output.
In a number of sensing applications, the sensing devices (for example diodes or transistors) generate an output current which depends on the parameter to be sensed. The range of applications in which current sensors can be used is enormous, and this invention can be applied to any such application. For example, the parameter to be sensed can be a light level in the case of a photosensor or a temperature in the case of a temperature sensor. The sensor will measure a physical property such as light, temperature, strain or other forces.
The output current of a sensor will often be very small, and it is advantageous to convert the signal to a more robust form close to the sensor in order to preserve the quality of the signal, particularly the signal to noise ratio. Sampling of the current is required in the case where the signal changes over time or when the output of several sensors is multiplexed together as is the case for an array of sensors.
Conventional current sampling circuits can be slow to acquire new signals, particularly when the currents are small.
Figure 1 shows a known simple sampling circuit.
The current to be sampled may for example comprise a photocurrent, and is represented by a current source 10. The current is drawn through a p-type drive transistor T1p, which has a capacitor C1 connected between its source and gate. This capacitor can thus store the gate-source voltage corresponding to the current being sampled.
The circuit has a first switch S1 (with timing clk1) between the gate and drain of the transistor T1p for turning the transistor on so that it can supply the current being sampled. A second switch S2 (with timing clk2) couples the sampling transistor to the sensor, and a third switch S3 (with timing clk3) couples the sampling transistor to the output of the sampling circuit.
As shown in Figure 2, during a sampling phase S the switches S1 and S2 are closed and the switch S3 is open. The current to be sampled, the photocurrent in this example, is drawn through the transistor T1p. The voltage present on the gate and the drain of T1p settles at a value which produces a drain current in T1p which is equal to the photocurrent. This voltage becomes stored across the capacitor C1. During a holding phase H the switches S1 and S2 are opened and the switch S3 is closed. The gate-source voltage of T1p is maintained by C1 and therefore the sampled photocurrent is available at the output of the circuit.
The time required to sample the current is proportional to (C1+Cd)/gm1 where Cd is the capacitance of the sensor (i.e. the photodiode) and gm1 is the transconductance of the transistor T1p. When the current to be measured is small, the transistor T1p will be operating in the sub-threshold region. In this region, the value of gm1 is proportional to the drain current Id1. Therefore when the current to be sampled is low the settling time is extended.
The settling time can be reduced using the circuit shown in Figure 3.
The p-type transistor T1p is replaced by an n-type transistor T1n and an inverting amplifier 20 is connected between the source of the transistor T1n and the gate. The storage capacitor C1 is again between the source and gate, as the n-type transistor has its drain connected to the high voltage line VDD. With this arrangement, the settling time is now proportional to (C1+Cd)/(A·gm1), where A is the gain of the inverting amplifier 20. This reduces the settling time of the circuit by increasing the effective value of the transconductance of T1n.
A switch S4 (with timing clk4) opens or closes the amplifier feedback loop, and a switch S5 (with timing clk5) can reset the amplifier.
As shown in Figure 4, during the sampling phase S the switches S2 and S4 are closed, while the S3 and S5 are open, so that the gate of T1 sees an amplified version of the voltage at its source. The gate source voltage Vgs of T1n required to produce a drain current equal to the photocurrent gets stored across C1. During the holding phase H the switches S4 and S2 are open, whereas S3 and S5 are closed. T1n provides the sampled current as output of the circuit. The amplifier sits around its threshold with its input and output connected together, thus ensuring that the voltage node associated with the sensor (in this example the cathode of the photodiode) is kept fairly constant.
The capacitor C1 in Figure 3 is connected between the input and the output of the inverting amplifier 20 during the sampling phase S. Due to the Miller effect, the effective value of C1 is increased, since the inverting amplifier 20 sees an equivalent capacitance A.C1 between its input and ground. This equivalent capacitor is in parallel with Cd and tends to make the circuit slow.
The circuit in Figure 3 is also limited by the current that needs to be sampled. That current fixes a gate source voltage for T1n that needs to be built up on the storage capacitor C1. When sampling for example 350pA, the gate source voltage needed is approximately 700mV, which corresponds to a particular operating point of the inverting amplifier.
Figure 5 shows a plot of the gain of an inverting amplifier as a function of Vout-Vin, which in the sampling phase is the gate source voltage of T1n. It can be seen that the operating point of the inverting amplifier, set by the gate source voltage of T1n, will be different from the voltage at which the gain is maximum (in absolute value). In other words, the amplifier 20 is not biased to its optimum operating point. This shows a fundamental limitation of the approach shown in Figure 3.
According to the invention, there is provided a current sampling circuit, comprising:

a current sampling transistor;
a capacitor arrangement between the gate and source of the current sampling transistor, for storing a gate-source voltage corresponding to a current being sampled;
an amplifier provided in a feedback loop between the gate and source of the current sampling transistor; and
a switch arrangement for controlling the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement,

This arrangement provides a coarse sampling phase, which is used to change the operating conditions of an amplifier used within the circuit, in particular by changing the desired voltage at the output. This means the amplifier can operate more efficiently in a subsequent fine tuning sampling phase.
The switch arrangement can comprise a switch for selecting if the first capacitor circuit is connected between the source and gate of the current sampling transistor for the first phase, or if the first and second capacitor circuits are between the source and gate of the current sampling transistor for the second phase. Thus, each phase uses a different circuit configuration in respect of the capacitors of the capacitor arrangement.
The switch arrangement can comprise a first amplifier output switch for connecting the output of the amplifier to the gate of the current sampling transistor for the first phase and a second amplifier output switch for connecting the output of the amplifier to the junction between the first and second capacitor circuits in the second phase. In this way, the desired voltage at the amplifier output can be changed to change the amplifier operating conditions.
A reset phase is preferably provided between the first and second phases in which the amplifier input and output are connected together.
One of the first and second capacitor circuits can comprise a first and second capacitor in series. By connecting a junction between the first and second capacitors to a reference potential during a sampling phase, the Miller effect explained above can be avoided.
The invention also provides a current sampling circuit, comprising:

This circuit overcomes the Miller effect.
The current sampling circuit of the invention can be used as part of a sensor circuit, in which a sensor has a current output which is the current to be sampled.
The invention also provides a current sampling method, comprising:

in a first sampling phase:
- amplifying a source voltage of a current sampling transistor using an amplifier and providing the amplified voltage to the gate; and
- sampling the gate source voltage corresponding to a current being sampled onto a first capacitor circuit;
using the sampled gate source voltage to shift the operating point of the amplifier; and
in a second sampling phase:
- amplifying a source voltage of the current sampling transistor using an amplifier and providing the amplified voltage to the gate; and
- sampling the gate source voltage corresponding to a current being sampled onto a capacitor arrangement comprising the first capacitor circuit and a second capacitor circuit.

The invention also provides a current sampling method, comprising:

in a sample phase:
- amplifying a source voltage of a current sampling transistor using an amplifier and providing the amplified voltage to the gate; and
- sampling the gate source voltage corresponding to a current being sampled onto a capacitor circuit which comprises a first and second capacitor in series, wherein during the sampling, a junction between the first and second capacitors is connected to a reference potential; and
in a hold phase, providing the sampled current as an output, and isolating the junction between the first and second capacitors from the reference potential.

These methods correspond to the use of the circuits of the invention. The sampling methods can be used as part of a signal sensing method, in which a sensor is used to perform a sensing function, thereby generating a current output which is sampled by the sampling methods of the invention.
The invention thus provides circuits and methods in which provide two approaches. The first is a way of eliminating the Miller effect, present during the sampling phase. This method is based on splitting the capacitance being increased by the Miller effect into two series capacitors and on connecting their common terminal to a reference potential, such as ground.
The second is a two step sampling approach. In a first sampling phase, a coarse gate source voltage value is stored across a capacitor and is used to shift the operating point of the inverting amplifier in a second sampling phase. In this way, during the second sampling phase the inverting amplifier will operate around its high gain region, thus giving shorter sampling times and good immunity to changes of transistor characteristics. The two approaches can be combined in one circuit/method.
Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

Figure 1 shows a first known current sampling circuit;
Figure 2 is a timing diagram for the circuit of Figure 1;
Figure 3 shows a second known current sampling circuit;
Figure 4 is a timing diagram for the circuit of Figure 3;
Figure 5 is a graph used to explain how the operating point of an amplifier influences performance;
Figure 6 shows a first example of current sampling circuit of the invention with associated timing diagram;
Figure 7 shows a second example of current sampling circuit of the invention with associated timing diagram; and
Figure 8 shows a third example of current sampling circuit of the invention with associated timing diagram.

The same reference numerals have been used in different figures where the components perform the same function as in other figures. Description of the function of each component is therefore not repeated.
The invention provides solutions to the two problems outlined above, namely the Miller effect capacitance issue and the amplifier operating point issue. Sensor circuits are described below which address these issues individually, and a circuit is described with addresses both issues.
The circuit and associated timing diagram of Figure 6 addresses the Miller effect issue. In particular, the settling time of the circuit in Figure 3 can be decreased with the circuit in Figure 6, in which the capacitance C1 being increased by the Miller effect is split into two capacitors C1 a, C1 b. The circuit includes a switch S4' for connecting a junction between the first and second capacitors C1a,C1b to a reference potential VSS1. The switch S4' is clocked with the same signal as the switch S4. Thus, during the sampling phase S, with the amplifier connected in a feedback loop, the junction is held at a fixed potential.
In this way, the Miller effect is eliminated and the settling time of the circuit is improved. During the sampling phase, both C1 a and C1b have one terminal connected to the fixed potential (e.g. ground) so that C1 a is seen as a capacitor driven by the output of the inverting amplifier whereas C1 b is seen as the input capacitance of the inverting amplifier.
During the holding phase H, C1a and C1b are connected in series, so that the sum of the voltage stored across C1a and the voltage stored across C1 b forms the gate source voltage necessary for T1n to provide the sampled current.
In the circuit in Figure 6, particular care must be taken for the rate at which the current to be sampled changes. If the current changes very rapidly, the sampled current may go well below the target current and then take time to recover, which will make the circuit intrinsically slow.
The circuit and associated timing diagram of Figure 7 addresses the amplifier operating point issue, and implements a double sampling method.
The timeline is divided into a first sampling phase Sa, a reset phase R1, a second sampling phase Sb and a holding phase H.
The circuit has a series capacitor arrangement C1,C2 between the gate and source of the current sampling transistor T1n, for storing the gate-source voltage corresponding to a current being sampled. The circuit is controlled to sample the gate-source voltage corresponding to the current being sampled on to the first capacitor C1 in the first sampling phase Sa, and is controlled to sample the gate-source voltage onto the first and second capacitors in series in the second sampling phase Sb.
The first sampling phase can be considered as a coarse sampling phase, and it is used primarily to set the operating point of the amplifier 20 for the second, fine sampling phase.
A switch S6 (with timing clk6) determines whether the first capacitor C1 is connected between the source and gate of the current sampling transistor (for the first phase), or if the first and second capacitors C1, C2 are connected in series between the source and gate of the current sampling transistor T1n (for the second phase).
The output of the amplifier 20 is connected either to the gate by means of a first amplifier output switch S4 (with timing clk4) for the first phase, or to the junction between the first and second capacitors C1,C2 by means of a second amplifier output switch S7 (with timing clk7) for the second phase. In this way, a voltage on the capacitor C1 is used to define the operating point of the amplifier.
During the first sampling phase Sa, the switches S2, S4 and S6 are closed, while the switches S3, S5, S7 are open. Capacitor C2 is then shorted, while the coarse value of Vgs that T1n needs in order to provide the current to be sampled is built up across C1.
During a reset phase R1, a switch S5 (with timing clk5) is closed. This connects the amplifier input and output together, and the switch S4 is open, so that the amplifier is reset, and not providing a feedback function.
During this reset phase, the inverter amplifier 20 is biased around its threshold, and also the source of T1n is then taken to the amplifier threshold. The gate of T1n will follow this change in the source voltage, since one terminal of the source-gate capacitor C1 is at high impedance. C2 is kept shorted, with the threshold voltage of the inverting amplifier at both its terminals.
During the second sampling phase Sb, the switches S6 and S5 are open, while the switch S7 is closed. The amplifier output is connected to the junction between the capacitors, and both capacitors are between the gate and source of the transsitor.
During this phase, the capacitor C1 keeps the coarse gate source voltage value Vgs stored from the first sampling phase Sa, while the correction needed to achieve the correct gate source voltage of T1 n is built across C2.
The operating point of the inverting amplifier has thus been shifted towards the high gain region by using the coarse voltage across C1.
The reset phase R1 is needed in order to avoid spikes in the drain current of T1n at the beginning of the second sampling phase Sb. This can happen because, as soon as the switch S7 closes, one terminal of C1 will see the amplified version of the source voltage of T1n, that will get coupled into the gate of T1n through C1, thus causing an initial extra current.
Phase R1 then ensures, through the reset of the inverting amplifier, that the correct voltages are set up at the terminals of C1 and C2.
During the holding phase H, the switches S3 and S5 close, while the switches S2 and S7 open. Capacitors C1 and C2 are then connected in series, so the sum of the voltages across each of them, i.e. the sum of the coarse value and the fine correction, forms the final gate source voltage of T1n necessary to provide the correct sampled current at the output of the circuit.
The double sampling circuit in Figure 7 is quite independent on the rate at which the current to be sampled changes.
Figure 8 shows an improved version of the circuit in Figure 7. In this circuit, the sampling time is decreased even more by splitting the capacitance associated with the Miller effect (C2 in Figure 7), as explained above in connection with Figure 6 for the single sampling case.
The circuit of Figure 8 includes two precharge transistors P1, P2. Apart from these, the circuit differs from the circuit of Figure 7 only in that the capacitor C2 is replaced by two series capacitors C2a,C2b with their junction connected to a fixed potential through a switch s8 (with timing clk8).
The switch S8 is closed during the two sample phases Sa, Sb and the reset phase R1, and then is opened during the holding phase.
In the circuit in Figure 8, a precharge phase is used, by means of the transistors P1, P2.
A first precharge transistor P1 is connected between the transistor gate and the high power line VDD and a second precharge transistor P2 is connected between the transistor drain and the high power line. These act as switches, controlled by lines clk9 and clk10.
In the precharge phase, P1 turns on and P2 turns off and the switches S2, S6, S8 are closed. P1 brings the gate of T1n up to the high voltage rail VDD, and the source of T1n is taken at the threshold of the inverting amplifier biases, so that C1, C2a and C2b have roughly VDD/2 across them.
P2 isolates T1 n from VDD so that no extra current flows across T1 n. This phase ensures that during the next first sampling phase Sa the initial current through T1n, given by the voltage stored across C1 during the precharge time, is high compared to the photocurrent to be sampled. Under this condition, the circuit responds more quickly to the changes in photocurrent, thus giving fast sampling times. During all other phases (Sa, R1, Sb and H), P1 is off and P2 is on so that the connection to the power line VDD is functionally the same as in all the other circuits described.
This circuit is of particular interest in sensor applications, especially when sensing small currents related to e.g. light intensity, temperature or degree of DNA hybridization, that can change in time.
The invention can be used in display devices for processing light sensor signals. Light sensing can be used to control a display automatically in dependence on the ambient light level, and such control schemes are known.
The circuits shown are only some examples. The switches shown in the circuits can of course be implemented with transistors, and if the current sampling circuit is to be integrated onto the substrate of another device (such as a display), the same technology devices will be used for the switches as for the other circuit elements on the substrate. The implementation of the circuits shown will therefore be routine to those skilled in the art.
Various modifications will be apparent to those skilled in the art.

Claims

A current sampling circuit, comprising:
a current sampling transistor (T1n);

a capacitor arrangement (C1,C2) between the gate and source of the current sampling transistor (T1n), for storing a gate-source voltage corresponding to a current being sampled;

an amplifier (20) provided in a feedback loop between the gate and source of the current sampling transistor (T1n); and

a switch arrangement (Sn) for controlling the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement (C1,C2),
wherein the capacitor arrangement comprises a first capacitor circuit (C1) for sampling a gate source voltage in a first sampling phase (Sa) and a second capacitor circuit (C2), with the first and second capacitor circuits being arranged for together sampling the gate source voltage in a second sampling phase (Sb),
and wherein the switch arrangement is operable to shift the operating point of the amplifier between the first and second phases based on the gate source voltage sampled in the first sampling phase.
A circuit as claimed in claim 1, wherein the switch arrangement comprises a switch (S6) for selecting if the first capacitor circuit (C1) is connected between the source and gate of the current sampling transistor for the first phase, or if the first and second capacitor circuits (C1,C2) are connected between the source and gate of the current sampling transistor (T1n) for the second phase.
A circuit as claimed in claim 1 or 2, wherein the switch arrangement comprises a first amplifier output switch (S4) for connecting the output of the amplifier (20) to the gate of the current sampling transistor (T1n) for the first phase and a second amplifier output switch (S7) for connecting the output of the amplifier (20) to the junction between the first and second capacitor circuits (C1,C2) in the second phase.
A circuit as claimed in any preceding claim, wherein the switch arrangement is operable to provide a reset phase between the first and second phases (Sa, Sb) in which the amplifier input and output are connected together.
A circuit as claimed in any preceding claim, wherein the switch arrangement comprises a sampling switch (S2) for connecting the current sampling transistor to a source of current, and an output switch (S3) for connecting the current sampling transistor to an output of the circuit.
A circuit as claimed in any preceding claim, wherein one (C2) of the fist and second capacitor circuits comprises a first and second capacitor in series (C2a,C2b), wherein the switching arrangement comprises a switch (S8) for connecting a junction between the first and second capacitors (C2a,C2b) to a reference potential.
A current sampling circuit, comprising:
a current sampling transistor (T1n);

a capacitor arrangement (C1,C2) between the gate and source of the current sampling transistor (T1n), for storing a gate-source voltage corresponding to a current being sampled;

an amplifier (20) provided in a feedback loop between the gate and source of the current sampling transistor (T1n); and

a switch arrangement (Sn) for controlling the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement (C1,C2),
wherein the capacitor arrangement comprises a first and second capacitor in series (C1a,C1b; C2a,C2b), and wherein the switching arrangement comprises a switch (S8) for connecting a junction between the first and second capacitors (C1 a,C1 b, C2a,C2b) to a reference potential.
A sensor circuit, comprising:
a current sampling circuit as claimed in any preceding claim; and

a sensor having a current output which is the current to be sampled.
A current sampling method, comprising:
in a first sampling (Sa) phase:
amplifying a source voltage of a current sampling transistor (T1n) using an amplifier and providing the amplified voltage to the gate; and

sampling the gate source voltage corresponding to a current being sampled onto a first capacitor circuit (C1);

using the sampled gate source voltage to shift the operating point of the amplifier; and

in a second sampling phase (Sb):
amplifying a source voltage of the current sampling transistor (T1n) using an amplifier and providing the amplified voltage to the gate; and

sampling the gate source voltage corresponding to a current being sampled onto a capacitor arrangement comprising the first capacitor circuit (C1) and a second capacitor circuit (C2).
A method as claimed in claim 9, comprising:
in the first sampling phase (Sa) connecting the first capacitor circuit (C1) between the source and gate of the current sampling transistor (T1n); and

in the second sampling phase (Sb) connecting the first and second capacitor circuits (C1,C2) between the source and gate of the current sampling transistor (T1n).
A method as claimed in claim 9 or 10, comprising:
in the first sampling phase (Sa) connecting the output of the amplifier (20) to the gate of the current sampling transistor (T1n); and

in the second sampling phase (Sb) connecting the output of the amplifier (20) to the junction between the first and second capacitor circuits (C1,C2).
A method as claimed in any one of claims 9to 11, further comprising providing a reset phase between the first and second phases (Sa, Sb) in which the amplifier input and output are connected together.
A method as claimed in any one of claims 9 to 12, comprising connecting the current sampling transistor to a source of current during a sampling phase and to an output of the circuit during a hold phase, wherein one (C2) of the fist and second capacitor circuits comprises a first and second capacitor in series (C2a,C2b), and wherein the method further comprises connecting the junction between the first and second capacitors (C2a,C2b) to a reference potential during the sampling phase.
A current sampling method, comprising:
in a sample phase:
amplifying a source voltage of a current sampling transistor (T1n) using an amplifier and providing the amplified voltage to the gate; and

sampling the gate source voltage corresponding to a current being sampled onto a capacitor circuit (C1) which comprises a first and second capacitor in series (C1a,C1b; C2a,C2b), wherein during the sampling, a junction between the first and second capacitors (C1a,C1b, C2a,C2b) is connected to a reference potential; and

in a hold phase, providing the sampled current as an output, and isolating the junction between the first and second capacitors (C1a,C1b, C2a,C2b) from the reference potential.
A signal sensing method, comprising:
using a sensor to perform a sensing function, thereby generating a current output;

using the method of any one of claims 9 to 14 to sample the current output and provide it at as output.