CN102650892B - Reference voltage stabilising arrangement and relevant voltage stabilizing method - Google Patents
Reference voltage stabilising arrangement and relevant voltage stabilizing method Download PDFInfo
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- CN102650892B CN102650892B CN201110460675.0A CN201110460675A CN102650892B CN 102650892 B CN102650892 B CN 102650892B CN 201110460675 A CN201110460675 A CN 201110460675A CN 102650892 B CN102650892 B CN 102650892B
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Abstract
The present invention proposes reference voltage stabilising arrangement and relevant voltage stabilizing method, one of this reference voltage stabilising arrangement includes input end, in order to receive reference voltage; Output terminal, in order to be coupled to load; Voltage buffer, is coupled between input end and output terminal; Charge storage device, is coupled to output terminal; And charge-discharge circuit, be coupled to charge storage device.Charge-discharge circuit can carry out charge or discharge to charge storage device, and the charge storage device after voltage buffer and charge or discharge can, to load supplying, make the voltage of load end through equaling reference voltage after a period of time.
Description
Technical field
The present invention relates to a kind of voltage stabilizing device.
Background technology
In circuit design, often need stable reference voltage to be provided to each circuit blocks, to enable each circuit blocks normal operation.Circuit blocks can include active member and/or passive device, when reference voltage is coupled to circuit blocks, circuit blocks may be drawn electric current or output current and causes the shake of reference voltage (or to be called surging in self-reference voltage place, glitch), therefore, circuit blocks needs to wait for a period of time, and could carry out follow-up running, and limit the operation rate of circuit blocks to reference voltage after stablizing according to reference voltage.So-called stable, refer to that reference voltage has been applicable to allowing circuit blocks operate in order to reference.
Therefore; in order to reduce the impact of surging; implementation often can be coupled to voltage buffer (voltagebuffer) with reference to voltage; voltage buffer by comparatively high driving ability (drivingcapability) carrys out driving circuit block, and provides stable reference voltage to circuit blocks (hereinafter referred to as load).Such as, in circuit design, adopt the voltage buffer that the modes such as the amplifier of unity gain (unitygainamplifier) are implemented.
But, when the resistance value of load become large or in order to drive the time of load to reduce time, voltage buffer to provide stable reference voltage to load within the time of presetting, then must improve the frequency range of voltage buffer, reduces the output impedance of voltage buffer and/or dynamically change the output current of voltage buffer.Therefore, the circuit area of voltage buffer and power consumption all significantly can rise with nearly square speed doubly, and cause the waste of hardware cost and the energy.
Summary of the invention
In view of this, how to reduce the impact of surging, and allow reference voltage can be provided to load rapidly with reference to voltage by stabilization energy fast, and reduce energy resource consumption, in fact for industry has problem to be solved.
Present description provides a kind of reference voltage stabilising arrangement, it includes: an input end, in order to receive a reference voltage; One output terminal, in order to be coupled to a load; One voltage buffer, is coupled between this input end and this output terminal; One charge storage device, is coupled to this output terminal; And a charge-discharge circuit, be coupled to this charge storage circuit; Wherein this charge-discharge circuit can carry out charge or discharge to this charge storage device, and this charge storage device after this voltage buffer and charge or discharge can, to this load supplying, make the voltage of this load end through equaling this reference voltage after a period of time.
This instructions also provides a kind of reference voltage antihunt means, and it includes: utilize a voltage buffer to receive a reference voltage; Charge or discharge are carried out to a charge storage device; And utilize this charge storage device after this voltage buffer and charge or discharge to a load supplying, make the voltage of this load end through equaling this reference voltage after a period of time.
This instructions also provides a kind of reference voltage stabilising arrangement, and it includes: a first input end, in order to receive one first reference voltage, one second input end, in order to receive one second reference voltage, one first output terminal and one second output terminal, one first voltage buffer, is coupled between this first input end and this first output terminal, one second voltage buffer, is coupled between this second input end and this second output terminal, one first charge storage device, is coupled to this first output terminal, one second charge storage device, is coupled to this second output terminal, one charging circuit, is coupled to this first charge storage circuit, and a discharge circuit, be coupled to this second charge storage circuit, wherein this charging circuit can charge to this first charge storage device, and this discharge circuit can discharge to this second charge storage device, the first charge storage device after this first voltage buffer and this charging can provide one first output voltage in this first output terminal, and the second charge storage device after this second voltage buffer and this electric discharge can provide one second output voltage in this second output terminal, and the voltage difference between this first output voltage with this second output voltage can be equal through after a period of time with the voltage difference between this first reference voltage with this second reference voltage.
One of advantage of above-mentioned reference voltage stabilising arrangement is the hsrdware requirements that can reduce voltage buffer, thus reduces hardware cost and the energy consumed.
Another advantage of above-mentioned reference voltage stabilising arrangement to reduce the impact of surging, and allow and be provided to load with reference to voltage rapidly with reference to electricity is stable fast, and can be applicable to the system application of various high speed.
Accompanying drawing explanation
Fig. 1 is the functional block diagram after the reference voltage stabilising arrangement of one embodiment of the invention simplifies.
Process flow diagram after embodiment when Fig. 2 is the reference voltage stabilising arrangement running of Fig. 1 simplifies.
Fig. 3 is the functional block diagram after the reference voltage stabilising arrangement of another embodiment of the present invention simplifies.
Symbol description
100 reference voltage stabilising arrangement 110 voltage buffers
120 charge storage device 130 charge-discharge circuits
140 control circuit 150,160 switches
170 input end 180 output terminals
300 reference voltage stabilising arrangement 310,311 voltage buffers
320,321 charge storage device 330 charging circuits
331 discharge circuit 340 control circuits
350,351,360,361 switch 370,371 input ends
380,381 output terminals
Embodiment
Below cooperation correlative type is illustrated embodiments of the invention.In these are graphic, identical label represents same or similar element or process step.
Fig. 1 is the functional block diagram after the reference voltage stabilising arrangement 100 of one of embodiments of the invention simplifies, and reference voltage stabilising arrangement 100 includes voltage buffer 110, charge storage device 120, charge-discharge circuit 130, control circuit 140, switch 150 and 160, input end 170 and output terminal 180.The voltage Vo of output terminal in order to receive reference voltage Vref, and can be provided to load by reference voltage stabilising arrangement 100, receives the output voltage Vo identical with reference voltage Vref to enable load.Load can include the circuit be made up of various active member and/or passive device, and is coupled between the output terminal 180 of reference voltage stabilising arrangement 100 and the second current potential.
Voltage buffer 110 can adopt the amplifier circuit of Configuration of Negative Feedback, or implements with the mode such as amplifier (class-ABamplifier) of even device (sourcefollower), common-source stage amplifier (commonsourceamplifier) and/or AB class with amplifier circuit collocation source class.In further embodiments, also can adopt other circuit design, receive the reference voltage Vref of input from input end 170, and the output voltage identical with reference voltage Vref is provided.
Charge storage device 120, is coupled between charge-discharge circuit 130 and the first current potential, and it can adopt one or more electric capacity or implemented, to store electric charge with electric capacity other circuit component of arranging in pairs or groups.
Charge-discharge circuit 130, in order to charge to charge storage device 120 and/or discharge (hereinafter referred to as discharge and recharge), makes charge storage device 120 store the default quantity of electric charge.Such as, charge-discharge circuit 130 can adopt the modes such as the current source circuit of various framework to implement.
Control circuit 140, in order to arrange charge-discharge circuit 130, makes charge storage device 120 can store the suitable quantity of electric charge.Such as, control circuit 140 according to the numerical value of the voltage Vo of reference voltage Vref and output terminal, can adopt the mode of tabling look-up, and arranges charge-discharge circuit 130 by charge storage device 120 charge or discharge to the suitable quantity of electric charge.Or, control circuit 140 also can according to the numerical value of the voltage Vo of reference voltage Vref and output terminal, adopt other simulation and/or the signal processing circuit of numeral, and charge-discharge circuit 130 is set by charge storage device 120 charge or discharge to the suitable quantity of electric charge.In addition, control circuit 140 also gauge tap 150 and 160 can in time present conducting or not on-state, provides output voltage Vo to be engraved in output terminal 180 when suitable.
Fig. 2 is the flow process Figure 200 after the embodiment of the reference voltage stabilising arrangement 100 of Fig. 1 when operating simplifies, and below will to arrange in pairs or groups Fig. 1 with Fig. 2, and further illustrate the function mode of reference voltage stabilising arrangement 100.
In flow process 210, reference voltage stabilising arrangement 100 receives reference voltage Vref, and now switch 150 is set to conducting by control circuit 140, and switch 160 is set to not conducting.Make charge-discharge circuit 130 conducting in charge storage device 120, and make voltage buffer 110 and charge storage device 120 not conducting in load.
In flow process 220, the voltage Vo of control circuit 140 meeting foundation reference voltage Vref and output terminal, and charge-discharge circuit 130 is set by charge storage device 120 discharge and recharge to the suitable quantity of electric charge.
In flow process 230, switch 150 can be set to not conducting by control circuit 140, and switch 160 is set to conducting, and voltage buffer 110 and charge storage device 120 is coupled to load, enable the voltage Vo be carried on received by output terminal 180 identical with reference voltage Vref rapidly.
In the above-described embodiment, control circuit 140 can adopt various suitable mode to determine the charge or discharge mode of charge storage device 120.Such as, in certain embodiments, control circuit 140 can arrange time, the electric current and/or voltage etc. of charge-discharge circuit 130 pairs of charge storage devices 120 discharge and recharge.In another embodiment, charge storage device 120 includes multiple electric capacity, and control circuit 140 can arrange charge-discharge circuit 130 only to the partition capacitance discharge and recharge of multiple electric capacity, and changes the quantity of electric charge stored by charge storage device 120.
In the above-described embodiment, the voltage Vo of control circuit 140 meeting foundation reference voltage Vref and output terminal, judges the appropriate charge amount of charge storage device 120.Such as, in one embodiment, load is represented with the capacitor equivalent of capacitance C1, and charge storage device 120 is represented with the capacitor equivalent of capacitance C2.To by load by existing current potential charge or discharge to reference voltage Vref time, the electric charge that load must absorb is Q1 (or electric charge of release), then control circuit 140 can arrange charge-discharge circuit 130 and charge storage device 120 is charged to Q1+Q2 in advance, and the current potential that wherein Q2 is charge storage device 120 equals the quantity of electric charge needed for reference voltage Vref.Therefore, after voltage buffer 110 and charge storage device 120 are coupled to load, the electric charge of Q1 can flow to load by charge storage device 120, and make the output of voltage buffer 110, the current potential of charge storage device 120 and load all becomes reference voltage Vref.Due to the transmission of electric charge between charge storage device 120 and load quickly, the time of the voltage Vo of output terminal 180 arrival reference voltage Vref can be made can not to be limited to the electric current of voltage buffer 110, and thus the hsrdware requirements of voltage buffer 110 can significantly reduce.In addition, suitably arrange the quantity of electric charge stored by charge storage device 120 by control circuit 140, the surging after reference voltage stabilising arrangement 100 also can be made to be coupled to load reduces.
In the flow process 220 of other embodiment, control circuit 140 also can adopt other mode to arrange charge-discharge circuit 130, such as, control circuit 140 arranges charge-discharge circuit 130 not based on the voltage Vo of reference voltage Vref or output terminal, but only arranges charge-discharge circuit 130 pairs of charge storage devices 120 and charge according to one or more regular time and/or discharge or charge and/or be discharged to the modes such as one or more fixing quantities of electric charge.
In the flow process 220 of other embodiments, control circuit 140 also can only according to the voltage Vo of reference voltage Vref or output terminal one of them and the discharge and recharge of charge-discharge circuit 130 pairs of charge storage devices 120 is set.Such as, in one embodiment, control circuit 140 can detect the size of surging, then adjusts the quantity of electric charge of charge-discharge circuit 130 pairs of charge storage devices 120 discharge and recharges according to the result detected.
In further embodiments, control circuit 140 also can adopt the combination of various ways and arrange charge-discharge circuit 130.Or in further embodiments, control circuit 140 also can omit or simplify.
In the above-described embodiment, also another switch (not illustrating in Fig. 1) can be increased between voltage buffer 110 and charge storage device 120, when making charge-discharge circuit 130 pairs of charge storage devices 120 carry out discharge and recharge, can not conducting between voltage buffer 110 and charge storage device 120.And when to load supplying, just by conducting between voltage buffer 110 and charge storage device 120.
In the flow process 230 of the above embodiments, when voltage buffer 110 and charge storage device 120 are coupled to load, charge-discharge circuit 130 also can be set and also be coupled to load a period of time, and discharge and recharge is carried out to load, enable the voltage Vo be carried on received by output terminal 180 identical with reference voltage Vref rapidly.
In the flow process 230 of the above embodiments, voltage buffer 110 and charge storage device 120 can be set to successively be coupled to load or be coupled to load simultaneously.
In the above-described embodiment, the quantity of electric charge that control circuit 140 can be estimated stored by it by the voltage of charge storage device 120, or also can according to charge-discharge circuit 130 carry out time of discharge and recharge, voltage, electric current and/or charge storage device 120 resistance value etc. estimate stored by charge storage device 120 the quantity of electric charge.
In the above-described embodiment, the first current potential that in Fig. 1, charge storage device 120 couples and the second current potential that load couples can be identical or different current potentials.
In the above-described embodiment, charge-discharge circuit 130 can only have charge function or discharging function, or also can have charging and discharging function simultaneously.
In the above-described embodiment, charge storage device 120 can be coupled to current potential higher than reference voltage Vref to charge by charge-discharge circuit 130, makes the voltage of the charge storage device after charging 120 be more than or equal to reference voltage Vref.Or charge storage device 120 also can be coupled to current potential lower than reference voltage Vref to discharge by charge-discharge circuit 130, makes the voltage of the charge storage device after electric discharge 120 be less than or equal to reference voltage Vref.
Fig. 3 is the functional block diagram after the reference voltage stabilising arrangement 300 of another embodiment of the present invention simplifies, and reference voltage stabilising arrangement 300 includes voltage buffer 310 and 311, charge storage device 320 and 321, charging circuit 330, discharge circuit 331, control circuit 340, switch 350,351,360 and 361, input end 370 and 371 and output terminal 380 and 381.Reference voltage stabilising arrangement 300 receives differential reference voltage Vref p and Vrefn at input end 370 and 371, and at output terminal 380 and 381, differential output voltage Vop and Von is provided to load, receives differential output voltage Vop and Von identical with differential reference voltage Vref p and Vrefn to enable load.
Voltage buffer 310 and 311, charge storage device 320 and 321, charging circuit 330, discharge circuit 331, control circuit 340, switch 350,351,360 are roughly the same with the connected mode of function block corresponding in Fig. 1, function mode and change shape with 361, and therefore similar part repeats no more.
But, because reference voltage stabilising arrangement 300 needs to produce differential output voltage Vop and Von, therefore control circuit 340 needs to arrange charging circuit 330 charge storage device 320 is charged to the suitable quantity of electric charge, and arranges discharge circuit 331 charge storage device 321 is discharged to the suitable quantity of electric charge.Therefore when control circuit 340 arranges switch 350 and 351 not conducting, and after switch 360 and 361 conducting is set, voltage buffer 310 and 311 and charge storage device 320 and 321 can be coupled to load, enable the differential voltage that is carried between output terminal 380 with voltage Vop with Von received by 381 identical with the differential voltage between reference voltage Vref p with Vrefn rapidly.
In the present embodiment, charge storage device 320 and 321 is all coupled to the first current potential.In further embodiments, charge storage device 320 and 321 also can be coupled to different current potentials respectively.
Output voltage Vop with Von of reference voltage stabilising arrangement can be identical with Vrefn with reference voltage Vref p respectively.Or output voltage Vop with Von of reference voltage stabilising arrangement can be not identical with Vrefn with reference voltage Vref p respectively, but the voltage difference between output voltage Vop with Von is identical with the voltage difference between reference voltage Vref p with Vrefn
In the above-described embodiment, also can between voltage buffer 310 and charge storage device 320, with/or increase switch between voltage buffer 311 and charge storage device 321, when charging circuit 330 pairs of charge storage devices 320 are charged, and/or discharge circuit 331 pairs of charge storage devices 321 are when discharging, can not conducting between voltage buffer 310 and charge storage device 320, and/or can not conducting between voltage buffer 311 and charge storage device 321.And when to load supplying, just by conducting between voltage buffer 310 and charge storage device 320, and/or conducting between voltage buffer 311 and charge storage device 321.
In the above-described embodiment, reference voltage stabilising arrangement is by pre-charged by charge storage device or be discharged to the suitable quantity of electric charge, therefore when voltage buffer and charge storage device are coupled to load, (or drawing certainly) load can be sent to by electric charge fast, make load can reach the voltage close or identical with reference voltage rapidly.Now, voltage buffer only needs to provide electric current with to estimating the action carrying out discharge and recharge with the charge differences amount of reality, and with reference to the output voltage correction of voltage stabilizing device to identical with reference voltage.Therefore, all can reduce for the frequency range of voltage buffer and the requirement of driving force, and charge storage device (as, electric capacity) hardware area and energy resource consumption all very low, the design difficulty of reference voltage stabilising arrangement, hardware area and power consumption therefore can be made significantly to reduce.
Because the time of transmission charge between charge storage device and load is quite quick, and voltage buffer only must revise small size voltage differences.Therefore, the present invention can be applicable in the system application such as analog-digital converter at a high speed.
In addition, in the application such as such as a/d converter successive approximation (successiveapproximationADC), control circuit can by the mode such as tabling look-up, and arrange charge-discharge circuit in advance by charge storage device discharge and recharge to accurate charge value.
In addition, the present invention also can arrange in pairs or groups with the mode of ameliorating of various voltage buffer and use.Such as, the frequency range of suitable raising voltage buffer, reduce the output impedance of voltage buffer and/or dynamically change the output current of voltage buffer, and in above-described embodiment of arranging in pairs or groups, adopting charge-discharge circuit and charge storage circuit to the mode of load charge-discharge.
Some vocabulary in instructions and claims is used to censure specific element, and person of ordinary skill in the field should understand, and same element may be called with different nouns.In instructions and claims, not using the difference of title as the mode of distinguish one element from another, but carry out the benchmark for distinguishing with element difference functionally." comprising " mentioned in instructions and claims is an open term, therefore should be construed to " comprise but be not limited to ".In addition, " couple " word comprise directly any and indirectly connect means.
The foregoing is only embodiments of the invention, combination that all can be suitable between the portion of techniques feature of each embodiment and each embodiment and not mutual exclusion, all do according to claims of the present invention equalization change, modify and combine, all belong to covering scope of the present invention.
Claims (10)
1. a reference voltage stabilising arrangement, it includes:
One input end, in order to receive a reference voltage;
One output terminal, in order to be coupled to a load;
One voltage buffer, is coupled between described input end and described output terminal;
One charge storage device, is coupled to described output terminal; And
One charge-discharge circuit, is coupled to described charge storage device;
Wherein said charge-discharge circuit can carry out charge or discharge to described charge storage device, and the described charge storage device after described voltage buffer and charge or discharge can to described load supplying, make the voltage of described load through equaling described reference voltage after a period of time
Wherein said charge storage device is charged to first quantity of electric charge and the second quantity of electric charge sum, when wherein said first quantity of electric charge is described load by existing current potential charge or discharge to described reference voltage, the quantity of electric charge that described load must absorb or discharge, the current potential that described second quantity of electric charge is described charge storage device equals the quantity of electric charge needed for described reference voltage.
2. reference voltage stabilising arrangement according to claim 1, also includes a control circuit,
Described control circuit can when first period, make described charge storage device and described load not conducting, and make described charge-discharge circuit and described charge storage device conducting, to make described charge-discharge circuit carry out charge or discharge to described charge storage device, and
Described control circuit can when second period, make described charge-discharge circuit and the not conducting of described charge storage device, and make described charge storage device and described load conduction, make described charge storage device to described load transmission electric charge or from described load-receipt electric charge.
3. reference voltage stabilising arrangement according to claim 2, wherein said control circuit according to the voltage of described reference voltage and/or described load, can control described charge-discharge circuit carries out discharge and recharge time, curtage to described charge storage device.
4. reference voltage stabilising arrangement according to claim 2, wherein said control circuit can according to the voltage of described reference voltage and/or described load, controls described charge-discharge circuit and carry out discharge and recharge at least partly to electric capacity multiple in described charge storage device.
5. the reference voltage stabilising arrangement according to claim 2,3 or 4, the signal processing circuit that wherein said control circuit can adopt simulation and/or numeral or the mode of tabling look-up, control described charge-discharge circuit and carry out charge or discharge to described charge storage device.
6. reference voltage stabilising arrangement according to claim 2, wherein said control circuit can when described first period, described voltage buffer and the not conducting of described charge storage device are set, and when described second period, described voltage buffer and described load conduction can be set.
7. reference voltage antihunt means, it includes:
A voltage buffer is utilized to receive a reference voltage;
Charge or discharge are carried out to a charge storage device; And
Utilizing the described charge storage device after described voltage buffer and charge or discharge to a load supplying, making the voltage of described load through equaling described reference voltage after a period of time;
Wherein said charge storage device is charged to first quantity of electric charge and the second quantity of electric charge sum, when wherein said first quantity of electric charge is described load by existing current potential charge or discharge to described reference voltage, the quantity of electric charge that described load must absorb or discharge, the current potential that described second quantity of electric charge is described charge storage device equals the quantity of electric charge needed for described reference voltage.
8. reference voltage antihunt means according to claim 7, also include:
When first period, make described charge storage device and described load not conducting, and charge or discharge are carried out to described charge storage device; And
When second period, make described charge storage device and described load conduction, and make described charge storage device to described load transmission or from described load-receipt electric charge.
9. reference voltage antihunt means according to claim 8, also include:
According to the voltage of described reference voltage and/or described load, control time, curtage that described charge storage device carries out discharge and recharge.
10. reference voltage antihunt means according to claim 8, also include:
According to the voltage of described reference voltage and/or described load, and at least partly discharge and recharge is carried out to electric capacity multiple in described charge storage device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161446523P | 2011-02-25 | 2011-02-25 | |
| US61/446523 | 2011-02-25 |
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| CN102650892A CN102650892A (en) | 2012-08-29 |
| CN102650892B true CN102650892B (en) | 2016-01-13 |
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| CN201110460675.0A Active CN102650892B (en) | 2011-02-25 | 2011-12-31 | Reference voltage stabilising arrangement and relevant voltage stabilizing method |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3814800B2 (en) * | 2002-08-20 | 2006-08-30 | 有限会社サンブリッジ | Output stabilization system |
| CN101694961A (en) * | 2009-09-18 | 2010-04-14 | 和芯微电子(四川)有限公司 | Low ripple wave boosting type charge pump |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL9002716A (en) * | 1990-12-11 | 1992-07-01 | Philips Nv | POWER SUPPLY. |
| JP3700558B2 (en) * | 2000-08-10 | 2005-09-28 | 日本電気株式会社 | Driving circuit |
| US6366124B1 (en) * | 2001-05-16 | 2002-04-02 | Pericom Semiconductor Corp. | BiDirectional active voltage translator with bootstrap switches for mixed-supply VLSI |
| JP3813477B2 (en) * | 2001-09-12 | 2006-08-23 | シャープ株式会社 | Power supply device and display device having the same |
| US6567028B2 (en) * | 2001-10-12 | 2003-05-20 | Micron Technology, Inc. | Reference voltage stabilization in CMOS sensors |
| JP4734518B2 (en) * | 2006-02-02 | 2011-07-27 | シャープ株式会社 | Power circuit |
| TW200832868A (en) * | 2007-01-26 | 2008-08-01 | Univ Nat Chiao Tung | Pre-charge sample-and-hold circuit |
| EP2075909A3 (en) * | 2007-12-26 | 2016-10-12 | TPO Displays Corp. | Current sampling method and circuit |
| JP2010146526A (en) * | 2008-12-22 | 2010-07-01 | Panasonic Corp | Reference voltage generating circuit |
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2011
- 2011-12-31 CN CN201110460675.0A patent/CN102650892B/en active Active
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2012
- 2012-01-17 TW TW101101699A patent/TWI474620B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3814800B2 (en) * | 2002-08-20 | 2006-08-30 | 有限会社サンブリッジ | Output stabilization system |
| CN101694961A (en) * | 2009-09-18 | 2010-04-14 | 和芯微电子(四川)有限公司 | Low ripple wave boosting type charge pump |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102650892A (en) | 2012-08-29 |
| TWI474620B (en) | 2015-02-21 |
| TW201236370A (en) | 2012-09-01 |
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