EP2012250B1 - Analogue divider - Google Patents
Analogue divider Download PDFInfo
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- EP2012250B1 EP2012250B1 EP20080103649 EP08103649A EP2012250B1 EP 2012250 B1 EP2012250 B1 EP 2012250B1 EP 20080103649 EP20080103649 EP 20080103649 EP 08103649 A EP08103649 A EP 08103649A EP 2012250 B1 EP2012250 B1 EP 2012250B1
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- Prior art keywords
- signal
- saw tooth
- input voltage
- regulator
- supplied
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
- G06G7/161—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form
Definitions
- the invention relates to a method for operating an analog divider, wherein a sawtooth or triangular signal is formed, for generating a first input voltage as a divisor and a reference potential are given, and wherein this sawtooth or triangular signal by means of a first comparator with a second input voltage as Dividend is compared in such a way that as a first comparison signal, a pulse width modulated signal is generated, the average value is output as a quotient of the division. Furthermore, the invention relates to an analog divider for carrying out the method.
- Analog dividers are circuits that are mainly used in control engineering. For example, in electric devices that are power-controlled, a quotient formation is required in order to determine a desired current from a predetermined power and a measured voltage. Another application is in the control of complex clocked converters with two pole positions. In this case, an input voltage and an output voltage are measured and derived according to the type of the converter, a duty cycle size, for example, by dividing the output voltage by the sum of input and output voltage.
- analogue dividers are known, by means of which an output voltage is derived from two input voltages, which corresponds to the quotient of the division of the two input voltages.
- operational amplifiers are used. These operational amplifiers are with appropriate wiring as logic devices such For example, subtractor, logarithm or De-logarithmier formed.
- An analog divider is then composed, for example, of two logarithmers, a subtractor and a de-logarithm (cf. Fig. 1 ).
- JP 2005 157 721 A1 In order to reduce the influence of the component tolerance, is in the JP 2005 157 721 A1 indicated a circuit in which a first input voltage is supplied as a divisor a sawtooth or triangular generator. This generator forms a sawtooth or triangular signal, wherein the value of the first input voltage is specified as a positive peak value of the signal. In a subsequent comparator, this sawtooth or triangular signal is compared with a second input voltage. As a comparison signal is obtained while a pulse width modulated signal, the average value is output as the quotient of the division of the second by the first input voltage.
- a sawtooth or triangular generator comprises components whose tolerances in turn lead to inaccuracies. According to the prior art, such circuits are therefore calibrated, but this is associated with considerable effort. In addition, a one-time calibration is not suitable, for example, to reduce inaccuracies due to a temperature drift of individual components.
- Circuit arrangements are also known for generating a sawtooth or triangular signal, in which further comparators are arranged in such a way that the influence of individual components is eliminated.
- a reference voltage is generally generated which is proportional to the first input voltage (see. Fig. 4 ).
- a known circuit arrangement of a triangular signal generator comprises two comparators and a capacitor to which the triangular signal is applied.
- one comparator compares the triangular signal with the first input voltage and the other comparator compares the triangular signal with a reference potential.
- a controller switches the capacitor alternately to a current source and a current sink (see. Fig. 5 ).
- Another circuit arrangement for generating a triangular signal has a similar structure, but instead of the current source and the current sink comprises a positive and a negative voltage source.
- the switching element for switching between positive and negative voltage source then an example designed as a wired operational amplifier integrator is connected to the output of the triangular signal can be tapped (see. Fig. 6 ).
- a triangular signal generated in this way has the disadvantage that due to the response times of the comparators delays in the switching of the switching element occur, which lead to an inaccurate triangular signal (see. Fig. 7 and 8th ). As a result, the quotient of the division is also error-prone.
- a control method for a two-stage converter in which a non-variable sawtooth signal is generated by means of a signal generator G and used as a first reference signal.
- a peaking serves to generate a second sawtooth signal, which is available as a non-variable second reference signal.
- the invention has for its object to provide an improvement over the prior art for an analog divider of the type mentioned.
- this object is achieved by a method for operating an analog divider, wherein a splitge leopard- or triangular signal is formed, for generating a first input voltage as a divisor and a reference potential are given, and wherein this shege leopard- or triangular signal by means of a first comparator with a second input voltage compared as a dividend in the way is that as a first comparison signal, a pulse width modulated signal is generated, the average value is output as a quotient of the division.
- the sawtooth or triangular signal is formed by means of a first and a second regulator, and the first regulator (REG1) is supplied with the first input voltage (U1) or a voltage proportional thereto and the sawtooth or triangular signal or a signal proportional thereto in such a way that the upper peak value of the sawtooth or triangular signal of the first input voltage is readjusted. Furthermore, the reference potential and the sawtooth or triangular signal are supplied to the second regulator (REG2) in such a way that the lower peak value of the sawtooth or triangular signal is readjusted to the value of the reference potential.
- the first comparison signal is smoothed by means of a first and a second low-pass filter and that a voltage applied to the output of the second low-pass filter output voltage (U D ) is readjusted by means of a third controller a smoothed signal at the output of the first low-pass filter.
- the sawtooth or triangular generator provides a signal that over the prior art leads to higher accuracies in analog dividers.
- a control signal is formed by means of the first controller as the upper nominal peak value, and this actuating signal is supplied to a second comparator for comparison with the sawtooth or triangular signal. Furthermore, by means of a second controller an actuating signal is formed as a lower desired peak value and this actuating signal is fed to a third comparator for comparison with the sawtooth or triangular signal.
- the second comparison signal at the output of the second comparator and the third Comparison signal at the output of the third comparator are supplied to a controller, by means of which the charging and discharging of a capacitor for forming the sawtooth or triangular signal is controlled.
- the comparators are thus given the control signals of the controller for comparison with the triangular signal. In this way one obtains two controlled systems for generating a triangular signal whose peak values correspond exactly to the desired values.
- the actuating signal of the first regulator is formed from the deviation of the upper actual peak value of the triangular signal from the first input voltage and the actuating signal of the second regulator is formed from the deviation of the lower actual peak value of the triangular signal from the reference potential.
- the first controller provides a lower control signal when the upper actual peak of the triangular signal rises above the value of the first input voltage. If, on the other hand, the upper actual peak value of the triangular signal falls below the value of the first input voltage, the first controller gives a higher actuating signal.
- a method for high first input voltages, a method is provided in which the control signal of the first controller from the deviation of the averaged by the low-pass filter triangular signal of half the first input voltage is formed and in which the control signal of the second controller from the deviation of the lower actual peak value of the triangular signal from Reference potential is formed.
- the first input voltage applied to the first regulator is thus halved, which is why a regulator with a lower permissible input voltage can be used for this process.
- an analog divider which receives a first input voltage as a divisor and a second input voltage as a dividend and which comprises a sawtooth or triangular generator, to which the first input voltage is predetermined as the upper peak value of a generated sawtooth or triangular signal, the output of the sawtooth or triangular generator being connected to an input of a first comparator, which is additionally supplied with the second input voltage.
- the sawtooth or triangular generator comprises a first controller to which the first input voltage or a voltage proportional thereto and the sawtooth or triangular signal are supplied and whose control signal is fed to a second comparator, which the sawtooth or triangular signal with the control signal of the first Regulator compares and at the output of a second comparison signal is applied.
- the sawtooth or triangular generator comprises a second regulator, at the input of which the reference potential is present and to which the sawtooth or triangular signal is supplied and whose actuating signal is supplied to a third comparator, which compares the sawtooth or triangular signal with the actuating signal of the second regulator and at whose output a third comparison signal is applied.
- the second and third comparison signals are supplied to a controller which alternately switches a charging circuit and a discharging circuit to a capacitor to form the sawtooth or triangular signal.
- the first comparison signal is fed via a first low-pass filter to a third controller whose output is connected to a second low-pass filter and in that the output voltage applied to the output of the second low-pass filter is in turn fed to the third controller as a controlled variable.
- a third controller whose output is connected to a second low-pass filter and in that the output voltage applied to the output of the second low-pass filter is in turn fed to the third controller as a controlled variable.
- the first controller is supplied with the first input voltage and the sawtooth or triangular signal for forming the actuating signal.
- the first regulator is supplied with half the first input voltage in such a way that the first input voltage is connected to the first regulator via a voltage divider and further that the first regulator is a sawtooth or triangular signal averaged by a low-pass filter is supplied.
- the voltage divider is formed in a simple manner from two equal resistors, which are connected in series between the first input voltage and the reference potential, wherein a connection point between the resistors is connected to the first regulator.
- the controller comprises a latch to which the second and third comparison signal are supplied and by means of which a switching element is driven, which alternately connects the capacitor to a positive current source and a negative current source. In this way, a simple circuit for generating a stable triangular signal is given.
- the frequency of the triangular signal is independent of the height of the first input voltage. This is accomplished by the current source providing a positive current formed of the first input voltage times a positive coefficient, and the current sink providing a negative current that is the first Input voltage is formed times a negative coefficient.
- the controller comprises a latch, to which the second and third comparison signal are supplied and by means of which a switching element is driven, which via a resistor, the capacitor alternately to this positive voltage source and this negative voltage source turns on and when the resistor and the capacitor are circuit elements of an integrally formed as an operational amplifier, at the output of the shege leopard- or triangular signal is applied.
- the accuracy of the analog division is also increased if the first comparator is followed by a switchable reference unit REF. In this way inaccuracies of the comparator are avoided, which can occur due to fluctuations of the signal states at the output of the comparator.
- the signal states of the pulse-width-modulated signal at the output of the reference unit stably assume the high and low values specified by the reference unit.
- FIG. 1 shows a circuit construction of an analog divider according to the prior art.
- Two input voltages U1, U2 are connected to one logarithm ln in each case.
- the outputs of the logarithms ln are fed to a divider ⁇ whose output is connected to the input of a de-logarithm e x .
- Logarithm ln, de-logarithm e x and divider ⁇ are designed as switched operational amplifiers.
- the scattering of electrical properties of the Bescharisbaurii leads to inaccuracies.
- analog divider with a sawtooth or triangular generator according to the preamble of the present invention.
- FIG. 2 is such an analog divider represented by the logic circuits in accordance with FIG. 1 occurring inaccuracies are minimized.
- a first comparator KO1 a sawtooth signal whose peak value corresponds to the value of a first input voltage U1, compared with the value of a second input voltage U2.
- the quotient thus corresponds to the mean value of the pulse width modulated signal applied as output voltage U D.
- the accuracy of the division depends on the one hand on the quality of the sawtooth signal and on the other hand on the response of the first comparator KO1.
- the charging circuit comprises by way of example a voltage source which supplies a constant reference voltage U REF and is connected via a resistor R to the negative terminal of a second comparator KO2.
- the negative terminal of the second comparator KO2 is also connected to a capacitor C, which is charged by means of a charging circuit.
- the first input voltage U1 is applied to the positive terminal of the second comparator KO2, so that a second comparison signal SIG2 OUT can be removed at the output. Accordingly, this second comparison signal SIG2 OUT indicates, with a high-low transition, that the voltage UC at the capacitor C is the value of the first input voltage U1 has reached.
- an abrupt discharge of the capacitor C is brought about when this state is reached by means of a mono-flip-flop MFF.
- the capacitor C is a switching element connected in parallel as part of the discharge circuit, wherein the mono-flip-flop MFF to which the second comparison signal SIG2 OUT is supplied at each high-low transition a turn-on with a pulse duration t FF greater than Discharge time of the capacitor C supplies.
- t ⁇ 2 U ⁇ 2 * C / K * U REF
- the duty cycle of the pulse width modulated signal at the output of the first capacitor KO1 is thus independent of the electrical properties of the capacitor C and the resistor R or the coefficient K.
- a smoothing member is arranged, consisting of a smoothing resistor R O and a smoothing capacitor C O , wherein the smoothing capacitor C O is connected to a reference potential of the voltages.
- this smoothing element is then applied as an average value of the first comparison signal SIG1 OUT an output voltage U D as a quotient of the division.
- FIG. 3 shows the waveforms in the operation of the circuit according to FIG. 2 , where four diagrams with a constant time axis are shown as abscissa.
- the voltage UC at the capacitor C and the second input voltage U2 over the time t are shown.
- the voltage UC at the capacitor C follows a sawtooth signal having a peak value equal to the value of the first input voltage U1.
- the intersections between the two voltage curves mark the high-low transitions of the first comparison signal SIG1 OUT at the output of the first comparator KO1, shown in the fourth diagram.
- the output voltage U D at the output of the smoothing element is shown as the mean value of the first comparison signal SIG1 OUT .
- the second diagram shows the course of the second comparison signal SIG2 OUT at the output of the second comparator KO2 over the time t.
- the high-low transition takes place as soon as the voltage UC at the capacitor C is the value of the first Input voltage U1 reached.
- Each high-low transition triggers a switch-on pulse of the switching element of the discharge circuit by means of a mono-flip-flop MFF, so that the voltage UC at the capacitor C drops abruptly and the second comparison signal SIG2 OUT again assumes the high-signal state.
- the duration t FF of each switch-on pulse must be at least as long as the discharge duration of the capacitor C.
- the pulse duration t FF must not significantly exceed the discharge duration, because the short-term occurrence of the capacitor voltage UC constant portions of the sawtooth signal then cause inaccuracies in the quotient formation. The occurring error is greater, the greater the frequency.
- the circuit shown has the disadvantage that the frequency of the sawtooth signal increases with decreasing input voltage U1. Over a constant observation period, more constant sections of the sawtooth signal thus occur.
- the auxiliary voltage of the charging circuit is set in a fixed ratio to the first input voltage U1.
- a corresponding circuit arrangement is in FIG. 4 shown. Except for the formation of the auxiliary voltage, the arrangement corresponds to in FIG. 2 shown.
- a triangular generator is arranged in the circuit instead of a sawtooth generator.
- FIG. 5 a corresponding circuit arrangement is shown.
- the negative input of the first comparator KO1 is supplied with a triangular signal whose peak value corresponds to the value of the first input voltage U1.
- This triangular signal is formed by means of a second comparator KO2, to whose positive input the first input voltage U1 and to whose negative input a capacitor C is connected.
- the negative input of the second comparator KO2 is connected to the negative input of the first comparator KO1.
- the capacitor C is cyclically charged and discharged by means of a charge and discharge circuit in such a way that a triangular signal is given.
- the charging and discharging circuit in this case comprises a switching element which turns on the capacitor C alternately to a current source with a charging current + i1 and to a current sink with a discharge current -i2.
- This switching element is controlled by means of a latch LA, also called a delay flip-flop, whose first input to the output of the second comparator KO2 and whose second input is connected to the output of a third comparator KO3.
- the third comparator KO3 is connected to the negative input to a reference potential of the voltages and the positive input is connected to the negative inputs of the two other comparators KO1, KO2.
- the first input signal of the latch LA has a high-low transition when the voltage UC across the capacitor C reaches the value of the first input voltage U1.
- a high-low transition of the second input signal of the latch LA occurs when the voltage across the capacitor C reaches the value of the reference potential.
- FIG. 6 is also shown a circuit arrangement with triangular generator, in which case instead of the current sources and the current sink, a positive and a negative voltage source + U REF 1, -U REF 2 are provided.
- driven latch LA switches the voltage sources + U REF 1, -U REF 2 alternately to the input of an integrator INT, which is formed, for example, as with a capacitor C and a resistor R connected operational amplifier.
- the output is then again the desired triangular signal U triangle , which is supplied to the negative input of the first comparator KO1.
- the corresponding diagrams of the signal sequences in an analog divider with triangular generator are in FIG. 7 shown.
- Six diagrams with a constant time axis are arranged as abscissa.
- the first diagram shows the profile of the voltage UC at the capacitor C, the first input voltage U1 and the second input voltage U2 over the time t.
- the capacitor voltage UC follows a triangular signal with a cyclical sequence of a rising ramp from the value of the reference potential to the value of the first input voltage U1 during a first time interval t S and a falling ramp from the value of the first input voltage U1 to the value of the reference potential during a second time period t f .
- the two input signals of the latch LA assume the low-signal states only for the duration of the response times of the corresponding comparators KO2, KO3 and then immediately return to the high-signal state, because immediately after the response of a comparator KO2, KO3 a switching of the Switching element by means of Latch LA done.
- the curves of the first and the second input signal over the time t are in the second and third diagram of FIG. 7 shown.
- the fourth diagram shows the turn-on times of the current source to the capacitor C over the time t.
- the ON connection is effected by means of a switching element as soon as the second input of the latch LA is subjected to a high-low transition, with a positive charging current + i1 flowing into the capacitor C.
- the switch-off occurs OFF.
- the shutoff OFF from the power source is at the same time the connection ON to the current sink and a discharge current -i2 flows from the capacitor C to the current sink until the capacitor voltage UC has reached the value of the reference potential.
- the course of the turn-on times of the current sink to the capacitor C is shown in the fifth diagram.
- the triangular signal generated in this way is compared in the first comparator KO1 with the second input voltage U2.
- the first comparison signal SIG1 OUT at the output of the The first comparator KO1 is then again a pulse width modulated signal whose duty cycle corresponds to the quotient of the division of the second input voltage U2 by the first input voltage U1:
- U ⁇ 2 / U ⁇ 1 t ⁇ 2 / t ⁇ 1 with t2 as the duration of the high-signal state
- the first five diagrams of FIG. 7 are in more detailed form also in FIG. 8 shown.
- this reaches the value of the first input voltage U1
- the high-low transition of the second comparison signal (SIG2 OUT ) is delayed due to the response time td-KO2 of the second comparator KO2.
- the switching of the Switching element due to the response time of the latch t d-LA delayed.
- delays occur due to the response time t d-KO3 of the third comparator KO3 and the response time t d-LA of the latch LA when the falling voltage UC across the capacitor C reaches the value of the reference potential.
- a defective ratio t2 / (t1-t d) Compared with an error-free ratio t2 / t1 is obtained a defective ratio t2 / (t1-t d).
- the percentage error ((t2 / t1) / (t2 / (t1-t d)) * 100%) is then for example, at 4.167% when the response time t d 1 is equal to 200 ns and a triangle wave frequency of 100 kHz is assumed.
- FIG. 9 An exemplary embodiment of the invention is in FIG. 9 shown.
- the two comparators KO2, KO3 of a triangular generator are preceded by two regulators REG1, REG2.
- the first regulator REG1 is supplied with the first input voltage U1 as the setpoint signal. This setpoint signal is by means of the first controller REG1 with the Actual values of the upper peak values of the triangular signal compared.
- the triangular signal formed as a capacitor voltage UC is supplied to an input of the first regulator REG1.
- the first regulator REG1 forms from the input variables a control signal SIG4 OUT , which is supplied to the second comparator KO2 for comparison with the triangular signal.
- the actuating signal SIG4 OUT is predetermined such that the actual peak values of the triangular signal of the first input voltage U1 are readjusted.
- the second regulator REG2 is supplied with the triangular signal.
- the second regulator REG2 compares the lower actual peak values of the triangular signal with a reference potential.
- the control signal SIG5 OUT of the second regulator REG2 is supplied to the third comparator KO3 for comparison with the triangular signal.
- the lower peak values of the triangular signal are readjusted to the value of the reference potential.
- comparators generally have a higher slew rate than operational amplifiers. Therefore, regulators REG1, REG2 with correspondingly high slew rates must be provided.
- the mean value of the triangular signal is formed by means of a low-pass filter TPF, which is connected upstream of the first regulator REG1.
- Half the value of the first input voltage U1 is formed by means of a voltage divider.
- the voltage divider comprises two high-impedance resistors R, which are arranged in series between the first input voltage U1 and the reference potential, wherein a connection point between the resistors R and an input of the first Regulator REG1 is connected. Otherwise corresponds to in FIG. 10 illustrated arrangement of in FIG. 9 shown.
- FIG. 11 shows the waveform during operation of an analog divider according to the invention.
- the triangular signal is shown as a capacitor voltage UC, superimposed by the curves of the reference potential 0, the first input voltage U1, the second input voltage U2 and the control signals SIG4 OUT , SIG5 OUT of the two regulators REG1, REG2.
- the first regulator REG1 forms a control signal SIG4 OUT whose profile is below the curve of the input voltage U1.
- the difference to the input voltage U1 is so great that the response times td-KO2 , td -LA of the second comparator KO2 and the latch LA are compensated and the rising ramp of the triangular signal ends precisely upon reaching the value of the input voltage U1.
- the second regulator REG2 forms a control signal SIG4 OUT whose profile is above the course of the reference potential 0.
- the difference to the reference potential 0 is again so great that the response times td-KO3 , td -LA of the third comparator KO3 and the latch LA are compensated and the falling ramp of the triangular signal terminates precisely when the reference potential is reached.
- a further increase in accuracy is achieved by the stabilization of the two signal states at the output of the first comparator KO1.
- a switchable reference unit REF is connected downstream of the first comparator KO1. At the output of the reference unit REF is then applied to a referenced signal SIG6 OUT that changes according to the first comparison signal SIG1 OUT at the output of the first comparator KO1 between a referenced high value + U REF-S and a referenced low value.
- the first comparator or the reference unit REF is followed by a smoothing unit, which comprises two low-pass filters TPF1, TPF2 and a third regulator REG3.
- the corresponding circuit arrangement is in FIG. 12 shown.
- the first low-pass filter TPF1 is formed, for example, as a so-called RC element with a first resistor R1 and a first capacitor C1.
- the second low-pass filter TPF2 is formed as an RC element with a second resistor R2 and a second capacitor C2.
- the cut-off frequency f g1 of the first low-pass filter TPF1 is smaller than the cut-off frequency f g2 of the second low-pass filter TPF2 (f g2 ⁇ 5 * f g1 to 10 * f g1 ).
- the design of the cut-off frequencies f g1 , f g1 depends on the frequency of the triangular signal and can be determined in a simple manner.
- the third regulator REG3 is connected, the third controller also being supplied with the output voltage U D as a controlled variable.
- the third regulator REG3 regulates the output voltage U D to the signal SIG7 OUT smoothed by the first low-pass filter TPF1.
- the corresponding signal curves are in FIG. 13 shown.
- the first diagram again shows the course of the triangular signal, superposed by the curves of the first and second input voltage U1, U2 and the two actuating signals SIG4 OUT , SIG5 OUT .
- the diagram below shows the profile of the first comparison signal SIG1 OUT at the output of the first comparator.
- the third diagram shows the corresponding comparison signal SIG6 OUT at the output of the reference unit with the two referenced signal states + U REF-S , O.
- the bottom diagram shows the course of the signals at the output of the first low-pass filter SIG7 OUT at the output of the second low-pass filter U D.
- the smoothed signal SIG7 OUT at the output of the first low-pass filter TPF1 has pronounced falling and rising portions, whereas the output voltage U D at the output of the second low-pass filter TPF2 is almost completely smoothed.
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Description
Die Erfindung betrifft einen Verfahren zum Betreiben eines Analog Dividierers, wobei ein Sägezahn- oder Dreieckssignal gebildet wird, zu dessen Generierung eine erste Eingangsspannung als Divisor und ein Bezugspotenzial vorgegeben werden, und wobei dieses Sägezahn- oder Dreieckssignal mittels eines ersten Komparators mit einer zweiten Eingangsspannung als Dividend in der Weise verglichen wird, dass als ein erstes Vergleichssignal ein pulsweitenmoduliertes Signal erzeugt wird, dessen Mittelwert als Quotienten der Division ausgegeben wird. Des Weiteren betrifft die Erfindung einen Analog Dividierer zur Ausführung des Verfahrens.The invention relates to a method for operating an analog divider, wherein a sawtooth or triangular signal is formed, for generating a first input voltage as a divisor and a reference potential are given, and wherein this sawtooth or triangular signal by means of a first comparator with a second input voltage as Dividend is compared in such a way that as a first comparison signal, a pulse width modulated signal is generated, the average value is output as a quotient of the division. Furthermore, the invention relates to an analog divider for carrying out the method.
Analoge Dividierer sind Schaltungen, die vor allem in der Regelungstechnik genutzt werden. Beispielsweise ist bei elektrischen Geräten, die leistungsgeregelt sind, eine Quotientenbildung erforderlich, um aus einer vorgegebenen Leistung und einer gemessenen Spannung einen Sollstrom zu ermitteln. Eine andere Anwendung ist in der Regelung komplexer getakteter Wandler mit zwei Polstellungen gegeben. Dabei werden eine Eingangsspannung und eine Ausgangsspannung gemessen und entsprechend dem Typ des Wandlers eine Tastverhältnisgröße abgeleitet, indem beispielsweise die Ausgangsspannung durch die Summe aus Eingangs- und Ausgangsspannung dividiert wird.Analog dividers are circuits that are mainly used in control engineering. For example, in electric devices that are power-controlled, a quotient formation is required in order to determine a desired current from a predetermined power and a measured voltage. Another application is in the control of complex clocked converters with two pole positions. In this case, an input voltage and an output voltage are measured and derived according to the type of the converter, a duty cycle size, for example, by dividing the output voltage by the sum of input and output voltage.
Nach dem Stand der Technik kennt man unterschiedlich aufgebaute analoge Dividierer, mittels derer aus zwei Eingangsspannungen eine Ausgangsspannung abgeleitet wird, welche dem Quotienten der Division der beiden Eingangsspannungen entspricht. Dabei kommen in der Regel Operationsverstärker zum Einsatz. Diese Operationsverstärker sind mit entsprechender Beschaltung als Logikbausteinen wie z.B. Subtrahierer, Logarithmierer oder De-Logarithmierer ausgebildet. Ein analoger Dividierer setzt sich dann beispielsweise aus zwei Logarithmierern, einem Subtrahierer und einem De-Logarithmierer zusammen (vgl.
Derartige Schaltungen sind aufwendig aufgebaut und ungenau, da die elektrischen Eigenschaften der Bauelemente zur Beschaltung der Operationsverstärker Toleranz unterliegen.Such circuits are complex and inaccurate, since the electrical properties of the components for wiring the operational amplifier are subject to tolerance.
Um den Einfluss der Bauelementetoleranz zu reduzieren, ist in der
Ein Sägezahn- oder Dreiecksgenerator umfasst dabei in der Regel Bauelemente, deren Toleranzen wiederum zu Ungenauigkeiten führen. Nach dem Stand der Technik werden derartige Schaltungen deshalb kalibriert, was jedoch mit erheblichem Aufwand verbunden ist. Zudem ist eine einmalige Kalibrierung nicht geeignet, um beispielsweise Ungenauigkeiten infolge einer Temperaturtrift einzelner Bauelemente zu reduzieren.As a rule, a sawtooth or triangular generator comprises components whose tolerances in turn lead to inaccuracies. According to the prior art, such circuits are therefore calibrated, but this is associated with considerable effort. In addition, a one-time calibration is not suitable, for example, to reduce inaccuracies due to a temperature drift of individual components.
Es sind auch Schaltungsanordnungen zur Generierung eines Sägezahn- oder Dreieckssignals bekannt, bei welcher weitere Komparatoren in der Weise angeordnet sind, dass sich der Einfluss einzelner Bauelemente aufhebt.Circuit arrangements are also known for generating a sawtooth or triangular signal, in which further comparators are arranged in such a way that the influence of individual components is eliminated.
Das ist beispielsweise der Fall, wenn ein Kondensator über einen Widerstand an eine konstante Referenzspannung geschaltet ist, wobei ein Komparator die Spannung am Kondensator laufend mit der ersten Eingangsspannung als Divisor vergleicht. Bei Erreichen der Eingangsspannung löst ein Signalwechsel am Ausgang des Komparators mittels eines Mono-Flip-Flops einen Schaltimpuls zur Betätigung eines Schaltelements aus, wodurch der Kondensator kurzzeitig kurzgeschlossen und somit entladen wird (vgl.
Sobald der Kondensator entladen ist, beginnt ein neuer Ladevorgang, sodass am Kondensator ein Sägezahnsignal anliegt (vgl.
Um den Einfluss der ersten Eingangsspannung auf die Frequenz des Sägezahnsignals aufzuheben und damit den negativen Einfluss der Schaltimpulszeiten konstant zu halten, wird in der Regel eine Referenzspannung erzeugt, die proportional zur ersten Eingangsspannung ist (vgl.
Der negative Einfluss der Schaltimpulszeiten fällt weg, wenn ein Dreieckssignal erzeugt wird. Eine bekannte Schaltungsanordnung eines Dreieckssignalgenerators umfasst zwei Komparatoren und einen Kondensator, an dem das Dreieckssignal anliegt. Dabei vergleicht ein Komparator das Dreieckssignal mit der ersten Eingangsspannung und der andere Komparator das Dreieckssignal mit einem Bezugspotenzial. Ausgelöst durch die Signalwechsel am Ausgang der Komparatoren schaltet eine Steuerung den Kondensator abwechselnd an eine Stromquelle und eine Stromsenke (vgl.
Eine andere Schaltungsanordnung zur Generierung eines Dreieckssignals ist ähnlich aufgebaut, umfasst jedoch anstelle der Stromquelle und der Stromsenke eine positive und eine negative Spannungsquelle. An das Schaltelement zur Umschaltung zwischen positiver und negativer Spannungsquelle ist dann ein beispielsweise als beschalteter Operationsverstärker ausgebildeter Integrator geschaltet, an dessen Ausgang das Dreieckssignal abgreifbar ist (vgl.
Ein auf diese Weise erzeugtes Dreieckssignal hat den Nachteil, dass aufgrund der Ansprechzeiten der Komparatoren Verzögerungen bei der Umschaltung des Schaltelements auftreten, die zu einem ungenauen Dreieckssignal führen (vgl.
In der
Ein analoger Dividierer zur Division zweier Gleichströme ist aus der
Der Erfindung liegt die Aufgabe zugrunde, für einen analogen Dividierer der eingangs genannten Art eine Verbesserung gegenüber dem Stand der Technik anzugeben.The invention has for its object to provide an improvement over the prior art for an analog divider of the type mentioned.
Erfindungsgemäß wird diese Aufgabe gelöst durch ein Verfahren zum Betreiben eines Analog Dividierers, wobei ein Sägezahn- oder Dreieckssignal gebildet wird, zu dessen Generierung eine erste Eingangsspannung als Divisor und ein Bezugspotenzial vorgegeben werden, und wobei dieses Sägezahn- oder Dreieckssignal mittels eines ersten Komparators mit einer zweiten Eingangsspannung als Dividend in der Weise verglichen wird, dass als ein erstes Vergleichssignal ein pulsweitenmoduliertes Signal erzeugt wird, dessen Mittelwert als Quotienten der Division ausgegeben wird. Dabei wird das Sägezahn- oder Dreieckssignal mittels eines ersten und eines zweiten Reglers gebildet und dem ersten Regler (REG1) die erste Eingangsspannung (U1) oder eine dazu proportionale Spannung und das Sägezahn- oder Dreieckssignal oder ein dazu proportionales Signal in der Weise zugeführt, dass der obere Spitzenwert des Sägezahn- oder Dreieckssignals der ersten Eingangsspannung nachgeregelt wird. Des Weiteren wird dem zweiten Regler (REG2) das Bezugspotenzial und das Sägezahn- oder Dreieckssignal in der Weise zugeführt, dass der untere Spitzenwert des Sägezahn- oder Dreieckssignals dem Wert des Bezugspotenzials nachgeregelt wird.According to the invention this object is achieved by a method for operating an analog divider, wherein a Sägezahn- or triangular signal is formed, for generating a first input voltage as a divisor and a reference potential are given, and wherein this Sägezahn- or triangular signal by means of a first comparator with a second input voltage compared as a dividend in the way is that as a first comparison signal, a pulse width modulated signal is generated, the average value is output as a quotient of the division. In this case, the sawtooth or triangular signal is formed by means of a first and a second regulator, and the first regulator (REG1) is supplied with the first input voltage (U1) or a voltage proportional thereto and the sawtooth or triangular signal or a signal proportional thereto in such a way that the upper peak value of the sawtooth or triangular signal of the first input voltage is readjusted. Furthermore, the reference potential and the sawtooth or triangular signal are supplied to the second regulator (REG2) in such a way that the lower peak value of the sawtooth or triangular signal is readjusted to the value of the reference potential.
Erfindungsgemäß ist zudem vorgesehen, dass das erste Vergleichssignal mittels eines ersten und eines zweiten Tiefpassfilters geglättet wird und dass eine am Ausgang des zweiten Tiefpassfilters anliegende Ausgangsspannung (UD) mittels eines dritten Reglers einem geglätteten Signal am Ausgang des ersten Tiefpassfilters nachgeregelt wird.According to the invention, it is also provided that the first comparison signal is smoothed by means of a first and a second low-pass filter and that a voltage applied to the output of the second low-pass filter output voltage (U D ) is readjusted by means of a third controller a smoothed signal at the output of the first low-pass filter.
Damit werden sowohl die Einflüsse der Toleranzen als auch die Ansprechzeiten der in der Schaltung angeordneten Komponenten kompensiert. Der Sägezahn- oder Dreiecksgenerator liefert ein Signal, dass gegenüber dem Stand der Technik zu höheren Genauigkeiten bei Analog Dividierern führt.Thus, both the influences of the tolerances and the response times of the components arranged in the circuit are compensated. The sawtooth or triangular generator provides a signal that over the prior art leads to higher accuracies in analog dividers.
In einer vorteilhaften Ausprägung des Verfahrens wird mittels erstem Regler ein Stellsignal als oberer Soll-Spitzenwert gebildet und dieses Stellsignal einem zweiten Komparator zum Vergleich mit dem Sägezahn- oder Dreieckssignal zugeführt. Des Weiterem wird mittels zweitem Regler ein Stellsignal als unterer Soll-Spitzenwert gebildet und dieses Stellsignal einem dritten Komparator zum Vergleich mit dem Sägezahn- oder Dreieckssignal zugeführt wird. Das zweite Vergleichssignal am Ausgang des zweiten Komparators und das dritte Vergleichssignal am Ausgang des dritten Komparators werden einer Steuerung zugeführt, mittels der das Aufladen und Entladen eines Kondensators zur Bildung des Sägezahn- oder Dreieckssignals gesteuert wird. Anstelle der erwünschten Werte für die Spitzenwerte des Dreiecksignals werden den Komparatoren also die Stellsignale der Regler zum Vergleich mit dem Dreieckssignal vorgegeben. Auf diese Weise erhält man zwei Regelstrecken zur Generierung eines Dreieckssignals, dessen Spitzenwerte genau den erwünschten Werten entsprechen.In an advantageous embodiment of the method, a control signal is formed by means of the first controller as the upper nominal peak value, and this actuating signal is supplied to a second comparator for comparison with the sawtooth or triangular signal. Furthermore, by means of a second controller an actuating signal is formed as a lower desired peak value and this actuating signal is fed to a third comparator for comparison with the sawtooth or triangular signal. The second comparison signal at the output of the second comparator and the third Comparison signal at the output of the third comparator are supplied to a controller, by means of which the charging and discharging of a capacitor for forming the sawtooth or triangular signal is controlled. Instead of the desired values for the peak values of the triangular signal, the comparators are thus given the control signals of the controller for comparison with the triangular signal. In this way one obtains two controlled systems for generating a triangular signal whose peak values correspond exactly to the desired values.
In einem einfachen Verfahren wird das Stellsignal des ersten Reglers aus der Abweichung des oberen Ist-Spitzewertens des Dreiecksignals von der ersten Eingangsspannung gebildet und das Stellsignal des zweiten Reglers aus der Abweichung des unteren Ist-Spitzewertens des Dreieckssignals vom Bezugspotenzial gebildet. Beispielsweise gibt der erste Regler ein niedrigeres Stellsignal vor, wenn der obere Ist-Spitzenwert des Dreiecksignals über den Wert der ersten Eingangsspannung ansteigt. Fällt hingegen der obere Ist-Spitzenwert des Dreiecksignals unter den Wert der ersten Eingangsspannung ab, gibt der erste Regler ein höheres Stellsignal vor.In a simple method, the actuating signal of the first regulator is formed from the deviation of the upper actual peak value of the triangular signal from the first input voltage and the actuating signal of the second regulator is formed from the deviation of the lower actual peak value of the triangular signal from the reference potential. For example, the first controller provides a lower control signal when the upper actual peak of the triangular signal rises above the value of the first input voltage. If, on the other hand, the upper actual peak value of the triangular signal falls below the value of the first input voltage, the first controller gives a higher actuating signal.
Für hohe erste Eingangsspannungen ist ein Verfahren vorgesehen, bei dem das Stellsignal des ersten Reglers aus der Abweichung des mittels Tiefpassfilter gemittelten Dreieckssignals von der halben ersten Eingangsspannung gebildet wird und bei dem das Stellsignal des zweiten Reglers aus der Abweichung des unteren Ist-Spitzewertens des Dreieckssignals vom Bezugspotenzial gebildet wird. Die am ersten Regler anliegende erste Eingangsspannung halbiert sich also, weshalb für dieses Verfahren ein Regler mit niedrigerer zulässiger Eingangsspannung verwendbar ist.For high first input voltages, a method is provided in which the control signal of the first controller from the deviation of the averaged by the low-pass filter triangular signal of half the first input voltage is formed and in which the control signal of the second controller from the deviation of the lower actual peak value of the triangular signal from Reference potential is formed. The first input voltage applied to the first regulator is thus halved, which is why a regulator with a lower permissible input voltage can be used for this process.
Gelöst wird die vorliegende Aufgabe zudem durch einen Analog Dividierer, welchem eine erste Eingangsspannung als Divisor und eine zweite Eingangsspannung als Dividend zugeführt sind und welcher einen Sägezahn- oder Dreiecksgenerator umfasst, dem die erste Eingangsspannung als oberer Spitzenwert eines generierten Sägezahn- oder Dreiecksignals vorgegeben ist, wobei der Ausgang des Sägezahn- oder Dreiecksgenerators mit einem Eingang eines ersten Komparator verbunden ist, welchem zudem die zweite Eingangsspannung zugeführt ist, sodass am Ausgang des ersten Komparators ein pulsweitenmoduliertes Signal als erstes Vergleichssignal des Sägezahn- oder Dreiecksignals und der zweiten Eingangsspannung anliegt und einer Glättungseinheit zugeführt ist, an dessen Ausgang das gemitteltes pulsweitenmodulierte Signal als Quotient der Division anliegt und als eine Ausgangsspannung abgreifbar ist. Dabei umfasst der Sägezahn- oder Dreiecksgenerator einen ersten Regler, dem als Eingangssignal die erste Eingangsspannung oder eine dazu proportionale Spannung und das Sägezahn- oder Dreieckssignal zugeführt sind und dessen Stellsignal einem zweiten Komparator zugeführt ist, welcher das Sägezahn- oder Dreieckssignal mit dem Stellsignal des ersten Reglers vergleicht und an dessen Ausgang ein zweites Vergleichssignal anliegt. Des Weitern umfasst der Sägezahn- oder Dreiecksgenerator einen zweiten Regler, an dessen Eingang das Bezugspotenzial anliegt und dem das Sägezahn- oder Dreieckssignal zugeführt ist und dessen Stellsignal einem dritten Komparator zugeführt ist, welcher das Sägezahn- oder Dreieckssignal mit dem Stellsignal des zweiten Reglers vergleicht und an dessen Ausgang ein drittes Vergleichssignal anliegt. Das zweite und das dritte Vergleichssignal sind einer Steuerung zugeführt, welche alternierend eine Ladeschaltung und eine Entladeschaltung an einen Kondensator zur Bildung des Sägezahn- oder Dreiecksignals schaltet.The present object is also achieved by an analog divider, which receives a first input voltage as a divisor and a second input voltage as a dividend and which comprises a sawtooth or triangular generator, to which the first input voltage is predetermined as the upper peak value of a generated sawtooth or triangular signal, the output of the sawtooth or triangular generator being connected to an input of a first comparator, which is additionally supplied with the second input voltage. such that at the output of the first comparator a pulse-width-modulated signal is present as a first comparison signal of the sawtooth or triangular signal and the second input voltage and is supplied to a smoothing unit, at the output of which the averaged pulse-width-modulated signal is applied as a quotient of the division and can be tapped off as an output voltage. In this case, the sawtooth or triangular generator comprises a first controller to which the first input voltage or a voltage proportional thereto and the sawtooth or triangular signal are supplied and whose control signal is fed to a second comparator, which the sawtooth or triangular signal with the control signal of the first Regulator compares and at the output of a second comparison signal is applied. Furthermore, the sawtooth or triangular generator comprises a second regulator, at the input of which the reference potential is present and to which the sawtooth or triangular signal is supplied and whose actuating signal is supplied to a third comparator, which compares the sawtooth or triangular signal with the actuating signal of the second regulator and at whose output a third comparison signal is applied. The second and third comparison signals are supplied to a controller which alternately switches a charging circuit and a discharging circuit to a capacitor to form the sawtooth or triangular signal.
Erfindungsgemäß ist zudem vorgesehen, dass das erste Vergleichssignal über einen ersten Tiefpassfilter einem dritten Regler zugeführt ist, dessen Ausgang mit einem zweiten Tiefpassfilter verbunden ist und dass die am Ausgang des zweiten Tiefpassfilters anliegende Ausgangsspannung wiederum dem dritten Regler als Regelgröße zugeführt ist. Auf diese Weise wird als Quotient der Division eine Ausgangsspannung ausgeben, die sich Änderungen der ersten oder zweiten Eingangsspannung sehr schnell anpasst. Damit ist eine Schaltung geschaffen, die auch bei stark schwankendem Divisor und Dividenden nahezu verzögerungsfreie einen genauen Quotienten der Division ausgibt.According to the invention, it is additionally provided that the first comparison signal is fed via a first low-pass filter to a third controller whose output is connected to a second low-pass filter and in that the output voltage applied to the output of the second low-pass filter is in turn fed to the third controller as a controlled variable. On this way, as a quotient of the division, it will output an output voltage which adapts very quickly to changes in the first or second input voltage. Thus, a circuit is created that outputs a precise quotient of the division even with strongly fluctuating divisor and dividends almost instantaneous.
In einer einfachen Ausprägung der Erfindung sind dem ersten Regler die erste Eingangsspannung und das Sägezahn- oder Dreiecksignal zur Bildung des Stellsignals zugeführt. Für hohe erste Eingangsspannungen ist es vorteilhaft, wenn dem ersten Regler die halbe erste Eingangsspannung in der Weise zugeführt ist, dass die erste Eingangsspannung über einen Spannungsteiler an den ersten Regler geschaltet ist und dass des Weiteren dem ersten Regler ein mittels Tiefpassfilter gemitteltes Sägezahn- oder Dreiecksignal zugeführt ist. Der Spannungsteiler wird in einfacher Weise aus zwei gleichen Widerständen gebildet, die in Reihe zwischen die erste Eingangsspannung und das Bezugspotenzial geschaltet sind, wobei ein Verbindungspunkt zwischen den Widerständen mit dem ersten Regler verbunden ist.In a simple embodiment of the invention, the first controller is supplied with the first input voltage and the sawtooth or triangular signal for forming the actuating signal. For high first input voltages, it is advantageous if the first regulator is supplied with half the first input voltage in such a way that the first input voltage is connected to the first regulator via a voltage divider and further that the first regulator is a sawtooth or triangular signal averaged by a low-pass filter is supplied. The voltage divider is formed in a simple manner from two equal resistors, which are connected in series between the first input voltage and the reference potential, wherein a connection point between the resistors is connected to the first regulator.
Vorteilhaft ist es zudem, wenn die Steuerung ein Latch umfasst, dem das zweite und dritte Vergleichssignal zugeführt sind und mittels dem ein Schaltelement angesteuert ist, welches den Kondensator alternierend an eine positive Stromquelle und eine negative Stromquelle anschaltet. Auf diese Weise ist eine einfache Schaltung zur Erzeugung eines stabilen Dreiecksignals gegeben.It is also advantageous if the controller comprises a latch to which the second and third comparison signal are supplied and by means of which a switching element is driven, which alternately connects the capacitor to a positive current source and a negative current source. In this way, a simple circuit for generating a stable triangular signal is given.
Dabei ist es günstig, wenn die Frequenz des Dreiecksignals unabhängig von der Höhe der ersten Eingangsspannung ist. Das wird erreicht, indem die Stromquelle einen positiven Strom liefert, der aus der ersten Eingangsspannung mal einem positiven Koeffizienten gebildet ist und indem die Stromsenke einen negativen Strom liefert, der aus der ersten Eingangsspannung mal einem negativen Koeffizienten gebildet ist.It is advantageous if the frequency of the triangular signal is independent of the height of the first input voltage. This is accomplished by the current source providing a positive current formed of the first input voltage times a positive coefficient, and the current sink providing a negative current that is the first Input voltage is formed times a negative coefficient.
Für Schaltungen, innerhalb derer eine positive und eine negative Spannungsquelle mit Referenzspannungen zur Verfügung steht, ist es vorteilhaft, wenn die Steuerung ein Latch umfasst, dem das zweite und dritte Vergleichssignal zugeführt sind und mittels dem ein Schaltelement angesteuert ist, welches über einen Widerstand den Kondensator alternierend an diese positive Spannungsquelle und diese negative Spannungsquelle anschaltet und wenn der Widerstand und der Kondensator Beschaltungselemente eines als Integrator ausgebildeten Operationsverstärkers sind, an dessen Ausgang das Sägezahn- oder Dreieckssignal anliegt.For circuits in which a positive and a negative voltage source with reference voltages is available, it is advantageous if the controller comprises a latch, to which the second and third comparison signal are supplied and by means of which a switching element is driven, which via a resistor, the capacitor alternately to this positive voltage source and this negative voltage source turns on and when the resistor and the capacitor are circuit elements of an integrally formed as an operational amplifier, at the output of the Sägezahn- or triangular signal is applied.
Die Genauigkeit der analogen Division wird zudem gesteigert, wenn dem ersten Komparator eine umschaltbare Referenzeinheit REF nachgeschaltet ist. Auf diese Weise werden Ungenauigkeiten des Komparators vermieden, die durch Schwankungen der Signalzustände am Ausgang des Komparators auftreten können. Die Signalzustände des pulsweitenmodulierten Signals am Ausgang der Referenzeinheit nehmen stabil die von der Referenzeinheit vorgegeben High- und Low-Werte an.The accuracy of the analog division is also increased if the first comparator is followed by a switchable reference unit REF. In this way inaccuracies of the comparator are avoided, which can occur due to fluctuations of the signal states at the output of the comparator. The signal states of the pulse-width-modulated signal at the output of the reference unit stably assume the high and low values specified by the reference unit.
Die Erfindung wird nachfolgend in beispielhafter Weise unter Bezugnahme auf die beigefügten Figuren erläutert. Es zeigen in schematischer Darstellung:
- Fig. 1
- Analog Dividierer, aufgebaut mit logischen Baugruppen
- Fig. 2
- Schaltungsanordnung eines Analog Dividierers mit Sägezahngenerator
- Fig. 3
- Signalverläufe eines Analog Dividierers nach
Figur 2 - Fig. 4
- Schaltungsanordnung eines Analog Dividierers mit Sägezahngenerator mit konstanter Frequenz
- Fig. 5
- Schaltungsanordnung eines Analog Dividierers mit Dreiecksgenerator und Stromquelle
- Fig. 6
- Schaltungsanordnung eines Analog Dividierers mit Dreiecksgenerator und Spannungsquelle mit Integrator
- Fig. 7
- Signalverläufe eines Analog
Dividierers nach Figur 5 oderFigur 6 - Fig. 8
- Auswirkung der Ansprechzeiten der Komparatoren auf die Signalverläufe eines Analog Dividierers mit Dreiecksgenerator
- Fig. 9
- Schaltungsanordnung eines Analog Dividierers mit Dreiecksgenerator und Kompensation der Ansprechzeiten der Komparatoren mittels Spitzenwertregler
- Fig. 10
- Schaltungsanordnung eines Analog Dividierers mit Dreiecksgenerator und Kompensation der Ansprechzeiten der Komparatoren mittels Mittelwertregler
- Fig. 11
- Signalverläufe eines Analog Dividierers nach
Figur 9 oderFigur 10 - Fig. 12
- Schaltungsanordnung eines Analog Dividierers mit modifizierter Glättungseinheit
- Fig. 13
- Signalverläufe eines Analog
Dividierers nach Figur 12
- Fig. 1
- Analog divider built with logic modules
- Fig. 2
- Circuit arrangement of an analog divider with sawtooth generator
- Fig. 3
- Waveforms of an analog divider after
FIG. 2 - Fig. 4
- Circuit arrangement of an analog divider with sawtooth generator with constant frequency
- Fig. 5
- Circuit arrangement of an analogue divider with triangular generator and current source
- Fig. 6
- Circuit arrangement of an analogue divider with triangular generator and voltage source with integrator
- Fig. 7
- Waveforms of an analog divider after
FIG. 5 orFIG. 6 - Fig. 8
- Effect of the response times of the comparators on the waveforms of an analogue divider with triangular generator
- Fig. 9
- Circuit arrangement of an analog divider with triangular generator and compensation of the response times of the comparators by means of peak value controller
- Fig. 10
- Circuit arrangement of an analogue divider with triangular generator and compensation of the response times of the comparators by means of a mean value controller
- Fig. 11
- Waveforms of an analog divider after
FIG. 9 orFIG. 10 - Fig. 12
- Circuit arrangement of an analog divider with modified smoothing unit
- Fig. 13
- Waveforms of an analog divider after
FIG. 12
Um die Anzahl der Bauelemente zu reduzieren kennt man deshalb auch Analog Dividierer mit einem Sägezahn- oder Dreiecksgenerator gemäß der Gattung der vorliegenden Erfindung.In order to reduce the number of components is therefore also analog divider with a sawtooth or triangular generator according to the preamble of the present invention.
In
Der Quotient entspricht demnach dem als Ausgangsspannung UD anliegenden Mittelwert des pulsweitenmodulierten Signals. Die Genauigkeit der Division hängt dabei einerseits von der Güte des Sägezahnsignals und andererseits vom Ansprechverhalten des ersten Komparators KO1 ab.The quotient thus corresponds to the mean value of the pulse width modulated signal applied as output voltage U D. The accuracy of the division depends on the one hand on the quality of the sawtooth signal and on the other hand on the response of the first comparator KO1.
Die in
Der negative Anschluss des zweiten Komparators KO2 ist dabei auch mit einem Kondensator C verbunden, der mittels Ladeschaltung aufgeladen wird. Am positiven Anschluss des zweiten Komparators KO2 liegt die erste Eingangsspannung U1 an, sodass am Ausgang ein zweites Vergleichssignal SIG2OUT abnehmbar ist. Dieses zweite Vergleichssignal SIG2OUT zeigt demnach mit einem High-Low-Übergang an, dass die Spannung UC am Kondensator C den Wert der ersten Eingangsspannung U1 erreicht hat. Zur Erzeugung des Sägezahnsignals wird bei Erreichung dieses Zustands mittels eines Mono-Flip-Flops MFF eine abrupte Entladung des Kondensators C herbeigeführt. Zu diesem Zweck ist als Teil der Entladeschaltung dem Kondensator C ein Schaltelement parallel geschaltet, wobei das Mono-Flip-Flop MFF, dem das zweite Vergleichssignal SIG2OUT zugeführt ist, bei jedem High-Low-Übergang einen Einschaltimpuls mit einer Impulsdauer tFF größer der Entladezeit des Kondensators C liefert.The negative terminal of the second comparator KO2 is also connected to a capacitor C, which is charged by means of a charging circuit. The first input voltage U1 is applied to the positive terminal of the second comparator KO2, so that a second comparison signal SIG2 OUT can be removed at the output. Accordingly, this second comparison signal SIG2 OUT indicates, with a high-low transition, that the voltage UC at the capacitor C is the value of the first input voltage U1 has reached. To generate the sawtooth signal, an abrupt discharge of the capacitor C is brought about when this state is reached by means of a mono-flip-flop MFF. For this purpose, the capacitor C is a switching element connected in parallel as part of the discharge circuit, wherein the mono-flip-flop MFF to which the second comparison signal SIG2 OUT is supplied at each high-low transition a turn-on with a pulse duration t FF greater than Discharge time of the capacitor C supplies.
Damit ist folgender Zusammenhang der einzelnen Signale gegeben:This gives the following relationship of the individual signals:
Der Ladestrom i des Kondensators C mit der Kapazität C ist bekanntermaßen:
Für kurze Ladezyklen gilt:
Die Periodendauer t1 ergibt sich dann aus dem Anstieg der Spannung UC am Kondensator C bei Erreichung der ersten Eingangsspannung U1:
Entsprechend ergibt sich die Dauer des High-Signalzustandes t2 des pulsweitenmodulierten Signals bei Erreichung der zweiten Eingangsspannung:
Das Tastverhältnis des pulsweitenmodulierten Signals am Ausgang des ersten Kondensators KO1 ist somit unabhängig von den elektrischen Eigenschaften des Kondensators C und des Widerstands R bzw. des Koeffizienten K.
Am Ausgang des ersten Komparators KO1 ist ein Glättungsglied angeordnet, bestehend aus einem Glättungswiderstand RO und einem Glättungskondensator CO, wobei der Glättungskondensator CO gegen ein Bezugspotenzial der Spannungen geschaltet ist. Am Ausgang dieses Glättungsglieds liegt dann als Mittelwert des ersten Vergleichssignals SIG1OUT eine Ausgangsspannung UD als Quotient der Division an.At the output of the first comparator KO1 a smoothing member is arranged, consisting of a smoothing resistor R O and a smoothing capacitor C O , wherein the smoothing capacitor C O is connected to a reference potential of the voltages. At the output of this smoothing element is then applied as an average value of the first comparison signal SIG1 OUT an output voltage U D as a quotient of the division.
Das zweite Diagramm zeigt den Verlauf des zweiten Vergleichsignals SIG2OUT am Ausgang des zweiten Komparators KO2 über der Zeit t. Während des Spannungsanstiegs am Kondensator C liegt am Ausgang des zweiten Komparators KO2 ein High-Signalzustand an. Der High-Low-Übergang erfolgt, sobald die Spannung UC am Kondensator C den Wert der ersten Eingangsspannung U1 erreicht. Jeder High-Low-Übergang löst dabei mittels Mono-Flip-Flop MFF einen Einschaltimpuls des Schaltelements der Entladeschaltung aus, sodass die Spannung UC am Kondensator C abrupt abfällt und das zweite Vergleichssignal SIG2OUT wieder den High-Signalzustand annimmt. Die Dauer, für die das zweite Vergleichssignal SIG2OUT den Low-Signalzustand annimmt, bestimmt sich dabei aus dem Ansprechverhalten des zweiten Komparators KO2 (Response Time) und des Mono-Flip-Flops MFF. Im Dritten Diagramm sind die Einschaltimpulse am Ausgang des Mono-Flip-Flops MFF über der Zeit t dargestellt. Dabei muss die Dauer tFF jedes Einschaltimpulses mindestens so lange wie die Entladedauer des Kondensators C sein. Die Impulsdauer tFF darf die Entladedauer jedoch nicht wesentlich überschreiten, weil die dann nach Abfallen der Kondensatorspannung UC kurzzeitig auftretenden konstanten Abschnitte des Sägezahnsignals Ungenauigkeiten bei der Quotientenbildung hervorrufen. Der auftretende Fehler ist dabei umso größer, je größer die Frequenz ist. Die in
Um eine Unabhängigkeit der Frequenz des Sägezahnsignals von der ersten Eingangsspannung U1 zu erreichen, wird die Hilfsspannung der Ladeschaltung in ein fixes Verhältnis zur ersten Eingangsspannung U1 gesetzt. Eine entsprechende Schaltungsanordnung ist in
Da bei einer niedrigen Eingangsspannung U1 auch die Hilfsspannung der Ladeschaltung entsprechend niedrig ist, bleibt die Frequenz des Sägezahnsignals gegenüber einem Signal mit höherer erster Eingangsspannung U1 konstant.
Zur Vermeindung des von den Einschaltimpulsen tFF des Mono-Flip-Flops MFF verursachten Fehlers wird in der Schaltung anstelle eines Sägezahngenerators ein Dreiecksgenerator angeordnet. In
Der Kondensator C wird mittels einer Lade- und Entladeschaltung in der Weise zyklisch geladen und entladen, dass ein Dreieckssignal gegeben ist. Die Lade- und Entladeschaltung umfasst dabei ein Schaltelement, das den Kondensator C abwechselnd an eine Stromquelle mit einem Ladestrom +i1 und an eine Stromsenke mit einem Entladestrom -i2 anschaltet. Gesteuert wird dieses Schaltelement mittels eines Latch LA, auch Delay-Flip-Flop genannt, dessen erster Eingang mit dem Ausgang des zweiten Komparators KO2 und dessen zweiter Eingang mit dem Ausgang eines dritten Komparators KO3 verbunden ist. Der dritte Komparator KO3 ist dabei mit dem negativen Eingang an ein Bezugspotenzial der Spannungen geschaltet und der positive Eingang ist mit den negativen Eingängen der beiden anderen Komparatoren KO1, KO2 verbunden.The capacitor C is cyclically charged and discharged by means of a charge and discharge circuit in such a way that a triangular signal is given. The charging and discharging circuit in this case comprises a switching element which turns on the capacitor C alternately to a current source with a charging current + i1 and to a current sink with a discharge current -i2. This switching element is controlled by means of a latch LA, also called a delay flip-flop, whose first input to the output of the second comparator KO2 and whose second input is connected to the output of a third comparator KO3. The third comparator KO3 is connected to the negative input to a reference potential of the voltages and the positive input is connected to the negative inputs of the two other comparators KO1, KO2.
Das erste Eingangssignal des Latch LA weist einen High-Low-Übergang auf, wenn die Spannung UC am Kondensator C den Wert der ersten Eingangsspannung U1 erreicht. Ein High-Low-Übergang des zweiten Eingangssignals des Latch LA tritt auf, wenn die Spannung am Kondensator C den Wert des Bezugspotenzials erreicht.The first input signal of the latch LA has a high-low transition when the voltage UC across the capacitor C reaches the value of the first input voltage U1. A high-low transition of the second input signal of the latch LA occurs when the voltage across the capacitor C reaches the value of the reference potential.
In
Die entsprechenden Diagramme der Signalabfolgen bei einem Analog Dividierer mit Dreiecksgenerator sind in
Die beiden Eingangssignale des Latch LA nehmen dabei nur für die Dauer der Ansprechzeiten der entsprechenden Komparatoren KO2, KO3 die Low-Signalzustände an und gehen dann sofort wieder in den High-Signalzustand über, weil unmittelbar nach dem Ansprechen eines Komparators KO2, KO3 ein Umschalten des Schaltelements mittels Latch LA erfolgt. Die Verläufe des ersten und des zweiten Eingangssignals über der Zeit t sind im zweiten und dritten Diagramm der
Das vierte Diagramm zeigt die Anschaltzeiten der Stromquelle an den Kondensator C über der Zeit t. Die Anschaltung ON erfolgt mittels Schaltelement, sobald der zweite Eingang des Latch LA mit einem High-Low-Übergang beaufschlagt wird, wobei ein positiver Ladestrom +i1 in den Kondensator C fließt. Sobald die Kondensatorspannung UC den Wert der ersten Eingangspannung U1 erreicht, erfolgt die Abschaltung OFF. Die Abschaltung OFF von der Stromquelle ist gleichzeitig die Anschaltung ON an die Stromsenke und es fließt ein Entladestrom -i2 aus dem Kondensator C zur Stromsenke, bis die Kondensatorspannung UC den Wert des Bezugspotenzials erreicht hat. Dann erfolgt wieder eine Abschaltung OFF der Stromsenke und gleichzeitig eine Anschaltung ON der Stromquelle. Der Verlauf der Anschaltzeiten der Stromsenke an den Kondensator C ist im fünften Diagramm dargestellt.The fourth diagram shows the turn-on times of the current source to the capacitor C over the time t. The ON connection is effected by means of a switching element as soon as the second input of the latch LA is subjected to a high-low transition, with a positive charging current + i1 flowing into the capacitor C. As soon as the capacitor voltage UC reaches the value of the first input voltage U1, the switch-off occurs OFF. The shutoff OFF from the power source is at the same time the connection ON to the current sink and a discharge current -i2 flows from the capacitor C to the current sink until the capacitor voltage UC has reached the value of the reference potential. Then again a shutdown OFF the current sink and at the same time an ON connection of the power source. The course of the turn-on times of the current sink to the capacitor C is shown in the fifth diagram.
Das auf diese Weise erzeugte Dreieckssignal wird im ersten Komparator KO1 mit der zweiten Eingangsspannung U2 verglichen. Das erste Vergleichssignal SIG1OUT am Ausgang des ersten Komparators KO1 ist dann wieder ein pulsweitenmoduliertes Signal, dessen Tastverhältnis dem Quotienten der Division der zweiten Eingangsspannung U2 durch die erste Eingangsspannung U1 entspricht:
Um die Frequenz des Dreiecksignals unabhängig vom Potenzial der ersten Eingangsspannung U1 zu machen, ist eine Stromquelle und eine Stromsenke in Abhängigkeit der ersten Eingangsspannung U1 vorzusehen, beispielsweise durch zwei konstante Koeffizienten K1 und K2, die den Ladestrom +i1 und den Entladestrom -i2 in ein Verhältnis zur ersten Eingangsspannung setzen:
Für die Zeitabschnitte tS und tf einer steigenden und einer fallenden Rampe des Dreieckssignals ergeben sich konstante Werte, wenn die Kapazität des Kondensators C und die Koffizienten K1, K2 konstant sind:
Der Fehler infolge der Ansprechzeiten der Komparatoren KO2, KO3 bleibt also auch bei niedrigen ersten Eingangsspannungen konstant.The error due to the response times of the comparators KO2, KO3 thus remains constant even at low first input voltages.
Die ersten fünf Diagramme der
In gleicher Weise treten Verzögerungen durch die Ansprechzeit td-KO3 des dritten Komparators KO3 und die Ansprechzeit td-LA des Latch LA auf, wenn die abfallende Spannung UC am Kondensator C den Wert des Bezugspotenzials erreicht.In the same way, delays occur due to the response time t d-KO3 of the third comparator KO3 and the response time t d-LA of the latch LA when the falling voltage UC across the capacitor C reaches the value of the reference potential.
In Summe ergeben sich dadurch folgende Ansprechzeiten td1, td2 :
Nimmt man an, dass die Ansprechzeiten der Komparatoren KO2, KO3 ungefähr gleich lang sind (td-KO2 = td-KO3), dann ergibt sich folgende Gesamtansprechzeit pro Periodendauer t1:
Gegenüber einem fehlerfreien Quotienten t2/t1 erhält man einen fehlerbehafteten Quotienten t2/(t1-td). Der prozentuelle Fehler ((t2/t1)/(t2/(t1-td))*100%) liegt dann zum Beispiel bei 4,167%, wenn die Ansprechzeit td1 gleich 200ns ist und eine Dreieckssignalfrequenz von 100kHz angenommen wird.Compared with an error-free ratio t2 / t1 is obtained a defective ratio t2 / (t1-t d). The percentage error ((t2 / t1) / (t2 / (t1-t d)) * 100%) is then for example, at 4.167% when the
Die durch die Ansprechzeiten der Komparatoren (KO2, KO3) und des Latch (LA) hervorgerufenen Fehler werden bei einem erfindungsgemäßen Analog Dividierer vermieden.The errors caused by the response times of the comparators (KO2, KO3) and the latch (LA) are avoided in an analog divider according to the invention.
Eine beispielhafte Ausprägung der Erfindung ist in
In gleicher Weise ist dem zweiten Regler REG2 das Dreieckssignal zugeführt. Der zweite Regler REG2 vergleicht die unteren Ist-Spitzenwerte des Dreiecksignals mit einem Bezugspotenzial. Das Stellsignal SIG5OUT des zweiten Reglers REG2 wird dem dritten Komparator KO3 zum Vergleich mit dem Dreieckssignals zugeführt. Dabei werden die unteren Spitzenwerte des Dreieckssignals dem Wert des Bezugspotenzials nachgeregelt.In the same way, the second regulator REG2 is supplied with the triangular signal. The second regulator REG2 compares the lower actual peak values of the triangular signal with a reference potential. The control signal SIG5 OUT of the second regulator REG2 is supplied to the third comparator KO3 for comparison with the triangular signal. The lower peak values of the triangular signal are readjusted to the value of the reference potential.
Es ist zu beachten, dass in der Regel Komparatoren eine höhere Anstiegsrate (Slew Rate) als Operationsverstärker aufweisen. Deshalb sind Regler REG1, REG2 mit entsprechend hohen Anstiegsraten vorzusehen.It should be noted that comparators generally have a higher slew rate than operational amplifiers. Therefore, regulators REG1, REG2 with correspondingly high slew rates must be provided.
Bei der in
Der Mittelwert des Dreiecksignals wird dabei mittels eines Tiefpassfilters TPF gebildet, der dem ersten Regler REG1 vorgeschaltet ist. Der halbe Wert der ersten Eingangsspannung U1 wird mittels eines Spannungsteilers gebildet. Der Spannungsteiler umfasst dabei zwei hochohmige Widerstände R, die in Serie zwischen erster Eingangsspannung U1 und Bezugspotenzial angeordnet sind, wobei ein Verbindungspunkt zuwischen den Widerständen R mit einem Eingang des ersten Reglers REG1 verbunden ist. Ansonsten entspricht die in
Der erste Regler REG1 bildet ein Stellsignal SIG4OUT, dessen Verlauf unterhalb des Verlaufes der Eingangsspannung U1 liegt. Die Differenz zur Eingangsspannung U1 ist dabei so groß, dass die Ansprechzeiten td-KO2, td-LA des zweiten Komparators KO2 und des Latch LA kompensiert werden und die ansteigende Rampe des Dreiecksignals genau bei Erreichung des Wertes der Eingangsspannung U1 endet.The first regulator REG1 forms a control signal SIG4 OUT whose profile is below the curve of the input voltage U1. The difference to the input voltage U1 is so great that the response times td-KO2 , td -LA of the second comparator KO2 and the latch LA are compensated and the rising ramp of the triangular signal ends precisely upon reaching the value of the input voltage U1.
In gleicher Weise bildet der zweite Regler REG2 ein Stellsignal SIG4OUT, dessen Verlauf oberhalb des Verlaufes des Bezugspotenzials 0 liegt. Die Differenz zum Bezugspotenzial 0 ist dabei wiederum so groß, dass die Ansprechzeiten td-KO3, td-LA des dritten Komparators KO3 und des Latch LA kompensiert werden und die abfallende Rampe des Dreiecksignals genau bei Erreichung des Bezugspotenzials endet.In the same way, the second regulator REG2 forms a control signal SIG4 OUT whose profile is above the course of the
Damit erhält man genaue Werte für die Dauer der ansteigenden Rampe tS und die Dauer der abfallenden Rampe tf des Dreiecksignals, die in Summe eine Periodendauer t1 des Dreiecksignals ergeben, welche von den Ansprechzeiten der Komparatoren KO1, KO2 und des Latch LA unbeeinflusst ist. Mit einem auf diese Weise erzeugten Dreiecksignal erreicht die Quotientenbildung eine Genauigkeit, die weit über der eines bekannten Analog Dividieres liegt.This gives accurate values for the duration of the rising ramp t S and the duration of the falling ramp t f of the triangular signal, which together result in a period t1 of the triangular signal which is unaffected by the response times of the comparators KO1, KO2 and the latch LA. With a triangular signal generated in this way, the quotient formation achieves an accuracy far above that of a known analog divider.
Eine weitere Steigerung der Genauigkeit wird durch die Stabilisierung der beiden Signalzustände am Ausgang des ersten Komparators KO1 erreicht. Dazu wird dem ersten Komparators KO1 eine umschaltbare Referenzeinheit REF Nachgeschaltet. Am Ausgang der Referenzeinheit REF liegt dann ein referenziertes Signal SIG6OUT an, dass entsprechend dem ersten Vergleichssignal SIG1OUT am Ausgang des ersten Komparators KO1 zwischen einem referenzierten High-Wert +UREF-S und einem referenzierten Low-Wert wechselt.A further increase in accuracy is achieved by the stabilization of the two signal states at the output of the first comparator KO1. For this purpose, a switchable reference unit REF is connected downstream of the first comparator KO1. At the output of the reference unit REF is then applied to a referenced signal SIG6 OUT that changes according to the first comparison signal SIG1 OUT at the output of the first comparator KO1 between a referenced high value + U REF-S and a referenced low value.
Um die Schnelligkeit, mit welcher der Analog Dividierer auf eine Änderung einer Eingangsspannung U1, U2 reagiert, zu erhöhen, wird dem ersten Komparator bzw. der Referenzeinheit REF eine Glättungseinheit nachgeschaltet, welche zwei Tiefpassfilter TPF1, TPF2 und einen dritte Regler REG3 umfasst. Die entsprechende Schaltungsanordnung ist in
Der erste Tiefpassfilter TPF1 ist beispielsweise als sogenanntes RC-Glied mit einem ersten Widerstand R1 und einem ersten Kondensator C1 ausgebildet. Auch der zweite Tiefpassfilter TPF2 ist als ein RC-Glied mit einem zweiten Widerstand R2 und einem zweiten Kondensator C2 ausgebildet.The first low-pass filter TPF1 is formed, for example, as a so-called RC element with a first resistor R1 and a first capacitor C1. Also, the second low-pass filter TPF2 is formed as an RC element with a second resistor R2 and a second capacitor C2.
Die Grenzfrequenz fg1 des ersten Tiefpassfilters TPF1 ist dabei kleiner als die Grenzfrequenz fg2 des zweiten Tiefpassfilters TPF2 (fg2 ≈ 5 * fg1 bis 10*fg1). Die Auslegung der Grenzfrequenzen fg1, fg1 hängt dabei von der Frequenz des Dreiecksignals ab und kann in einfacher Weise ermittelt werden.The cut-off frequency f g1 of the first low-pass filter TPF1 is smaller than the cut-off frequency f g2 of the second low-pass filter TPF2 (f g2 ≈ 5 * f g1 to 10 * f g1 ). The design of the cut-off frequencies f g1 , f g1 depends on the frequency of the triangular signal and can be determined in a simple manner.
Zwischen den ersten Tiefpassfilter TPF1 und den zweiten Tiefpassfilter TPF2 ist der dritte Regler REG3 geschaltet, wobei dem dritten Regler auch die Ausgangsspannung UD als Regelgröße zugeführt ist. Der dritte Regler REG3 regelt die Ausgangsspannung UD dem mittels erstem Tiefpassfilter TPF1 geglätteten Signal SIG7OUT nach. Dabei werden die ansteigenden und abfallenden Abschnitte des geglätteten Signal SIG7OUT steiler oder flacher, wenn sich das pulsweitenmodulierten Signals am Eingang des ersten Tiefpassfilters TPF1 ändert. Diese Verstärkung der Änderungen am Eingang der Glättungseinheit bewirkt, dass sich auch die Ausgangsspannung UD schneller ändert.Between the first low-pass filter TPF1 and the second low-pass filter TPF2, the third regulator REG3 is connected, the third controller also being supplied with the output voltage U D as a controlled variable. The third regulator REG3 regulates the output voltage U D to the signal SIG7 OUT smoothed by the first low-pass filter TPF1. Here are the rising and falling portions of the smoothed signal SIG7 OUT steeper or flatter when the pulse width modulated signal at the input of the first low pass filter TPF1 changes. This amplification of the changes to the input of the smoothing unit causes the output voltage U D to change faster.
Die entsprechenden Signalverläufe sind in
Im Diagramm darunter ist der Verlauf des ersten Vergleichssignals SIG1OUT am Ausgang des ersten Komparators dargestellt. Das dritte Diagramm zeigt das entsprechende Vergleichssignal SIG6OUT am Ausgang der Referenzeinheit mit den zwei referenzierten Signalzuständen +UREF-S, O.The diagram below shows the profile of the first comparison signal SIG1 OUT at the output of the first comparator. The third diagram shows the corresponding comparison signal SIG6 OUT at the output of the reference unit with the two referenced signal states + U REF-S , O.
Das unterste Diagramm zeigt den Verlauf der Signale am Ausgang des ersten Tiefpassfilters SIG7OUT um am Ausgang des zweiten Tiefpassfilters UD. Das geglättete Signal SIG7OUT am Ausgang des ersten Tiefpassfilters TPF1 weist ausgeprägte abfallende und ansteigende Abschnitte auf, wohingegen die Ausgangsspannung UD am Ausgang des zweiten Tiefpassfilters TPF2 nahezu vollständig geglättet ist.The bottom diagram shows the course of the signals at the output of the first low-pass filter SIG7 OUT at the output of the second low-pass filter U D. The smoothed signal SIG7 OUT at the output of the first low-pass filter TPF1 has pronounced falling and rising portions, whereas the output voltage U D at the output of the second low-pass filter TPF2 is almost completely smoothed.
Claims (11)
- Method for operating an analogue divider, wherein a saw tooth or triangle signal is formed, for the generation of which a first input voltage (U1) is predefined as divisor and a reference potential, and wherein said saw tooth or triangle signal is compared by means of a first comparator (KO1) with a second input voltage (U2) as dividend in such a manner that a pulse width modulated signal is generated as a first comparison signal (SIGIOUT), the average value of which is output as quotient of the division, characterised in that the saw tooth or triangle signal is formed by means of a first and second regulator (REG1, REG2) and the first input voltage (U1) or a voltage proportional thereto and the saw tooth or triangle signal or a signal proportional thereto are supplied to the first regulator (REG1) in such a manner that the upper peak value of the saw tooth or triangle signal is re-adjusted to the first input voltage and the reference potential and the saw tooth or triangle signal are also supplied to the second regulator (REG2) in such a manner that the lower peak value of the saw tooth or triangle signal is re-adjusted to the value of the reference potential and the first comparison signal (SIGIOUT) is smoothed by means of a first and second low-pass filter (TPF1, TPF2) and an output voltage (UD) present at the output of the second low-pass filter (TPF2) is re-adjusted by means of a third regulator (REG3) to a smoothed signal (SIG7OUT) at the output of the first low-pass filter (TPF1).
- Method according to claim 1, characterised in that a control signal (SIG4OUT) is formed as upper target peak value by means of first regulator (REG1) and said control signal (SIG4OUT) is supplied to a second comparator (K02) for comparison with the saw tooth or triangle signal, also a control signal (SIGSOUT) is formed as lower target peak value by means of second regulator (REG2) and said control signal (SIG5OUT) is supplied to a third comparator (K03) for comparison with the saw tooth or triangle signal and the second comparison signal (SIG2OUT) at the output of the second comparator (K02) and the third comparison signal (SIG3OUT) at the output of the third comparator (K03) are supplied to a controller, by means of which the charging and discharging of a capacitor are controlled to form the saw tooth or triangle signal.
- Method according to claim 2, characterised in that the control signal (SIG4OUT) of the first regulator (REG1) is formed from the deviation of the upper actual peak value of the saw tooth or triangle signal from the first input voltage (U1) and the control signal (SIG5OUT) of the second regulator (REG2) is formed from the deviation of the lower actual peak value of the saw tooth or triangle signal from the reference potential.
- Method according to claim 2, characterised in that the control signal (SIG4OUT) of the first regulator (REG1) is formed from the deviation of the saw tooth or triangle signal averaged by means of the low-pass filter from half the first input voltage (U1) and the control signal (SIG5OUT) of the second regulator (REG2) is formed from the deviation of the lower actual peak value of the saw tooth or triangle signal from the reference potential.
- Analogue divider, to which a first input voltage (U1) is supplied as divisor and a second input voltage (U2) is supplied as dividend and which comprises a saw tooth or triangle generator, to which the first input voltage (U1) is predefined as upper peak value of a generated saw tooth or triangle signal, wherein the output of the saw tooth or triangle generator is connected to an input of a first comparator (KO1), to which the second input voltage (U2) is also supplied, so that at the output of the first comparator (KO1) a pulse width modulated signal is present as first comparison signal (SIG1OUT) of the saw tooth or triangle signal and the second input voltage (U2) and is supplied to a smoothing unit, at the output of which the averaged pulse width modulated signal is present as quotient of the division and can be tapped as output voltage (UD), characterised in that the saw tooth or triangle generator comprises a first regulator (REG1), to which the first input voltage (U1) or a voltage proportional thereto and the saw tooth or triangle signal are supplied as input signals and the control signal (SIG4OUT) of which is supplied to a second comparator (K02), which compares the saw tooth or triangle signal with the control signal (SIG4OUT) of the first regulator (REG1) and at the output of which a second comparison signal is present (SIG2OUT), the saw tooth or triangle generator also comprises a second regulator (REG2), at the input of which the reference potential is present and to which the saw tooth or triangle signal is supplied and the control signal (SIG5OUT) of which is supplied to a third comparator (K03), which compares the saw tooth or triangle signal with the control signal (SIGSOUT) of the second regulator (REG2) and at the output of which a third comparison signal (SIG3OUT) is present and the second and third comparison signals (SIG2OUT, SIG3OUT) are supplied to a controller, which switches a charging circuit and a discharging circuit in an alternating manner to a capacitor (C) to form the saw tooth or triangle signal and the first comparison signal (SIG1OUT) is supplied by way of a first low-pass filter (TPF1) to a third regulator (REG3), the output of which is connected to a second low-pass filter (TPF2) and the output voltage (UD) present at the output of the second low-pass filter (TPF2) is in turn supplied to the third regulator (REG3) as controlled variable.
- Analogue divider according to claim 5, characterised in that the first input voltage (U1) and the saw tooth or triangle signal are supplied to the first regulator (REG1) to form the control signal (SIG4OUT).
- Analogue divider according to claim 5, characterised in that half the first input voltage (U1) is supplied to the first regulator (REG1) in such a manner that the first input voltage (U1) is switched by way of a voltage divider to the first regulator (REG1) and a saw tooth or triangle signal averaged by means of low-pass filter is also supplied to the first regulator (REG1).
- Analogue divider according to one of claims 5 to 7, characterised in that the controller comprises a latch (LA), to which the second and third comparison signals (SIG2OUT, SIG3OUT) are supplied and by means of which a switching element is actuated, which connects the capacitor (C) in an alternating manner to a positive current source (+i1) and a negative current source (-i2).
- Analogue divider according to claim 8, characterised in that the current source supplies a positive current (+i1), which is formed from the first input voltage (U1) times a positive coefficient and the current sink supplies a negative current (-i2), which is formed from the first input voltage (U1) times a negative coefficient.
- Analogue divider according to one of claims 5 to 8, characterised in that the controller comprises a latch (LA), to which the second and third comparison signals (SIG2OUT, SIG3OUT) are supplied and by means of which a switching element is actuated, which connects the capacitor (C) in an alternating manner to a positive voltage source and a negative voltage source by way of a resistor and the resistor and capacitor (C) are wiring elements of an operation amplifier configured as integrator, at the output of which the saw tooth or triangle signal is present.
- Analogue divider according to one of claims 5 to 10, characterised in that a switchable reference unit REF is connected downstream of the first comparator (KO1).
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2007
- 2007-06-19 AT AT9432007A patent/AT505446B1/en not_active IP Right Cessation
-
2008
- 2008-04-22 EP EP20080103649 patent/EP2012250B1/en not_active Not-in-force
Also Published As
Publication number | Publication date |
---|---|
AT505446B1 (en) | 2009-08-15 |
AT505446A1 (en) | 2009-01-15 |
EP2012250A2 (en) | 2009-01-07 |
EP2012250A3 (en) | 2011-10-12 |
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