EP1825340A2 - Adaptiver digitaler spannungsregler - Google Patents
Adaptiver digitaler spannungsreglerInfo
- Publication number
- EP1825340A2 EP1825340A2 EP05852550A EP05852550A EP1825340A2 EP 1825340 A2 EP1825340 A2 EP 1825340A2 EP 05852550 A EP05852550 A EP 05852550A EP 05852550 A EP05852550 A EP 05852550A EP 1825340 A2 EP1825340 A2 EP 1825340A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- time
- duty cycle
- output voltage
- voltage error
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/618—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series and in parallel with the load as final control devices
Definitions
- the invention pertains generally to the field of power conversion, and more particularly to digitally-controlled switched-mode DC/DC converters.
- a broad class of switched-mode DC/DC power converters exists with the property that the ratio of the average output voltage to the input voltage is determined by the average duty cycle of a controllable switching device within the power conversion stage of the converter. Examples include buck, boost, inverting buck-boost, forward, and flyback converters, operated in the continuous conduction mode (CCM).
- CCM continuous conduction mode
- regulation of these converters is accomplished by continually estimating the output voltage error (the output voltage error being the difference between the uncorrupted output voltage and the desired output voltage) and continually adjusting the duty cycle of the switching device to compensate for changes in load conditions manifest in output voltage error estimates.
- the act of regulation consists of controlling, cycle by cycle, the duty cycle of the switching device in accordance with output voltage error estimates, so that the amplitude of the output voltage error is continually minimized.
- PWM pulse width modulation
- Duty cycle control mechanisms generally incorporate a mechanism for estimating the target duty cycle (the target duty cycle being the duty cycle essential to achieve the desired output voltage).
- a target duty cycle estimation mechanism is commonly a feedback mechanism, driven by the output voltage error, but it could as well be a feedforward mechanism, driven by the input voltage, or some combination of the two.
- pulse width control mechanisms are analog in nature; that is they accept as input a continuously variable analog signal representing the desired duty cycle, and they output pulses of continuously variable width.
- continuous advances in integrated circuit technology have stimulated the application of digital techniques to the field of power conversion.
- the first digital PWM regulation mechanisms replacing analog PWM regulators, have been developed and are being commercialized. It is the nature of such mechanisms that the generated pulse widths are quantized - a consequence of the temporal resolution of the digital regulation mechanism. If the temporal resolution of the regulation mechanism is
- the pulse widths are constrained to be integral multiples of ⁇ t.
- the duty cycle control mechanism examines the current output voltage error estimate, and if it is positive, selects the smaller duty cycle for the next cycle of the switching device. Similarly, if the current output voltage error estimate is negative, it selects the larger duty cycle for the next cycle of the switching device. At its best, however, this duty cycle control mechanism may not be able to limit output voltage ripple to an acceptable level...in which case the only obvious recourse for manufacturers of regulators is to improve the temporal resolution of the regulation mechanism...i.e., boost the clock frequency.
- ripple Even if the ripple is tolerable under static line and load conditions, it may present a challenge to tight regulation under dynamic load conditions, owing to the difficulty in providing accurate output voltage feedback in the presence of increased (though tolerable) ripple.
- the only obvious recourse to manufacturers of regulators to minimize ripple without penalizing dynamic performance is to boost the clock frequency.
- boosting the clock frequency to mitigate the effects of quantization on output voltage error may compromise cost and efficiency metrics. For example, the complexity and, consequently, the cost of the digital regulation mechanism are likely to increase as well as the power dissipation. Moreover, the increased cost and power dissipation will be further multiplied, if the requirement to boost the clock frequency should prevent the integration (at a substrate level) of the digital regulation mechanism with other electronic componentry.
- the primary objective of this invention is to provide digital control methods that mitigate the requirement for higher clock frequencies solely for the purpose of achieving acceptable output voltage error (static and dynamic) in a broad class of DC/DC converters.
- a digital duty cycle control mechanism including a mechanism for estimating the output voltage error; a mechanism for estimating the target duty cycle, a novel duty cycle quantization mechanism for determining a first set of one or more quantized ON time/OFF time pairs for regulating the output voltage, and a novel output- voltage-error-driven selector mechanism for determining the turn ON and turn OFF times of the switching device by choosing, cycle by cycle, from a second set of two or more quantized ON time/OFF time pairs, derived from the first set, is disclosed.
- the novelty of the duty cycle quantization mechanism follows from the insight that the output voltage ripple resulting from a sequence of quantized switching cycles (a cycle being the sum of consecutive ON and OFF times) decreases as the number of quantized switching cycles available to generate the sequence increases; and that the number available can be expanded by relaxing the (prior art) premise that all switching cycles be fixed in length, cycle by cycle, under nominal load conditions. If, for example, the switching cycle were allowed to shrink/stretch by the temporal resolution of the digital regulation mechanism, the number of available switching cycles increases three-fold, with the potential for comparable reductions in output voltage ripple.
- the novelty of the selector mechanism follows from the insight that in a temporally quantized switching environment, the feedback mechanism controlling the switch is fundamentally limited in the amount of useful information it can provide at each cycling of the switch.
- a digital regulation mechanism practicing conventional fixed-frequency pulse width modulation may provide as little as four bits, cycle by cycle.
- instantaneous output voltage error feedback must be available, even if its reliability is limited to 1 bit, to operate effectively in a temporally quantized environment.
- a duty cycle quantization mechanism for determining, from an estimated target duty cycle, a first set of one or more quantized ON time/OFF time pairs for regulating the output voltage, and in a novel output-voltage- error-driven selector mechanism for determining the turn ON and turn OFF times of the switching device by choosing, cycle by cycle, from a second set of two or more quantized ON time/OFF time pairs, derived from the first set, the ripple induced by quantization as well as the delay in the feedback path are reduced.
- the choosing of ON time/OFF time pairs means that the choice can be broken into two choices: ON time and OFF time; and that feedback measured during the ON time AND during the OFF time may be applied virtually instantaneously to regulate the output voltage.
- a method for converting an input voltage to an output voltage by means of a switched-mode DC/DC converter; the input voltage being converted into an output voltage with the aid of a power stage, including at least one controllable switch, which is turned ON and turned OFF by a control device
- a duty cycle control mechanism for controlling the duty cycle of the controllable switching device, the duty cycle control mechanism including a mechanism for estimating the output voltage error; a mechanism for estimating the target duty cycle; a duty cycle quantization mechanism for determining, for a target duty cycle estimate, a first set of quantized ON time/OFF time pairs suitable for controlling said controllable switching device, characterized in that the quantized ON time and OFF time of each pair (in said first set) are determined independently of each other; that is, the sum of the ON time and OFF time is not fixed; and may vary, pair to pair, constrained to a set
- output-voltage-error-driven selector mechanism for determining the turn ON and turn OFF times of said controllable switching device by choosing, cycle by cycle, an ON time/OFF time pair from a second set of quantized ON time/OFF time pairs, derived from said first set, choosing in such a manner that the amplitude of the output voltage error is continually minimized.
- a switched-mode DC/DC converter comprising;
- a power stage for the purpose of converting an input voltage into at least one output voltage, the power stage including at least one controllable switching device; and a control device for the purpose of turning ON and turning OFF the controllable switching device, characterized in that owing to the temporal resolution of the control
- both the turn ON and turn OFF times of the controllable switching device are
- a duty cycle control mechanism for controlling the duty cycle of said controllable switching device, comprising:
- a duty cycle quantization mechanism for determining, for a target duty cycle estimate, a first set of at least one quantized ON time/OFF time pair suitable for controlling said controllable switching device, characterized in that the quantized ON time and OFF time of each pair (in said first set) are determined independently of each other; that is, the sum of the ON time and OFF time is not fixed; and may vary, pair to pair, constrained to a set
- an output- voltage-error-driven selector mechanism for determining the turn ON and turn OFF times of said controllable switching device by choosing, cycle by cycle, an ON time/OFF time pair from a second set of at least two quantized ON time/OFF time pairs, derived from said first set, choosing in such a manner that the amplitude of the output voltage error is continually minimized.
- the selector mechanism determines turn ON and turn OFF times by choosing, cycle by cycle, an ON time/OFF time pair from a set of two quantized ON time/OFF time pairs, extracted from a table (of sets) indexed by the estimated target duty cycle; choosing the ON time/OFF time pair with the lower implied duty cycle when the output voltage error estimate is positive (i.e., the output voltage is higher than the desired output voltage), and the pair with the higher implied duty cycle when the output voltage error estimate is negative.
- the selector mechanism determines turn ON and turn OFF times by choosing, cycle by cycle, an ON time/OFF time pair from a set of three quantized ON time/OFF time pairs, generated by the selector mechanism from a quantized ON time/OFF time pair generated by the duty cycle quantization mechanism; choosing the ON time/OFF time pair with the lowest implied duty cycle when the output voltage error estimate is highest, and the pair with the highest implied duty cycle when the output voltage error estimate is lowest, and the remaining pair when the output voltage error is neither highest nor lowest .
- the selector mechanism determines turn ON and turn OFF times by choosing, cycle by cycle, an ON time/OFF time pair from a set of six quantized ON time/OFF time pairs, generated by the selector mechanism from a quantized ON time/OFF time pair generated by the duty cycle quantization mechanism; choosing the ON time/OFF time pair with the lowest implied duty cycle when the output voltage error estimate is highest, and the pair with the highest implied duty cycle when the output voltage error estimate is lowest, and one of the remaining intermediate pairs when the output voltage error is one of the corresponding intermediate values.
- the digital duty cycle control mechanism of the present invention may be implemented in mixed signal circuitry including logic circuits and/or a microprocessor with appropriate software or firmware. Further, those skilled in the art will understand that the digital duty cycle control mechanism of the present invention may be applied to any DC/DC converter topology, including but not limited to buck, boost, inverting buck-boost, forward, and flyback converters.
- Fig. 1 is a block diagram illustrating a prior art digital duty cycle control mechanism.
- Fig. 2 is a block diagram illustrating a digital duty cycle control mechanism according to the present invention.
- Fig. 3 is a block diagram illustrating one embodiment of a digital duty cycle control mechanism according to the present invention.
- Fig. 4 is a block diagram illustrating a second embodiment of a digital duty cycle control mechanism according to the present invention.
- Fig. 5 is a block diagram illustrating a third embodiment of a digital duty cycle control mechanism according to the present invention.
- Fig. 6 is a table of variable-frequency duty cycle pairs indexed by the estimated target duty cycle.
- a broad class of switched-mode DC/DC power converters exists with the property that the ratio of the average output voltage to the input voltage is determined by the average duty cycle of a controllable switching device within the power conversion stage of the converter.
- Examples include buck, boost, inverting buck-boost, forward, and flyback converters, operated in the continuous conduction mode (CCM).
- CCM continuous conduction mode
- regulation of these converters is accomplished by continually estimating the output voltage error (the output voltage error being the difference between the uncorrupted output voltage and the desired output voltage) and continually adjusting the duty cycle of the switching device to compensate for changes in load conditions manifest in output voltage error estimates.
- the act of regulation consists of controlling, cycle by cycle, the duty cycle of the switching device in accordance with output voltage error estimates, so that the amplitude of the output voltage error is continually minimized.
- Regulation mechanisms for this purpose generally incorporate a pulse width control mechanism and a duty cycle control mechanism, where the former generates the ON pulse appropriate to the realization of the duty cycle generated by the latter.
- Duty cycle control mechanisms thus incorporate a mechanism for estimating the target duty cycle (the target duty cycle being the duty cycle essential to achieve the desired output voltage).
- a target duty cycle estimation mechanism is commonly a feedback mechanism, driven by the output voltage error, but it could as well be a feedforward mechanism, driven by the input voltage, or it could be some combination of the two.
- pulse width control mechanisms are analog in nature; that is they accept as input a continuously variable analog signal representing the desired duty cycle, and they output pulses of continuously variable width.
- continuous advances in integrated circuit technology have stimulated the application of digital techniques to the field of power conversion.
- the first digital PWM regulation mechanisms replacing analog PWM regulators, have been developed and are being commercialized. It is the nature of such mechanisms that the generated pulse widths are quantized - a consequence of the temporal resolution of the digital regulation mechanism. If the temporal resolution of the regulation mechanism is
- the pulse widths are constrained to be integral multiples of ⁇ t.
- Figure 1 describes a prior art switched-mode DC/DC power converter (cf. US Patent 6.677.733) comprising power stage 100 for the purpose of converting input voltage Vin to output voltage Vout; fixed-frequency control device 150 for the purpose of turning ON and turning OFF the controllable switching device 110, included in power stage 100; and duty cycle control mechanism 200 for controlling the duty cycle of switching device 110.
- power stage 100 for the purpose of converting input voltage Vin to output voltage Vout
- fixed-frequency control device 150 for the purpose of turning ON and turning OFF the controllable switching device 110, included in power stage 100
- duty cycle control mechanism 200 for controlling the duty cycle of switching device 110.
- control device 150 is a fixed-frequency control device, it turns ON switching device 110 at fixed intervals, Ts w. Control device 150 turns OFF switching device 110 by translating (if necessary) duty cycle input into ON time, cycle by cycle.
- the duty cycle control mechanism is comprised of an output voltage error estimator 230, a mechanism for generating, from an output voltage error signal, an estimate of the uncorrupted output voltage error, and an output-voltage-error-driven duty cycle selector 250 for determining the turn ON and turn OFF times of switching device 110, in such a manner that the amplitude of the output voltage error is continually minimized.
- the output voltage error estimator frequently takes the form of a digital PID (proportional-integral-differential) filter, operating on an output voltage error signal.
- PID filters provide the possibility of trading off delay for improved signal- to-noise ratio. Where delay must be minimized, a bi- valued output voltage error estimate derived via a binary comparator may be appropriate. Such is the nature of output voltage error estimator 230.
- the estimate of the output voltage error is sampled by duty cycle selector 250 at the end of every switching cycle, and the value applied to select the duty cycle of the next switching cycle, thereby determining turn ON and turn OFF times of switching device 110.
- the duty cycle selector 250 chooses, cycle by cycle, Dmin or Dmax (Dmin and Dmax having been specified to span a range of input voltage specific to the application); choosing Dmin when the output voltage error estimate is positive (i.e., the uncorrupted output voltage is higher than the desired output voltage), and Dmax when the output voltage error estimate is negative.
- Figure 2 describes a switched-mode DC/DC power converter according to the present invention, comprising power stage 101 for the purpose of converting input voltage Vin to output voltage Vout; control device 151 for the purpose of turning ON and turning OFF the controllable switching device 112, included in power stage 101; and duty cycle control mechanism 201 for controlling the duty cycle switching device 111.
- the control device 151 is further characterized in that, owing to the temporal resolution
- control device are constrained to be integral multiples of ⁇ t. Because control device
- 151 is not a fixed-frequency control device, it must input ON times and OFF times in order to turn ON and turn OFF switching device 111.
- the target duty cycle estimator 231 frequently takes the form of a digital PID (proportional-integral-differential) filter, operating on an output voltage error signal.
- the filter may operate on an input voltage signal in lieu of or in addition to the output voltage error signal.
- the output voltage error estimator 231 is frequently implemented as a PID filter.
- PID filters provide the possibility of trading off delay for improved signal-to-noise ratio. Where delay must be minimized, even at the price of a limited reliability output voltage error estimate, a bi- valued or tri-valued output voltage error estimate derived via binary or ternary comparators is simple and effective. Such is the nature of output voltage error estimator 231.
- the output- voltage-error-driven duty cycle selector 211 chooses the duty cycle based on samples of the output voltage error estimate taken during the ON time or the OFF time or both.
- duty cycle selector 211 chooses the duty cycle based on samples of the output voltage error estimate taken during the ON time
- the estimate of the output voltage error is sampled by duty cycle selector 211 after the switching cycle has begun but before the choice of duty cycle has been determined, and applied (by duty cycle selector 211) in time to effect the turn OFF implicit in the chosen duty cycle.
- the output voltage error estimate may be derived straightforwardly by sampling a binary or ternary comparator.
- the ideal error sampling time may be determined from the ON times of DQl and DQK; specifically, the sampling time relative to the start of the switching
- the first sample could be taken !/4(OFFl + OFFK) after the turn OFF time (prior to the start of a switching cycle), and the second sample '/4(0Nl + ONK) after the succeeding turn ON time (marking the start of a switching cycle), enabling an output voltage error estimate to be constructed and a duty cycle chosen in time to effect the turn OFF implicit in the chosen duty cycle. If both of these samples are positive, the error estimate is positive; if both samples are negative, the error estimate is negative. If one sample is positive and the other negative, the error estimate is zero in the case of a tri-valued estimate, or unchanged from the previous value in the case of a bi-valued estimate.
- duty cycle selector 211 chooses the duty cycle based on samples of the output voltage error estimate taken during the ON time AND AGAIN during the OFF time
- the estimate of the output voltage error is sampled by duty cycle selector 211 ONCE after the switching cycle has begun but before the turn OFF time has been determined, and sampled AGAIN after the turn OFF time but before the final determination of duty cycle, and its implied turn ON time.
- the duty cycle selector 211 applies the first sample to limit the choice of duty cycles, and in so doing determines the turn OFF time; and applies the second sample to choose, finally, the duty cycle, and in so doing determines the turn ON time, marking the end of the switching cycle.
- sampling times may be determined from the ON and OFF times of DQl and DQK.
- the first sampling time, relative to the start of the switching cycle, is 1 A (ONl +0NK) rounded down (if necessary) to the nearest
- the duty cycle selector 211 chooses, cycle by cycle, a duty cycle from the set DQk (and its corresponding ON time/OFF time pair); choosing DQl when the aggregate output voltage error estimate is highest, DQK when the aggregate output voltage error estimate is lowest, and one of the remaining intermediate duty cycles when the aggregate output voltage error is one of the corresponding intermediate values.
- the determination of the set DOJ for a given value of DT is accomplished by the variable-frequency duty cycle quantizer 221 via a two-step process, the first step being the enumeration of quantized duty cycles in the neighborhood of DT, and the second step being the selection of DQj from the enumerated possibilities.
- the systematic enumeration of quantized duty cycles is accomplished by generating a set of quantized ON time/OFF time pairs characterized in that the quantized ON and OFF times of each pair (in the set) are determined independently of each other; that is, the sum of the ON time and OFF time is not fixed; and may vary, pair to pair, constrained to a set of discrete
- quantized pairs is trivially transformed into a set of quantized duty cycles. More switching cycle possibilities translates to more duty cycle possibilities, making it possible to select duty cycles DOj closer to DT, a critical factor in the minimization of quantization-induced output voltage ripple.
- the determination of the second set of duty cycles DQk from the first set DOj 5 is accomplished by the duty cycle selector 211 via a two-step process, the first step being the extension of the set DOj, and the second step being the selection of DQk from the extension of set DQj .
- the number of elements of set XDQj should be large enough so that the largest duty cycle in the set is large enough to compensate for the effects of parasitics at high load.
- the computation of XDQj must be done as often as DQj changes.
- the working set of duty cycles, DQk may be determined statically or dynamically; that is to say DQk may be a prescribed subset of XDQj, or it may be dynamically "mapped" to a generally contiguous subset of XDQj, determined by the load.
- the number of elements in this subset, K is in either case determined by the logic of the duty cycle selector.
- duty cycle selector 211 chooses the duty cycle based on binary or ternary samples of the output voltage error estimate taken during the ON time or the OFF time
- the number of elements, K is 2 or 3; in the case that duty cycle selector 211 chooses the duty cycle based on binary or ternary samples of the output voltage error estimate taken during both the ON time and the OFF time, the number of elements, K, ranges from 4 to 9.
- K 2
- the prescribed subset of XDQj namely XDQl and XDQJJ, may generate intolerable output voltage ripple. This could be an artifact of the effect of parasitics, necessitating a significantly higher duty cycle at high load than at low load.
- a mechanism for dynamically determining DQk is useful.
- a count of the excess of DQl 's over DQ2's or of DQ2's over DQl 's, in a window could be used to adjust DQl and DQ2. Both of these mechanisms could be adapted for other values of K.
- variable-frequency duty cycle quantization same-cycle output voltage feedback
- dynamic determination of the working set of duty cycles to compensate for the load-dependent effects of parasitics significantly improve static and dynamic performance, at minimal computational cost. While the duty cycle control mechanism described above has implicit performance limitations similar in nature to those of prior art duty cycle control mechanisms, the effects of duty cycle quantization on performance are substantially reduced, without introducing application dependencies.
- Figure 3 describes a switched-mode DC/DC power converter according to the present invention, comprising power stage 102 for the purpose of converting input voltage Vin to output voltage Vout; control device 152 for the purpose of turning ON and turning OFF the controllable switching device 112, included in power stage 102; and duty cycle control mechanism 202 for controlling the duty cycle of switching device 112.
- the control device 152 is further characterized in that, owing to the temporal resolution
- control device both the turn ON and turn OFF times of the controllable switching device are constrained to be integral multiples of ⁇ t.
- 152 is not a fixed-frequency control device, it must input ON times and OFF times in order to turn ON and turn OFF switching device 112.
- the duty cycle control mechanism is comprised of a target duty cycle estimator/output voltage error estimator 232, a mechanism for estimating, from an output voltage error signal or an input voltage signal or a combination of both, the target duty cycle, DT, and the uncorrupted output voltage error, VE; and an output-voltage-error-driven duty cycle selector 252, for determining the turn ON and turn OFF times of switching device 112 by choosing, cycle by cycle, a quantized duty cycle (and its corresponding quantized ON time/OFF time pair) from a pair of quantized duty cycles (DQmin and DQmax bracketing DT), extracted from a table of duty cycle pairs 242, indexed by the estimated target duty cycle, DT; choosing in such a manner that the amplitude of the output voltage error is continually minimized.
- a target duty cycle estimator/output voltage error estimator 232 a mechanism for estimating, from an output voltage error signal or an input voltage signal or a combination of both, the target duty cycle, DT, and the uncorrupt
- the target duty cycle estimator 232 frequently takes the form of a digital PID (proportional-integral-differential) filter, operating on an output voltage error signal.
- the filter may operate on an input voltage signal in lieu of or in addition to the output voltage error signal.
- the output voltage error estimator 232 is frequently implemented as a PID filter.
- PID filters provide the possibility of trading off delay for improved signal-to-noise ratio. Where delay must be minimized, a bi-valued output voltage error estimate derived via a binary comparator is simple and effective. Such is the nature of output voltage error estimator 232.
- duty cycle control mechanism 202 the output voltage error is sampled by duty cycle selector 252 after the switching cycle has begun but before the choice of duty cycle has been determined, and applied (by duty cycle selector 252) in time to effect the turn OFF implicit in the chosen duty cycle.
- the output voltage error estimate may be derived straightforwardly by sampling a binary comparator.
- the ideal error sampling time may be determined from the ON times of DQmin and DQmax; specifically, the sampling time relative to the start of the switching cycle is % (ONmin + ONmax), rounded down (if necessary) to the
- a bi-valued output voltage error estimate is most easily constructed from two bi-valued samples of the error voltage, separated in time but specified such that in the steady state, one sample would normally be positive and the other negative.
- the first sample could be taken %(0FFmin + OFFmax) after the turn OFF time (prior to the start of a switching cycle), and the second sample '/4(ONnUn + ONmax) after the succeeding turn ON time (marking the start of a switching cycle), enabling an output voltage error estimate to be constructed and a duty cycle chosen in time to effect the turn OFF implicit in the chosen duty cycle. If both of these samples are positive, the error estimate is positive; if both samples are negative, the error estimate is negative. If one sample is positive and the other negative, the error estimate is unchanged from the previous value.
- the duty cycle selector 252 chooses, cycle by cycle, DQmin or DQmax (and its corresponding ON time/OFF time pair), DQmin and DQmax having been extracted from table 242, indexed by DT; choosing DQmin when the output voltage error estimate is positive (i.e., the uncorrupted output voltage is higher than the desired output voltage), and DQmax when the output voltage error estimate is negative.
- the determination of DQmin and DQmax for a given value of DT is a two-step process, the first step being the enumeration of quantized duty cycles in the neighborhood of DT, and the second step being the selection of DQmin and DQmax from the enumerated possibilities.
- the systematic enumeration of quantized duty cycles is accomplished by generating a set of quantized ON time/OFF time pairs characterized in that the quantized ON and OFF times of each pair (in the set) are determined independently of each other; that is, the sum of the ON time and OFF time is not fixed; and may vary, pair to pair,
- DQmin and DQmax are derived trivially.
- Figure 4 describes a switched-mode DC/DC power converter according to the present invention, comprising power stage 103 for the purpose of converting input voltage Vin to output voltage Vout; control device 153 for the purpose of turning ON and turning OFF the controllable switching device 113, included in power stage 103; and duty cycle control mechanism 203 for controlling the duty cycle of switching device 113.
- the control device 153 is further characterized in that, owing to the temporal resolution
- control device are constrained to be integral multiples of ⁇ t. Because control device
- 153 is not a fixed-frequency control device, it must input ON times and OFF times in order to turn ON and turn OFF switching device 113.
- the duty cycle control mechanism is comprised of a target duty cycle estimator/output voltage error estimator 233, a mechanism for estimating, from an output voltage error signal or an input voltage signal or a combination of both, the target duty cycle, DT, and the uncorrupted output voltage error, VE; a variable-frequency duty cycle quantizer 223 for determining the quantized duty cycle DQ closest to the target duty cycle estimate, DT; and an output- voltage-error-driven duty cycle selector 213, a mechanism for determining the turn ON and turn OFF times of switching device 113 by generating, for each value of DQ, a set of three quantized duty cycles (DQmin, DQ, and DQmax, ordered from lowest to highest) and by choosing, cycle by cycle, DQmin or DQ or DQmax (and its corresponding ON time/OFF time pair), choosing in such a manner that amplitude of the output voltage error is continually minimized.
- a target duty cycle estimator/output voltage error estimator 233 a mechanism for estimating, from
- the target duty cycle estimator 233 frequently takes the form of a digital PID (proportional-integral-differential) filter, operating on an output voltage error signal.
- the filter may operate on an input voltage signal in lieu of or in addition to the output voltage error signal.
- the output voltage error estimator 233 is frequently implemented as a PID filter.
- PID filters provide the possibility of trading off delay for improved signal-to-noise ratio. Where delay must be minimized, and dynamic response is important, a tri-valued output voltage error estimate derived via a ternary comparator (a binary comparator with a dead zone) is simple and effective. Such is the nature of output voltage error estimator 233.
- duty cycle control mechanism 203 the estimate of the output voltage error is sampled by duty cycle selector 213 after the switching cycle has begun but before the choice of duty cycle has been determined, and applied (by duty cycle selector 213) in time to effect the turn OFF implicit in the chosen duty cycle.
- the output voltage error estimate may be derived straightforwardly by sampling a ternary comparator.
- the ideal sampling time may be determined from the ON times of DQmin and DQmax; specifically, the sampling time relative to the start of the switching cycle is 1 A (ONmin + ONmax), rounded down (if necessary) to the nearest multiple of ⁇ t.
- the computation of the sampling time must be done as often as DQ
- tri-valued output voltage error estimate could also be constructed from two bi-valued error samples separated in time but specified such that in the steady state, one sample would normally be positive and the other negative.
- a tri-valued output voltage error estimate is most easily constructed from two bi-valued samples of the error voltage, separated in time but specified such that in-the steady state, one sample would normally be positive and the other negative.
- the first sample could be taken %(OFFmin + OFFmax) after the turn OFF time (prior to the start of a switching cycle), and the second sample !/4(0Nmin + ONmax) after the succeeding turn ON time (marking the start of a switching cycle), enabling an output voltage error estimate to be constructed and a duty cycle chosen in time to effect the turn OFF implicit in the chosen duty cycle. If both of these samples are positive, the error estimate is positive; if both samples are negative, the error estimate is negative. If one sample is positive and the other negative, the error estimate is zero (neither positive nor negative).
- the duty cycle selector 213 chooses, cycle by cycle, DQmin or DQ or DQmax (and its corresponding ON time/OFF time pair); choosing DQmin when the output voltage error estimate is positive (i.e., the uncorrupted output voltage is higher than the desired output voltage), DQmax when the output voltage error estimate is negative, and DQ when the output voltage error estimate is zero (neither positive nor negative).
- the determination of DQ for a given value of DT is accomplished by the variable- frequency duty cycle quantizer 223 via a two-step process, the first step being the enumeration of quantized duty cycles in the neighborhood of DT, and the second step being the selection of DQ from the enumerated possibilities.
- the systematic enumeration of quantized duty cycles is accomplished by generating a set of quantized ON time/OFF time pairs characterized in that the quantized ON and OFF times of each pair (in the set) are determined independently of each other; that is, the sum of the ON time and OFF time is not fixed; and may vary, pair to pair, constrained to a set of discrete values
- the tri-valued output voltage error estimate determines the ON time, adjusting ONq by -1, O, or +1 clocks.
- the OFF time is determined implicitly by adjusting OFFq in the opposite direction.
- a second simple and cost effective option is to set: and:
- the tri-valued output voltage error estimate determines the ON time, adjusting ONq by -1, O, or O clocks.
- the OFF time is determined by adjusting OFFq by O, O, or -1.
- Figure 5 describes a switched-mode DC/DC power converter according to the present invention, comprising power stage 104 for the purpose of converting input voltage Vin to output voltage Vout; control device 154 for the purpose of turning ON and turning OFF the controllable switching device 114, included in power stage 104; and duty cycle control mechanism 204 for controlling the duty cycle of switching device 114.
- the control device 154 is further characterized in that, owing to the temporal resolution
- control device are constrained to be integral multiples of ⁇ t. Because control device
- 154 is not a fixed-frequency control device, it must input ON times and OFF times in order to turn ON and turn OFF switching device 114.
- the duty cycle control mechanism is comprised of a target duty cycle estimator/output voltage error estimator 234, a mechanism for estimating, from an output voltage error signal or an input voltage signal or a combination of both, the target duty cycle, DT, and the uncorrupted output voltage error, VE; a variable-frequency duty cycle quantizer 224 for determining the quantized duty cycle DQ closest to the target duty cycle estimate, DT; and an output- voltage-error-driven duty cycle selector 214, a mechanism for determining the turn ON and turn OFF times of switching device 114 by generating, for each value of DQ, a set of six quantized duty cycles (DQmin, DQmn, DQn, DQx, DQmx, and DQmax, ordered from lowest to highest) and by choosing, cycle by cycle, DQmin or DQmn or DQn or DQx or DQmx or DQmax (and its corresponding ON time/OFF time pair), choosing in such a manner that amplitude of the output voltage error is
- the target duty cycle estimator 234 frequently takes the form of a digital PID (proportional-integral-differential) filter, operating on an output voltage error signal.
- the filter may operate on an input voltage signal in lieu of or in addition to the output voltage error signal.
- the output voltage error estimator 234 is frequently implemented as a PID filter.
- PID filters provide the possibility of trading off delay for improved signal-to-noise ratio. Where delay must be minimized, and both static and dynamic response are important, a more precise output voltage error estimate, derived from multiple samples, may be appropriate. Such is the nature of output voltage error estimator 234.
- the estimate of the output voltage error is sampled by duty cycle selector 214 ONCE, via a ternary comparator, after the switching cycle has begun but before the turn OFF time has been determined, and sampled AGAIN, via a binary comparator, after the turn OFF time but before the final determination of duty cycle, and its implied turn ON time.
- the duty cycle selector 214 applies the first sample to limit the choice of duty cycles, and in so doing determines the turn OFF time; and applies the second sample to choose, finally, the duty cycle, and in so doing determines the turn ON time, marking the end of the switching cycle. Both choices are made immediately on sampling, in time to effect the turn OFF and the turn ON implicit in the chosen duty cycle.
- the output voltage error estimate may be derived straightforwardly by sampling a ternary comparator.
- the ideal sampling times are determined from the ON and OFF times of DQmin and DQmax.
- the first sampling time, relative to the start of the switching cycle, is 1 A (ONmin +0Nmax) rounded down (if necessary) to the nearest
- sampling times must be done as often as DQ changes.
- the tri-valued output voltage error estimate could also be constructed from two bi-valued samples separated in time but specified such that in the steady state, one sample would normally be positive and the other negative. Further, it is noted that in the event two bi-valued samples were used to obtain a tri-valued output voltage error estimate, the tri-valued estimate could be scheduled during switch ON when DT > .5 and during switch OFF when DT ⁇ .5. In this case the bi-valued estimate would be scheduled during switch ON when DT ⁇ .5 and during switch OFF when DT > .5.) For a boost converter, where the output voltage error excursions are not symmetric with respect to the mean, the derivation of an output voltage error estimate is not as straightforward.
- a tri-valued output voltage error estimate is most easily constructed from two bi-valued samples of the error voltage, separated in time but specified such that in the steady state, one sample would normally be positive and the other negative.
- the first sample could be taken %(0FFmin + OFFmax) after the turn OFF time (prior to the start of a switching cycle), and the second sample '/4(0Nmin + ONmax) after the succeeding turn ON time (marking the start of a switching cycle), enabling an output voltage error estimate to be constructed and a duty cycle chosen in time to effect the turn OFF implicit in the chosen duty cycle. If both of these samples are positive, the error estimate is positive; if both samples are negative, the error estimate is negative. If one sample is positive and the other negative, the error estimate is zero (neither positive nor negative).
- the duty cycle selector 214 chooses, cycle by cycle, DQmin, DQmn, DQn, DQx, DQmx, or DQmax (and its corresponding ON time/OFF time pair); choosing DQmin when the aggregate output voltage error estimate is highest, DQmax when the aggregate output voltage error estimate is lowest, and one of the remaining intermediate duty cycles when the aggregate output voltage error is one of the corresponding intermediate values.
- the determination of DQ for a given value of DT is accomplished by the variable- frequency duty cycle quantizer 223 via a two-step process, the first step being the enumeration of quantized duty cycles in the neighborhood of DT, and the second step being the selection of DQ from the enumerated possibilities.
- the systematic enumeration of quantized duty cycles is accomplished by generating a set of quantized ON time/OFF time pairs characterized in that the quantized ON and OFF times of each pair (in the set) are determined independently of each other; that is, the sum of the ON time and OFF time is not fixed; and may vary, pair to pair, constrained to a set of discrete values
- DQ is chosen as the duty cycle closest to but less than DT, and its associated ON time/OFF time pair is derived trivially.
- DQmin thru DQmax is accomplished by the duty cycle selector 213. While a number of options are available, a simple, and cost effective option is to set: and:
- the tri-valued output voltage error estimate determines the ON time, adjusting ONq by -1, O, or +1 clocks.
- the second, bi-valued estimate determines the OFF time, adjusting OFFq by +2, +1, O, -1, or -2 clocks, depending on the values of both estimates.
- duty cycle control mechanism described above is appealing. Moreover, the application of twice-in-the-same-cycle output voltage feedback further improves static and dynamic performance. While the duty cycle control mechanism described above has implicit performance limitations similar in nature to those of prior art duty cycle control mechanisms, the effects of duty cycle quantization on performance are substantially reduced, without introducing application dependencies.
- duty cycle control mechanisms are capable of providing effective output voltage regulation while the power converter is operating in continuous conduction mode
- provision for efficient operation at light load often requires the addition of a low-power or power-saving control mechanism for regulating output voltage when the power converter transitions to discontinuous conduction mode.
- Mechanisms for regulating in discontinuous conduction mode generally implement the pulse frequency modulation (PFM) paradigm, wherein the controllable switch is turned ON, for a fixed period, whenever the output voltage error estimate drops below a prescribed threshold value.
- PFM pulse frequency modulation
- the abrupt resumption of load presents the more serious challenge to designers of power supply regulators.
- the slam is typically detected when the (slam-induced) droop in the output voltage triggers a threshold detection mechanism, perhaps the very mechanism used to turn ON the switch in PFM mode.
- the transition from PFM to PWM may then be accomplished straightforwardly, by holding the switch ON until the energy stored in the converter is sufficient to supply the new load at the desired output voltage (via the PWM duty cycle control mechanism).
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Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/008,481 US6992469B1 (en) | 2004-12-08 | 2004-12-08 | Digital voltage regulator for DC/DC converters |
US11/180,399 US7098641B2 (en) | 2004-12-08 | 2005-07-12 | Adaptive digital voltage regulator |
PCT/US2005/043333 WO2006062790A2 (en) | 2004-12-08 | 2005-11-30 | Adaptive digital voltage regulator |
Publications (2)
Publication Number | Publication Date |
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EP1825340A2 true EP1825340A2 (de) | 2007-08-29 |
EP1825340A4 EP1825340A4 (de) | 2008-10-08 |
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Application Number | Title | Priority Date | Filing Date |
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EP05852550A Withdrawn EP1825340A4 (de) | 2004-12-08 | 2005-11-30 | Adaptiver digitaler spannungsregler |
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EP (1) | EP1825340A4 (de) |
KR (1) | KR20070094766A (de) |
WO (1) | WO2006062790A2 (de) |
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CN101196755B (zh) * | 2006-12-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | 一种高精度电压调节器 |
US9224340B2 (en) * | 2012-05-23 | 2015-12-29 | Dialog Semiconductor Inc. | Predictive power control in a flat panel display |
WO2016202223A1 (en) | 2015-06-16 | 2016-12-22 | The Hong Kong University Of Science And Technology | Three-dimensional power stage and adaptive pipeline control |
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US5475296A (en) * | 1994-04-15 | 1995-12-12 | Adept Power Systems, Inc. | Digitally controlled switchmode power supply |
WO1998044622A2 (en) * | 1997-03-27 | 1998-10-08 | Koninklijke Philips Electronics N.V. | Digitally controlled switched-mode voltage converter |
US5932938A (en) * | 1997-10-02 | 1999-08-03 | Fujitsu Limited | Switching power supply unit |
US6163143A (en) * | 1998-03-31 | 2000-12-19 | Fujitsu Limited | Power supply apparatus and method of controlling power supply circuit |
US20030117118A1 (en) * | 2001-12-26 | 2003-06-26 | Tdk Corporation | Switching power supply and control circuit used therefor |
EP1324476A1 (de) * | 2001-12-27 | 2003-07-02 | Dialog Semiconductor GmbH | Stromwandler mit Induktor und mit digital gesteuertem Taktgeber |
US20040146101A1 (en) * | 2003-01-24 | 2004-07-29 | Intersil Americas Inc. | High resolution digital pulse width modulator for DC-DC voltage converter |
US20040156219A1 (en) * | 2003-02-10 | 2004-08-12 | Power-One Limited | Digital control system and method for switched mode power supply |
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US5594324A (en) * | 1995-03-31 | 1997-01-14 | Space Systems/Loral, Inc. | Stabilized power converter having quantized duty cycle |
USRE38780E1 (en) * | 1999-09-01 | 2005-08-23 | Intersil Americas Inc. | Current mode DC/DC converter with controlled output impedance |
EP1261121A3 (de) * | 2001-05-22 | 2004-02-04 | Powerdsine Limited | Energieverteilung mit digitaler Stromsteuerung |
US6992469B1 (en) * | 2004-12-08 | 2006-01-31 | Kiawe Forest, Llc | Digital voltage regulator for DC/DC converters |
-
2005
- 2005-11-30 KR KR1020077015571A patent/KR20070094766A/ko not_active Application Discontinuation
- 2005-11-30 WO PCT/US2005/043333 patent/WO2006062790A2/en active Application Filing
- 2005-11-30 EP EP05852550A patent/EP1825340A4/de not_active Withdrawn
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US5475296A (en) * | 1994-04-15 | 1995-12-12 | Adept Power Systems, Inc. | Digitally controlled switchmode power supply |
WO1998044622A2 (en) * | 1997-03-27 | 1998-10-08 | Koninklijke Philips Electronics N.V. | Digitally controlled switched-mode voltage converter |
US5932938A (en) * | 1997-10-02 | 1999-08-03 | Fujitsu Limited | Switching power supply unit |
US6163143A (en) * | 1998-03-31 | 2000-12-19 | Fujitsu Limited | Power supply apparatus and method of controlling power supply circuit |
US20030117118A1 (en) * | 2001-12-26 | 2003-06-26 | Tdk Corporation | Switching power supply and control circuit used therefor |
EP1324476A1 (de) * | 2001-12-27 | 2003-07-02 | Dialog Semiconductor GmbH | Stromwandler mit Induktor und mit digital gesteuertem Taktgeber |
US20040146101A1 (en) * | 2003-01-24 | 2004-07-29 | Intersil Americas Inc. | High resolution digital pulse width modulator for DC-DC voltage converter |
US20040156219A1 (en) * | 2003-02-10 | 2004-08-12 | Power-One Limited | Digital control system and method for switched mode power supply |
Non-Patent Citations (1)
Title |
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See also references of WO2006062790A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO2006062790A2 (en) | 2006-06-15 |
WO2006062790A3 (en) | 2006-10-05 |
KR20070094766A (ko) | 2007-09-21 |
EP1825340A4 (de) | 2008-10-08 |
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