EP1807764A2 - Vorrichtung und verfahren zur modusumschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten - Google Patents

Vorrichtung und verfahren zur modusumschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten

Info

Publication number
EP1807764A2
EP1807764A2 EP05803464A EP05803464A EP1807764A2 EP 1807764 A2 EP1807764 A2 EP 1807764A2 EP 05803464 A EP05803464 A EP 05803464A EP 05803464 A EP05803464 A EP 05803464A EP 1807764 A2 EP1807764 A2 EP 1807764A2
Authority
EP
European Patent Office
Prior art keywords
mode
comparison
execution units
switching
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP05803464A
Other languages
German (de)
English (en)
French (fr)
Inventor
Reinhard Weiberle
Bernd Mueller
Ralf Angerbauer
Yorck Collani
Rainer Gmehlich
Eberhard Boehl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE200410051964 external-priority patent/DE102004051964A1/de
Priority claimed from DE200410051937 external-priority patent/DE102004051937A1/de
Priority claimed from DE200410051950 external-priority patent/DE102004051950A1/de
Priority claimed from DE200410051952 external-priority patent/DE102004051952A1/de
Priority claimed from DE200410051992 external-priority patent/DE102004051992A1/de
Priority claimed from DE200510037229 external-priority patent/DE102005037229A1/de
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1807764A2 publication Critical patent/EP1807764A2/de
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1641Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1654Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1695Error detection or correction of the data by redundancy in hardware which are operating with time diversity
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845Systems in which the redundancy can be transformed in increased performance

Definitions

  • Transient errors caused by alpha particles or cosmic rays, are increasingly becoming a problem for semiconductor integrated circuits.
  • the likelihood that a voltage spike caused by an alpha particle or cosmic rays will distort a logical value in an integrated circuit increases.
  • a wrong calculation result can be the result.
  • safety-relevant systems in particular in motor vehicles, such errors must therefore be reliably detected.
  • Essential components of a microcontroller are on the one hand memory modules (for example RAM, ROM, cache), the Cors and the input / output interfaces, the so-called
  • Peripherals eg A / D converter, CAN interface. Since memory elements can be effectively monitored with check codes (parity or ECC), and peripherals are often monitored application specific as part of a sensor or actuator signal path, another redundancy approach is doubling the cores of a microcontroller alone.
  • Such microcontrollers with two integrated cores are also known as dual-core architectures. Both cores execute the same program segment redundantly and in isochronous mode (lockstep mode), the results of the two cores are compared, and an error is then detected in the comparison for consistency. This configuration of a dual-core system may be referred to as a compare mode.
  • Dual-core architectures are also used in other applications to increase performance, ie to increase performance. Both cores execute different programs, program segments, and instructions, which can improve performance, so this configuration of a dual-core system can be referred to as a performance mode. This system is also referred to as a symmetric multiprocessor system (SMP).
  • SMP symmetric multiprocessor system
  • SMP Multiprocessor System
  • a method for switching in a computer system having at least two execution units, wherein at least two operating modes are switched and a first operating mode corresponds to a comparison mode and a second operating mode corresponds to a performance mode, characterized in that the execution units can be connected to an internal bus of the computer system, wherein at least two execution units are connected in the performance mode with the internal bus and at the changeover from the performance mode and the comparison mode at least an execution unit is separated from the internal bus by a switch controlled by the switch.
  • a comparator is furthermore provided, wherein in the comparison mode the comparator is activated.
  • a method is used in which a comparator is furthermore provided, the comparator being deactivated in the performance mode.
  • a method is used in which a comparator is provided which compares this data and outputs an error signal in the event of inequality, wherein the error signal is masked in the performance mode.
  • a method is used in which the at least two execution units whose data are compared in comparison mode are treated in this mode as a logical execution unit on the internal bus.
  • a method is used in which, in the comparison mode, at least one execution unit is separated from the internal bus and input data of the at least one non-separated execution unit is duplicated and these are supplied to the at least one separated execution unit.
  • a method is used in which, in the comparison mode, all but one execution unit are separated from the internal bus and input data of the non-separated execution unit are duplicated and supplied to all separate execution units.
  • a device for switching over in a computer system having at least two execution units wherein a changeover switch is provided which switches between at least two operating modes, a first operating mode being one
  • Comparison mode and a second mode of operation corresponds to a performance mode, characterized in that the execution units with an internal bus of the computer system is connectable, wherein the execution units are connected in the performance mode with the internal bus and in comparison mode only one execution unit with the - A -
  • internal bus is connected and the at least second execution unit are separated by a switch controlled by the switch from the internal bus.
  • a device in which a comparator is furthermore provided which is deactivated in the performance mode.
  • a device in which a comparator is also provided which is activated in the comparison mode.
  • a device in which the changeover switch and the comparator are combined in one component as a switching and comparison unit.
  • FIG. 1 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a comparison unit G20, a switching unit G50 and a unit for
  • FIG. 2 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined comparison and switching unit G70 comprising a comparison unit G20 and a switching unit G50 and a unit for switching request recognition G40.
  • FIG. 3 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined switchover request recognition, comparison and switchover unit G80 consisting of a comparison unit G20 and a switchover unit G50 and a unit for
  • FIG. 4 shows a multiprocessor system G200 with two execution units G210a, G210b of a switching and comparison unit G260.
  • FIG. 5 shows in a flow chart a method which, within a specific pipeline stage G230a, G230b, exchanges a special undefined bit combination with a NOP or other neutral bit combination.
  • FIG. 6 shows a multiprocessor system H200 with two execution units H210a, H210b and a switching and comparison unit H260.
  • FIG. 7 shows in a flow chart a method which shows how, with the aid of the unit ID, the program flow can be changed from one comparison mode to another
  • Performance mode can be separated in a multiprocessor system with 2 execution units.
  • FIG. 8 shows a possible method, such as the program flow when changing from a comparison mode to a performance mode in one using the unit ID
  • Multiprocessor system can be separated with 3 execution units.
  • FIG. 9 shows in a flow chart a method which synchronizes the execution units when switching from the performance mode to the comparison mode.
  • FIG. 10 shows a state machine which represents the switching between a performance and a comparison mode.
  • FIG. 11 shows a multiprocessor system G400 with two execution units and two interrupt controllers G420a, G420b including interrupt masking registers contained therein
  • G430a, G430b and various interrupt sources G440a to G440n are provided.
  • FIG. 12 shows a multiprocessor system with two execution units, a switching and comparison unit and an interrupt controller with three register sets.
  • FIG. 13 shows the simplest form of a comparator.
  • FIG. 14 shows a comparator with a unit to compensate for a phase offset.
  • FIG. 15 describes the basic behavior of the preferred component M700 (switching and comparison unit) in the comparison mode.
  • FIG. 16 describes the basic behavior of the preferred component M700 (switching and comparison unit) in the performance mode.
  • FIG. 17 shows an embodiment of the switching and comparison unit.
  • FIG. 18 shows a further embodiment of the switching and comparison unit.
  • a switching and comparing unit which generates a mode signal is shown.
  • FIG. 20 shows a general representation of a switching and comparison unit.
  • Figure 21 shows a general representation of a switching and comparing unit which generates a general mode and a general error signal.
  • FIG. 22 shows the question of response communication with an external unit.
  • FIG. 23 shows the communication with an intelligent actuator.
  • a processor a core, a CPU, as well as an FPU (floating point unit), a DSP (digital signal processor), a coprocessor or an ALU (arithmetic logical unit) may be referred to as the execution unit.
  • FPU floating point unit
  • DSP digital signal processor
  • ALU Arimetic logical unit
  • FIG. 1 shows a multiprocessor system G60 with two execution units GlOa, GlOb a comparison unit G20, a switching unit G50 and a unit for Umschaltablyerkennung G40 shown.
  • the invention relates to a multiprocessor system G60 shown in Figure 1, Figure 2, Figure 3 with at least two execution units GlOa, GlOb, a comparison unit G20, a switching unit G50 and a unit for Umschaltyingerkennung G40.
  • the Switching unit G50 has at least two outputs to at least two system interfaces G30a, G30b. Registers, memories or peripherals such as digital outputs, D / A converters and communication controllers can be controlled via these interfaces.
  • This multiprocessor system can be operated in at least two modes of operation, a compare mode (VM) and a performance mode (PM).
  • the comparison unit G20 is deactivated.
  • the switching unit G50 is configured in this operating mode such that each execution unit GlOa, GlOb with a system interface G30a,
  • the execution unit GlOa is connected to the system interface G30a and the execution unit GlOb is connected to the system interface G30b.
  • the comparison mode identical or similar instructions, program segments or programs are executed in both execution units GlOa, GlOb. Conveniently, these commands are executed isochronously, but it is also a processing with asynchrony or a defined clock skew conceivable.
  • the output signals of the execution units GlOa, GlOb are compared in the comparison unit G20. If there is a difference, an error is detected and suitable measures can be taken. These measures can trigger an error signal, initiate error handling, operate switches or a combination of these and other conceivable measures.
  • the switching unit G50 is configured in a variation such that only one signal is connected to the system interfaces G30a, G30b. In another configuration, the switching unit only causes the compared and thus same signals to be connected to the system interfaces G30a, G30b.
  • the switchover request detection G40 detects a switchover to another mode, regardless of the currently active mode.
  • FIG. 2 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined comparison and switching unit G70 comprising a comparison unit G20 and a switching unit G50 and a unit for switching request recognition G40.
  • the switching unit G50 and the comparison unit G20 can be combined to form a common switching and comparison unit (UVE) G70, as shown in FIG.
  • UVE switching and comparison unit
  • the unit for switching request recognition G40, the comparator G20 and the switching unit G50 can be combined in a common component G80.
  • Comparator G20 be summarized in a common component. Also conceivable is a summary Umschaltorerkennung G40 with the switch G50 in a common component.
  • Switchover request recognition G40 and a combined switchover and comparison unit G70 are combined switchover and comparison unit G70.
  • Execution units go n signals N 140, ..., N14n to the switching and comparison component N100. This can generate up to n output signals N160, ..., N16n from these input signals.
  • the "pure performance mode” all signals N14i are directed to the corresponding output signals N16i.
  • the "pure comparison mode” all signals N140, ..., N14n are only applied to exactly one of the output signals N16i directed.
  • the switching logic NI 10 first determines how many output signals there are. It also determines which of the input signals contribute to which of the output signals. An input signal can contribute to exactly one output signal. Formulated in a different mathematical form is thus by the Switching logic defines a function that assigns to each element of the set ⁇ N140, ..., N14n ⁇ an element of the set ⁇ N160, ..., N16n ⁇ .
  • the processing logic N120 determines to each of the outputs N16i how the inputs contribute to that output signal. Again, this component does not have to be your own
  • a first possibility is to compare all signals and to detect an error in the presence of at least two different values, which can be optionally signaled.
  • a second possibility is to make a k out of m selection (k> m / 2).
  • an error signal can be generated if one of the signals is detected as deviating.
  • a possibly different error signal can be generated if all three
  • a third option is to apply these values to an algorithm. This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA). Such an FTA is based on extreme values of the
  • Delete input values and make a kind of averaging over the remaining values This averaging can be done over the entire set of remaining values or preferably over a subset that is easy to form in HW. In this case, it is not always necessary to actually compare the values. For averaging, for example, you just have to add and divide FTM, FTA or
  • Processing logic i.e., the determination of the comparison operation per output signal, i.e. per function value
  • This information is of course multivalued in the general case, i. not just a logical bit. Not all the theoretically conceivable modes are useful in a given implementation, it is preferable to restrict the number of modes allowed. It should be emphasized that in the case of only two execution units, where there is only one compare mode, all the information can be condensed to only one logical bit.
  • Switching from a performance mode to a comparison mode is characterized in the general case by the fact that execution units that are displayed in the performance mode on different outputs are mapped in the compare mode to the same output.
  • this is realized in that there is a subsystem of execution units in which in the performance mode all input signals N14i to be considered in the subsystem are switched directly to corresponding output signals N16i, while in the comparison mode they are all mapped to one output.
  • switching can also be realized by changing pairings. It is thus explained that in the general case one can not speak of the one performance mode and the one comparison mode, although in a given form of the invention one can limit the set of allowed modes such that this is the case. However, one can always speak of switching from a performance mode to a comparison mode (and vice versa).
  • the switching is triggered either by the execution of special switching instructions, special instruction sequences, explicitly marked instructions or by the access to specific addresses by at least one of the execution units of the multiprocessor system.
  • Fault logic N 130 collects the error signals generated by the comparators, for example, and optionally can passively turn outputs N16i off, for example, via a switch.
  • the following examples tend to focus on the case of two execution units, where most concepts are easier to visualize
  • the switching between the modes can be coded by various methods.
  • special switching commands are to be used, which are detected by the switching request recognition unit G40.
  • Another possible method for coding the switching is defined by the access to a special memory area which again detects the unit for switching request recognition G40.
  • FIG. 4 shows a multiprocessor system G200 with two execution units G210a, G210b and a switching and comparison unit G260.
  • undefined bit combinations of the at least two execution units G210a, G210b are used in the assembler. As undefined or undefined bit combinations in this sense are all
  • bit combinations that are specified in the description of the instruction set as undefined or illegal. These are e.g. Illegal Operand, Illegal Instruction, Illegal Operation.
  • the general characteristic of these undefined bit combinations is that a normal execution unit when executing such a bit combination either generates an error signal or exhibits an undefined behavior. So these bit combinations are not needed to represent the semantics of an ordinary program.
  • the previous development environment can be used, as it exists for single-processor systems.
  • This can be realized, for example, by defining a macro "SWITCH MODE TO PM" and a macro "SWITCH MODE TO VM” which inserts appropriate undefined bit combinations at the appropriate place in the code in the sense defined above.
  • SWITCH MODE TO VM which inserts appropriate undefined bit combinations at the appropriate place in the code in the sense defined above.
  • the use of this combination is then defined as a general "SWITCH” macro, which then effects a switch to the other depending on the current mode If more than two different modes exist in the system, more such combinations must be available for use of this method then one per switchover mode can be used.
  • the switchover request is coded by a bit combination not defined in the instruction set. These may not be processed in the usual way within an execution unit G210a, G210b.
  • an additional pipeline stage (REPLACE stage) G230a, G230b is proposed, which recognizes the corresponding bit combinations and replaces them for further processing by neutral bit combinations.
  • this is done using the "NOP" (No Operation) command, which is characterized by the fact that it does not change the internal state of the execution unit, except for the intruction pointer, the REPLACE stage G230a, G230b being after the usually first stage , the FETCH stage G220a G220b and before the rest
  • Pipeline levels G240a, G240b, are inserted in the assembler undefined bit combinations, which are summarized here in one unit.
  • Pipeline G215a, G215b generate additional signals G250a, G250b, when a corresponding bit combination has been detected for switching, which signals a separate switching unit and comparison unit G260 that a change of the processing mode is to be performed.
  • the REP stages G230a, G230b are preferably arranged between the FET G220a, G220b and the remaining pipeline stages G240a, G240b in the pipeline units G215a, G215b of the execution units G210a, G210b.
  • the REP stages G230a, G230b recognize the corresponding bit combinations and, in this case, forward NOP instructions to the remaining stages G240a, G240b.
  • FIG. 5 shows in a flow chart a method which, within a specific pipeline stage G230a, G230b, exchanges a special undefined bit combination with a NOP or other neutral bit combination.
  • FETCH stage G300 a command ie a bit combination is fetched from memory. Thereafter, in block G310, a distinction is made as to whether the fetched bit combination corresponds to the specific undefined bit combination which encodes a switchover. If this is not the case, in the next step G320 the bit combination is transferred without change to the remaining pipeline stages G340 for further processing.
  • step G330 If the particular bit combination encoding a switch was detected in step G310, in step G330 it is replaced with the NOP bit combination and then passed to the further pipeline stages G340 for further processing.
  • the blocks G310, G320, G330 represent the functionality of a REPLACE stage G230a, G230b according to the invention, which may also contain further functionality.
  • FIG. 6 shows a multiprocessor system H200 with two execution units H210a, H210b and a switching and comparison unit H260.
  • the components H220a, H220b, H240a, H240b have the same meaning as G220a, G220b, G240a, G240b.
  • the unit for switching request recognition G40 described here by the special pipeline stages H230a, H230b, this has, in addition to the signals H250a, H250b, which signal a changeover, further signals. So that the execution units
  • H210a, H210b can be synchronized when switching from the performance mode to the comparison mode, the pipeline units H215a, H215b of the execution units H210a, H210b each have a signal input H280a, H280b, with which the processing can be stopped.
  • This signal is set by the switching and comparison unit H260 for the pipeline unit H215a or H215b which first detected a switchover command and thus activated the signal H250a or GH50b. Only when both pipeline units H215a, H215b of the execution units H210a, H210b have recognized the switchover command and have synchronized their internal states by means of software or other hardware measures, this signal H280a, H280b is canceled again.
  • the H280a, H280b are not needed because no synchronization is necessary.
  • each execution unit has its individual number or Can determine unit ID.
  • an ID unit a unit or method, via which each execution unit has its individual number or Can determine unit ID.
  • one execution unit can determine the number 0 for itself and the other the number 1.
  • the numbers are assigned or determined accordingly.
  • This ID does not distinguish between a comparison mode and a performance mode, but uniquely identifies an execution unit.
  • the ID unit may be included in the respective execution units, for example implemented as a bit or bit combination in the processor status register or as a separate register or as a single bit or as an external unit to the execution units which provides a corresponding TD upon request.
  • the comparison unit is no longer active, but the execution units still execute the same instructions. This is because the instruction pointers that mark the location in the program where an execution work is currently working or is currently working in the next step are not affected by the switchover. So that the execution units can subsequently execute different software modules, the program sequence of the execution units must be separated. Therefore, the instruction pointers in performance mode usually have different values, since according to the invention independent instructions, program segments or programs are processed.
  • the separation of the program flows is done in the proposal described here by determining the respective execution unit number. Depending on which ID has an execution unit, the execution unit executes a specific software module. Since each execution unit has an individual number or ID, the program flow of the participating execution units can thereby be reliably separated.
  • FIG. 7 shows in a flow chart a method which shows how, with the aid of the unit ID, the program flow can be separated when changing from a comparison mode to a performance mode in a multiprocessor system with 2 execution units.
  • Performance mode G500 the units ID or execution unit number G510 is queried by both execution units.
  • the execution unit 0 receives the execution unit number 0, the execution unit 1 the execution unit number 1.
  • G510 a comparison of the determined Execution number with the number 0. If these are the same, in step G520 the execution unit for which this comparison was successful continues with the code for execution unit 0.
  • the execution unit for which this comparison was unsuccessful continues in G530 with the comparison with the number 1. If this comparison is successful, the execution unit 1 code continues in G540. If this comparison is unsuccessful, an execution unit number not equal to 0 and 1 was determined for the corresponding execution unit. This represents an error and continues with G550.
  • FIG. 8 describes a possible method for 3 execution units.
  • the units ID or execution unit number H510 is queried by the execution units.
  • the execution unit 0 receives the execution unit number 0, the execution unit 1 the execution unit number 1 and execution unit 2 the execution unit number.
  • step H520 the execution unit for which this comparison was successful continues with the code for execution unit 0.
  • the execution units for which this comparison was unsuccessful continue to compare with # 1 in H530.
  • the code for execution unit 1 in H540 is continued.
  • the execution units for which this comparison was unsuccessful continue to compare with number 2 in H535.
  • the execution unit for which this comparison succeeds continues with the execution unit 2 code in H536. If this comparison was unsuccessful, the corresponding execution unit became one
  • Execution unit number not equal to 0,1 and 2 determined. This is an error and H550 will continue.
  • the determined execution unit number can also be used directly as an index in a jump table.
  • this method can also be used for multiprocessor systems with more than 3 execution units.
  • switching from performance mode to compare mode several things need to be considered.
  • This can be done by hardware, software, firmware, or a combination of all three.
  • the prerequisite for this is that all execution units execute identical or similar instructions, programs or program segments after switching to the compare mode.
  • a synchronization method is described which is applicable when the comparison mode is characterized in that identical instructions are processed and a bit-accurate comparison takes place.
  • FIG. 9 shows in a flow chart a method which synchronizes the execution units when switching from a performance mode to a comparison mode.
  • step G600 preferably all interrupts are disabled. This is not only important because the
  • Interrupt controller for the comparison mode must be reprogrammed accordingly.
  • Software should also be used to adjust the internal status of the execution units. However, if an interrupt is triggered during the preparation for switching to the comparison mode, then an adjustment is no longer possible without further effort.
  • Step G610 If the two execution units have separate caches, the contents of the caches must also be adjusted before the switchover in order to prevent a cache hit in the comparison mode for an address for the one execution unit and a cache miss for another execution unit occurs. If this is not done independently by the cache hardware, this can be done by marking all cachelines as invalid, for example. It must wait until the cache (or caches) are completely invalid. If necessary, this should be ensured by a waiting loop in the program code. This can also be achieved by other means, it is crucial that after this step, the caches are in the same state.
  • step G620 the write buffers of the execution units are emptied so that after the switch no activities of the execution units still originating from the performance mode take place.
  • step G630 the state of the pipeline stages of the execution units is synchronized. For this purpose, for example, one executes an appropriate number of NOP (No Operation) instructions before the switching sequence / switching command.
  • NOP No Operation
  • Execution units have an instruction cache, ensuring that this instruction sequence is aligned with the boundaries of a cacheline (alignment). Since the instruction cache has been marked as invalid prior to the execution of these NOPs, these NOPs must first be cached. If this instruction sequence begins at a 0 cacheline boundary, data transfer from memory (e.g., RAM / ROM / Flash) to the cache is complete before the switch instruction occurs. Again, this must be taken into account when determining the necessary number of NOPs.
  • memory e.g., RAM / ROM / Flash
  • step G640 the command step for switching to the comparison mode is actually performed.
  • step G650 the contents of the respective register files of each execution unit are equalized.
  • the registers are to be loaded with identical contents before or after the changeover. It is important that after switching the contents of a register in the O execution units is identical, before the register contents are transferred to external and thus compared by the comparison unit.
  • step G660 the interrupt controllers are reprogrammed so that an external interrupt signal triggers the same interrupt 5 on all interconnected execution units.
  • step G670 the interrupts are released again.
  • FIG. 10 shows a state machine which represents the switching between a performance and a comparison mode (and vice versa).
  • Undefined event that is able to trigger a reset always starts to work in state G700.
  • Examples of events that can trigger a reset are external signals, problems with the power supply, or internal error events that make it unnecessary to continue working.
  • the state G700 of the switching and comparison unit G70 and also of the multiprocessor system G60, in which work is carried out in the performance mode, is thus the default state of the system. In all cases in which an otherwise undefined state would be assumed, the default state G700 is assumed. This default position of state G700 is ensured by hardware measures. For example, the system state or the state of the switching and comparison unit G60 in a register, in a bit of a register, by a bit combination in a
  • the state G700 is always assumed after a reset or power on. This is ensured by, e.g. the reset signal or the "Power On” signal is routed to the reset input or the set input of the flip-flop or the register.
  • state G700 the system operates in a performance mode.
  • the execution units GlOa, GlOb work with different commands, programs or program pieces.
  • a switchover request can be recognized, for example, by an execution unit GlOa, GlOb executing a special switchover command.
  • Possibilities are a recognition by the access to a special memory address, by an internal signal or also by an external signal. As long as there is no switchover request, the multiprocessor system G60 and therefore also the switchover and comparison unit G70 remain in state G700. In addition, the changeover request designates the recognition of a switchover condition, which is identified as a changeover request is identified in this special system.
  • the remaining in the state G700 is represented by the transition G810. If a changeover request is recognized by the execution unit GlOa, then the changeover and comparison unit G70 is transferred to the state G710 via the transition G820.
  • Condition G710 thus designates the situation that the execution unit GlOa has recognized a switchover request and waits until the execution unit GlOb also recognizes a switchover request. As long as this is not the case, the switching and comparison unit G70 remains in state G710, which is represented by the transition G830.
  • the transition G840 takes place when in the state G710 the execution unit GlOb also recognizes a switchover request.
  • the switching and comparison unit G70 thus assumes the state G730.
  • state G730 the synchronization processes take place with which the two execution units GlOa, GlOb are synchronized with one another in order to then operate in the comparison mode.
  • the switching and comparison unit G70 remains in state G730, which is represented by the transition G890.
  • the transition is made to the state G720 via the transition G860.
  • the state G720 thus designates the situation that the execution unit GlOb has recognized a switchover request and waits until the execution unit GlOa also recognizes a switchover request.
  • the switching and comparison unit G70 remains in state G720, which is represented by the transition G870.
  • the transition G880 takes place when in the state G720 the execution unit GlO a also recognizes a switchover request.
  • the switching and comparison unit thus assumes the state G730.
  • state G730 is immediately entered. This case represents the transition G850.
  • both execution units GlOa, GlOb have recognized a switching request.
  • the internal states of the execution units GlOa, GlOb are synchronized to operate in comparison mode after completion of these synchronization operations.
  • transition G900 takes place. This transition indicates the end of synchronization.
  • execution units GlOa, GlOb operate in compare mode. The completion of the synchronization work can be done by the
  • Transition G900 occurs when both execution units GlOa, GlOb have signaled that they are ready to operate in compare mode.
  • the termination can also be signaled for a set time.
  • the switching and comparison unit G70 can monitor the states of the execution units GlOa, GlOb and recognize themselves when both execution units GlOa, GlOb have finished their synchronization work. After detection, transition G900 is then initiated.
  • the multiprocessor system G60 remains in compare mode, represented by transition G910. If in state G740 on
  • the changeover and comparison unit is set to state G700 via transition G920. As already described, the system operates in state G700 in the performance mode. The separation of the program flows during the transition from state G740 to state G700 can then be carried out as described in the method.
  • FIG. 11 shows a multiprocessor system G400 with two execution units G410a, G410b and two interrupt controllers G420a, G420b including interrupt masking registers G430a, G430b contained therein and various interrupt sources G440a to G440n. Also shown is a switch and compare unit G450 having a special interrupt mask register G460.
  • each execution unit G410a, G410b has its own interrupt controller G420a, G420b in order to simultaneously handle two interrupts in the performance mode.
  • the interrupt sources G440a to G440n are advantageously connected in the same way to both interrupt controllers G420a, G420b in each case. This type of connection causes the same interrupt to be triggered on both execution units G410a, G410b without further measures.
  • the interrupt controllers G420a, G420b are programmed so that the corresponding interrupt sources G440a to G440n are appropriately divided among the various execution units G410a, G410b according to the application.
  • interrupt masking registers G430a, G430b This is done by means of a suitable programming of the interrupt masking registers G430a, G430b.
  • the mask registers provide one bit in the register for each interrupt source G440a through G440n. If this bit is set, the interrupt is disabled, so it is not sent to the connected execution unit G410a, G410b forwarded.
  • a given interrupt source G440a to G440n is processed by exactly one execution unit G410a or G410b.
  • this is true for at least some of the interrupt sources.
  • interrupt sources G440a to G440n can be processed simultaneously without an interrupt nesting (an interrupt processing is interrupted by a second interrupt) or interrupt pending (the processing of the second is postponed until the processing of the first is ended is) takes place.
  • Interrupt Mask Registers G430a, G430b are programmed with the same value, respectively. It is proposed to use a special register G460 to speed up the switching process. In one embodiment, this register G460 is arranged in the switchover and comparison unit G460, but it can also be used in the switchover request recognition G40, in a combined switchover request recognition, in the
  • Comparator in the switching unit G80, as well as in all combinations. It is also conceivable that this register is arranged outside of these three components at another suitable location.
  • the register G460 contains the interrupt mask, which is to apply in comparison mode.
  • the changeover and comparison unit G450 receives a signal from the switchover request detection G40 to switch from one performance to another
  • step G600 the interrupt mask registers G430a, G430b of the interrupt controllers G420a, G420b are reprogrammed. This is now performed by hardware from the switching and comparison unit G450 in parallel with the other synchronization steps after the switching signal has been received and the interrupt controllers G420a, G420b have been disabled.
  • the interrupt masking registers G430a, G430b in the compare mode are not individually reprogrammed, but always the central register G460. This is then transmitted synchronously by hardware to the two interrupt masking registers G430a, G430b.
  • the method described here for an interrupt mask register can be described in the same Sent to all interrupt status registers, which are arranged in an interrupt controller.
  • a register G460 another storage medium from which it is possible to transfer to the interrupt masking registers G430a, G430b as quickly as possible.
  • FIG. 12 shows a multiprocessor system GlOOO with two execution units GlOlOa, GlOlOb, a switchover and comparison unit G 1020, and an interrupt controller G1030 with three different register sets G1040a, G1040b, G1050.
  • a special interrupt controller G1030 is proposed, as shown in FIG. This one is in one
  • Multiprocessor system GlOOO used, which in the example with two execution units GlOlOa, GlOlOb, and a switching and comparison unit G 1020, which can switch between a comparison and a performance mode, is shown.
  • the register sets G 1040a, G 1040b are used.
  • the interrupt controller G1030 operates as well as two interrupt controllers G420a, G420b.
  • the register set G 1040a is assigned to the execution unit GlOlOa and the register set G 1040b to the execution unit GlOlOb.
  • the interrupt sources G 1060a to G 106On are appropriately distributed by masking to the execution units GlOlOa, GlOlOb.
  • Comparator G1020 a signal G1070. This signals to the interrupt controller G1030 that the system is switched to comparison mode or that the system is operating in comparison mode from this point in time. The interrupt controller G 1030 then uses the register set G1050. This ensures that the same interrupt signals are generated at both execution units GlOlOa, GlOlOb. With a change from the comparison mode to the
  • Performance mode which the switching and comparison unit G 1020 signals again via the signal G1070 the interrupt controller G1030, is switched to the register sets G1040a, G1040b again.
  • protection of the corresponding register sets can thus also be achieved by only permitting writing to the register sets G1040a, G1040b in the performance mode, and writing to the register set G1050, which is reserved for the comparison mode, being inhibited by hardware.
  • FIG. 13 shows the simplest form of a comparator M500, G20.
  • the comparison component M500 can receive two input signals M510 and M511. It then compares these to equality, in the context presented here, preferably in the sense of a bit-wise equality. In the case of equality, the value of the input signals M510, M511 is given to the output signal M520 and the error signal M530 does not become active, ie it signals the "good" state. If it detects inequality, the error signal M530 is activated. The signal M520 can then optionally be deactivated.
  • fault containment ie other components that lie outside of the execution units are not corrupted by the potentially faulty signal, but there are also systems in which the signal This is the case, for example, if only fail-silence is required at the system level, for example, the error signal can then be routed externally.
  • the component M500 can be executed as a so-called TSC component (totally seif checking).
  • the error signal M530 will be on at least two lines
  • Variant in the use of the system according to the invention is to use such a TSC comparator.
  • a second class of embodiments may be distinguished as to what degree of synchronicity the two inputs M510, M511 (or M610, M611) must have.
  • One possible embodiment is characterized by intermittent synchronicity, i. the comparison of the data can be done in one cycle.
  • a slight change results from using a synchronous delay element with a fixed phase offset between the inputs, which provides the appropriate signals for example, delayed by half-integer or integer clock periods.
  • phase offset is useful to avoid common cause errors, ie those causes of error that can affect multiple processing units simultaneously and similarly.
  • FIG. 14 therefore describes another embodiment.
  • the components and signals M600, M610, M611, M620, M630 have the same meaning as the corresponding components and signals M500, M510, M511, M520, M530 of Figure 13.
  • component M640 is inserted beyond these components , which delays the earlier input by the phase offset.
  • this delay element is accommodated in the comparator to use it only in the comparison mode.
  • intermediate buffers M650, M651 can be placed in the input chain in order to be able to tolerate asynchronisms which are not pure clock or phase offsets.
  • These intermediate buffers are preferably designed as FIFO memories (first-in, first out). Such a memory has an input and an output and can store several memory words.
  • An incoming memory word is shifted in its place upon arrival of a new memory word. After the last digit (the depth of the buffer) it is shifted "out of memory.” If such a buffer is present, it can also tolerate asynchronisms up to the maximum depth of the buffer, in which case an error signal must be output even if the buffer overflows.
  • comparator embodiments it can be distinguished according to how the signal M520 (or M620) is generated.
  • a preferred embodiment is to put the input signals M510, M511 (or M610, M611) on the output and to make the connection interruptible by switches.
  • the particular advantage of this embodiment is that for
  • the same switch can be used.
  • the signals can also be generated from internal comparator buffers.
  • Comparison modes are, then these are preferably coupled to the corresponding mode of the comparator.
  • comparator (hereinafter for the sake of simplicity always referred to as a comparator).
  • a comparator There are many possibilities. On the one hand you can lead to the comparator a signal with which it is activated or deactivated. For this purpose, an additional logic is inserted in the comparator, which can do this. Another possibility is to provide the comparator with no comparative data.
  • a third possibility is to have the error signal of the system level
  • a preferred variant of the implementation is therefore to combine these two parts in one component. This is a component with at least the input signals (output execution unit 1, output execution unit 2), at least the output signals
  • Output 1, Output 2 a logic output signal “Output total” (can physically match Output 1 or Output 2) and a comparator
  • the component has the ability to switch the mode, pass all signals in the performance mode, and in a comparison mode Mode to compare several signals and pass one if necessary
  • Other input and output signals are advantageous: an error signal for signaling a detected error, a mode signal for signaling the mode in which this component is located, and control signals to and from the component.
  • the two or more execution units are in
  • Performance mode as master connected to a processor internal bus.
  • the comparison unit is deactivated or the error signal which is generated in the case of a different behavior of the execution units in one of the conceivable comparison modes is masked. This means that the switching and comparison unit is transparent to the software. In the comparison mode considered, the physical
  • Execution units are treated as a logical execution unit on the bus, i. there is only one master on the bus.
  • the error signal of the comparator is activated.
  • the switching and comparison unit separates all but one execution unit via switches from the processor-internal bus, duplicates the inputs of the one logical execution unit and makes them available to all execution units involved in the comparison mode.
  • FIG. 15 and FIG. 16 describe the basic behavior of the preferred component M700 (switching and comparison unit, corresponds to G70). For the sake of simplicity, this is
  • FIG. 15 shows the status of the component in the comparison mode, FIG. 16 in the performance mode.
  • the various switch positions in these modes are implemented by M700 through the M760 control.
  • the two execution units M730, M731 can first write in the performance mode on the data and address bus M710 when the switches M750 and M751 are closed, as shown in FIG. It is assumed that possible write conflicts will be resolved either via the bus protocol or through other, not drawn components.
  • comparison mode the behavior is different, at least from a logical point of view.
  • the switches M750, M751 are then opened and thus the direct access possibilities are interrupted.
  • the switches M752, M753 are then closed in FIG.
  • the signals M740, M741 of the execution units M730, M731 are passed to the comparison component M720.
  • This is at least as constructed as drawn in Figure 13, but it can also extensions, as shown in Figure 14, include.
  • On a representation of the error signal or other signals of the Comparative component M720 is omitted in Figure 15, and Figure 16. If the two signals match, the switch M754 is closed, and then one of the two matching signals is forwarded to the address / data bus M710. All in all, it is necessary that the M700 switching and comparison unit can influence the M750-M754 switches. The respective switch position depends on the mode and on the
  • FIG. 17 shows a variant of the switching and comparison unit. Even for a simple system with only two execution units GlOa, GlOb there are many variants of the
  • FIG. 16 Another, which is particularly advantageous when no buffers are to be used in the comparator, is shown in FIG. As in FIG. 15, FIG. 16, there are the signals M840, M841 of the execution units. The latter are not drawn in this figure.
  • M840, M841 of the execution units The latter are not drawn in this figure.
  • M810 which specifies the mode of the component. In performance mode, it closes the switch
  • FIG. 18 shows a further embodiment of the switching and comparison unit. This alternative, although it has more switches, but leaves the comparator in the performance mode inactive and therefore easier to deal with asynchronisms.
  • Buffer times or in one implementation lower buffer depths.
  • the M930 switch In performance mode, the M930 switch is always closed. In compare mode, component M910 closes switches M932, M933 and interrupts direct access to the bus by opening switch M931. Optionally, the M910 mode logic still allows the M920 comparator to operate report. In the comparison mode, the switch M930 is closed in error-free case. In the event of an error, the comparison component M920 interrupts the forwarding of the signal M940 to the bus by opening the switch M930.
  • this component is thus characterized in that there are several processing units that output signals to the bus
  • the component can process (e.g., compare, but possibly also vote or sort) at least two of the output signals of the execution units and that the component can affect at least one switch that breaks at least one of the direct bus accesses. This is especially useful if the execution units are computer cores. Furthermore, it is advantageous if the state of the influenceable switch characterizes the operating mode of the arithmetic unit.
  • the system properties in particular the possible comparison modes, are then implemented particularly well if the component can apply a signal to the address data bus.
  • this is a switching through one of the output signals of one of the execution units.
  • this may arise from the processing of various output signals of the various execution units.
  • this mode information may even be available explicitly in a subcomponent.
  • this signal may also be routed out of the component and made available to other parts of the system.
  • the optional error signal is generated by fault circuit logic N130, which collects the error signals, and is either a direct forwarding of the single error signals or a bundling of the error information contained therein.
  • the mode signal Nl 50 is optional, but its use outside of this component can be beneficial in many places.
  • Information of the switching logic NI10 i.e., the function described in the description of Figure 20
  • the processing logic i.e., the determination of the comparison operation per output signal, i.e., per function value
  • This information is of course multivalued in the general case, i. not just a logical bit. Not all theoretically conceivable modes are in a given
  • the mode signal then brings the relevant mode information to the outside.
  • An HW implementation is preferably shown so that the externally visible mode signal can be configured.
  • the processing logic and circuitry are also configured to be configurable. Preferably, these configurations are coordinated. Alternatively, one can give only or additionally changes of the mode signal to the outside. This has advantages, especially in a two-party configuration.
  • this mode signal is protected.
  • An implementation in the two-system is based, for example, on the implementation shown in FIG. 17 in FIG.
  • the signal M850 is led out of the switching and comparison unit. In a two-way system, this information can be represented logically over one bit. A hedge can then preferably be displayed via a dual-rail signal. In the general case, the signal can also be protected by a doubling, which is optionally inverted. Alternatively, one can also generate a parity, which is preferably internally generated intrinsically safe, or use a CRC (cyclic redundancy check) or ECC (error correcting code).
  • CRC cyclic redundancy check
  • ECC error correcting code
  • the mode signal can be used outside the component. Initially, it can be used to self-monitor the operating system. This is from a SW point of view for one
  • this signal can optionally also be used in other data sinks of a ⁇ C (or more general arithmetic unit).
  • a memory protection unit MPU
  • MPU memory protection unit
  • An MPU is a unit that can ensure that only permitted accesses are made to the data / address bus, for example by blocking access to certain address spaces for certain program sections.
  • Mode signal is already sufficient information to check. Then, quasi-static programming is sufficient for the initialization time of the ⁇ C. Analogously, the evaluation of this signal can also be used on the interrupt controller. Such monitoring can then form the basis or an integral part of the security concept.
  • suitable design and software structuring it may be possible to construct the security concept for an entire error class in the application under consideration on this mode signal. This is particularly advantageous when the mode signal is intrinsically safe in a suitable form as described above. It is then further advantageous in this case if the component under consideration has the possibility to send an error signal or to actuate a shutdown path if it detects a discrepancy between the mode signal and the
  • An essential further purpose is the evaluation of the mode signal outside of the arithmetic unit.
  • a direct application is the evaluation in a decrementing Watchdog.
  • Such a “watchdog” consists of at least one (counter) register, which can be set by the microprocessor to an integer value After setting this register, the “watchdog” automatically decrements the value of the register with a fixed period , If the value of the register is zero, or if an overflow occurs, the watch dog generates an error signal
  • Reset the value of the register in good time This can be used to check (within limits) whether the microprocessor is executing the software correctly. If the microprocessor no longer executes the software correctly, it is assumed that in this case the "watchdog" is no longer correctly operated and thus an error signal is generated by the "watchdog". The integrity of the hardware and data structures can be reliably verified in a compare mode, but it must be ensured that the microprocessor regularly returns to this.
  • the task of the "watchdog” described here is therefore not only to generate an error signal if it is no longer reset within a defined period of time, but also if the microprocessor no longer switches back to the defined comparison mode within a defined period of time the "watchdog" can only be reset if the signal mode indicates the defined comparison mode of the arithmetic unit. This ensures that the arithmetic unit regularly returns to this mode.
  • the value in the register of the "watchdog” is decremented only when certain interrupts are triggered at the microprocessor, for which purpose the external interrupt signals of the ⁇ C must also be coupled to the watchdog
  • the watchdog stores which interrupts the ⁇ C in The watchdog is “pulled up” as soon as such an interrupt comes, it is reset by the presence of the correct mode signal.
  • An essential point in ensuring the correct operation of the software on a computer as described in the invention is the correct change between the different allowed modes.
  • the changeability itself should be checked, preferably also the correct change. As described above, one may also be interested in having a special one
  • Mode is accepted regularly. Such a method is always particularly advantageous when the mode signal itself is intrinsically safe.
  • One possibility is to pass the mode signal to an ASIC or another ⁇ C. This can at least check the following points via timers and simple logic using this signal:
  • N300 is a computational unit that can send such a mode signal. This may be, for example, a ⁇ C with multiple execution units and another component that can generate this mode signal. For example, this may be different
  • N300 gives this signal N310 to the partner (e.g., other arithmetic unit, other ⁇ C or ASIC) N330.
  • This can ask about the N320 signal to N300 questions which N300 has to answer via N321.
  • Such a question may be a computational task whose correct result is to be delivered via N321 from N300 within a defined time interval.
  • N330 can check the correctness of this result independently of N300. For example, the results are stored in N330 or N330 can calculate them yourself. If an incorrect value is detected, an error is detected.
  • the special feature of the proposed question-answer communication is that a parallel to the response, the mode signal is observed.
  • the questions are to be asked so that to answer by N300, they must adopt certain modes.
  • An arithmetic unit N400 which has the invention, sends an actuating command via the connection N420 to an (intelligent) actuator or an actuator control N430. In parallel, it sends the mode signal to this actuator via the N410 connection.
  • Actuator N430 uses the mode signal to check whether control is permitted and optionally returns an error status via signal N440. If the drive is faulty, it assumes the non-critical fail-silence state in the system.

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070085278A (ko) * 2004-10-25 2007-08-27 로베르트 보쉬 게엠베하 적어도 2개의 실행 유닛을 구비한 컴퓨터 시스템의 전환방법 및 그 전환 장치
DE102005037230A1 (de) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Überwachung von Funktionen eines Rechnersystems
DE102006048169A1 (de) * 2006-10-10 2008-04-17 Robert Bosch Gmbh Verfahren zur Überwachung einer Funktionsfähigkeit einer Steuerung
CN101580073B (zh) * 2008-05-12 2012-01-25 卡斯柯信号有限公司 计算机联锁***码位级冗余方法
JP4709268B2 (ja) * 2008-11-28 2011-06-22 日立オートモティブシステムズ株式会社 車両制御用マルチコアシステムまたは内燃機関の制御装置
US8375250B2 (en) * 2009-03-04 2013-02-12 Infineon Technologies Ag System and method for testing a module
DE102011086530A1 (de) * 2010-11-19 2012-05-24 Continental Teves Ag & Co. Ohg Mikroprozessorsystem mit fehlertoleranter Architektur
JP5796311B2 (ja) 2011-03-15 2015-10-21 オムロン株式会社 制御装置およびシステムプログラム
DE102012201185A1 (de) 2012-01-27 2013-08-01 Siemens Aktiengesellschaft Verfahren zum Betreiben mindestens zweier Datenverarbeitungseinheiten mit hoher Verfügbarkeit, insbesondere in einem Fahrzeug, und Vorrichtung zum Betreiben einer Maschine
JP5983744B2 (ja) 2012-06-25 2016-09-06 富士通株式会社 情報処理装置および情報処理装置の故障検出方法
JP6693400B2 (ja) * 2016-12-06 2020-05-13 株式会社デンソー 車両用制御システム
US10635831B1 (en) * 2018-01-06 2020-04-28 Ralph Crittenden Moore Method to achieve better security using a memory protection unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864670A (en) * 1970-09-30 1975-02-04 Yokogawa Electric Works Ltd Dual computer system with signal exchange system
US4049957A (en) * 1971-06-23 1977-09-20 Hitachi, Ltd. Dual computer system
US4029952A (en) * 1973-11-06 1977-06-14 Westinghouse Electric Corporation Electric power plant having a multiple computer system for redundant control of turbine and steam generator operation
US5428769A (en) * 1992-03-31 1995-06-27 The Dow Chemical Company Process control interface system having triply redundant remote field units
US5544077A (en) * 1994-01-19 1996-08-06 International Business Machines Corporation High availability data processing system and method using finite state machines
US5537583A (en) * 1994-10-11 1996-07-16 The Boeing Company Method and apparatus for a fault tolerant clock with dynamic reconfiguration
EP1036483B1 (en) * 1997-12-11 2006-08-30 Telefonaktiebolaget LM Ericsson (publ) Redundancy termination for dynamic fault isolation
DE19815263C2 (de) * 1998-04-04 2002-03-28 Astrium Gmbh Vorrichtung zur fehlertoleranten Ausführung von Programmen
US6550017B1 (en) * 1999-06-29 2003-04-15 Sun Microsystems, Inc. System and method of monitoring a distributed fault tolerant computer system
US6550018B1 (en) * 2000-02-18 2003-04-15 The University Of Akron Hybrid multiple redundant computer system
US6772368B2 (en) * 2000-12-11 2004-08-03 International Business Machines Corporation Multiprocessor with pair-wise high reliability mode, and method therefore

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode

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