EP1581965A2 - Semiconductor chip stack and method for passivating a semiconductor chip stack - Google Patents

Semiconductor chip stack and method for passivating a semiconductor chip stack

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Publication number
EP1581965A2
EP1581965A2 EP03788833A EP03788833A EP1581965A2 EP 1581965 A2 EP1581965 A2 EP 1581965A2 EP 03788833 A EP03788833 A EP 03788833A EP 03788833 A EP03788833 A EP 03788833A EP 1581965 A2 EP1581965 A2 EP 1581965A2
Authority
EP
European Patent Office
Prior art keywords
semiconductor chip
spacer
semiconductor
chip stack
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP03788833A
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German (de)
French (fr)
Inventor
Holger HÜBNER
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Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1581965A2 publication Critical patent/EP1581965A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Definitions

  • Semiconductor chip stacks can be produced in that two semiconductor chips, each having an upper side provided with at least one electronic component and a wiring level, are permanently connected to one another with these upper sides, with connection contacts of the respective semiconductor chips being electrically electrically connected via rewiring or a vertical electrically conductive connection be connected to each other.
  • This arrangement face to face
  • the further assembly process should not be hindered by such a passivation; in particular, existing on a bottom chip connection contact surfaces for external connection, for. B. are not contaminated by means of bond wires.
  • the chips are usually passivated with oxynitride and polyimide.
  • this requires a subsequent photolithographic opening of the connection contact surfaces (bond pads).
  • Lithography on the assembled wafers is difficult because the wafers that contain the bottom chips, which have not yet been separated, can hardly be coated with layers of lacquer and exposed using the top chips.
  • Passivation is particularly difficult when conductor tracks on the top of the bottom chip lead from the free top to the top chips placed on top.
  • the connection contact surfaces are also placed very close to the top chips (a few hundred micrometers), so that sealing the space with conventional potting compounds is ruled out.
  • the object of the present invention is to provide a possibility for passivating the intermediate space between face-to-face mounted semiconductor chips.
  • an intermediate space present between the semiconductor chips is filled at least along an edge of the upper side of the smaller upper semiconductor chip (top chip) by a spacer made of a photostructurable polymer, a photoresist, a sealing compound or an adhesive and is thus sealed off from the outside.
  • the connection contact surfaces for bond wires or other external connections on the top of the other semiconductor chip (bottom chip) are kept free of the material of this spacer.
  • a larger spacer attached to the flanks of the upper semiconductor chip can also be provided for better sealing of the intermediate space.
  • a photoresist is preferably used as the material, which penetrates into the intermediate space after assembly of the chip stack and preferably completely fills the intermediate space.
  • the photoresist can then be exposed, the portion present in the intermediate space being shadowed by the upper semiconductor chip.
  • the exposed portion is treated and removed with a developer liquid in the manner known per se from lithography technology.
  • any photostructurable polymer is suitable for this, in particular polyimide or BCB.
  • a casting compound in particular an epoxy resin, or an adhesive based on the free one Top of the lower semiconductor chip is removed with a solvent.
  • a photostructurable material has the advantage that the layer of this material can be applied somewhat thicker than the intermediate space, so that subsequently due to the lateral shading at the edges of the upper semiconductor chip, when developing and removing this material, a larger proportion laterally at the edges of the upper Semiconductor chips remain as on the free area of the lower semiconductor chip. In this way, larger spacers are formed on the edges of the top chip in a simple manner, which reliably seal the space between the semiconductor chips.
  • bottom chip 1 In the figure are an arrangement of a larger lower semiconductor chip (bottom chip 1) and a smaller upper one
  • top chip 2 shown in cross section.
  • the component tops of the chips face each other and are permanently attached to each other.
  • These top sides usually each carry wiring levels 11, 12 from one or more metallization levels, which are structured according to the wiring to interconnects and are separated from one another by intermetallic dielectrics.
  • the top chips are placed upside down on a wafer, which still contains the bottom chips in the wafer assembly, and fastened on the respective bottom chips.
  • the mutually assigned connection contacts of the chips become permanently electrically conductive through rewiring 3 or vertical electrically conductive connections 4 between connection contacts arranged directly one above the other interconnected, which can be done with one of the known soldering methods.
  • Spacers are designed such that, as can be seen in the cross-section in the figure, the lateral edges of the smaller upper semiconductor chip (top chip 2) are passivated with the material. A particularly reliable sealing of the space between the semiconductor chips to the outside is thus achieved.
  • An advantage of this arrangement is in particular that the connection contact surfaces 5 of the bottom chip 1 on the side of the top chip 2 are kept completely free of the material of the spacers 7, so that electrical connections, for. B. a bond wire 6 shown in the figure can be attached there.
  • the wafers equipped with the top chips are coated with a photostructurable polymer (for example polyimide, BCB) in a first exemplary embodiment.
  • a photostructurable polymer for example polyimide, BCB
  • a material with a sufficiently low viscosity is selected that penetrates into the gap between the chips and preferably fills the gap completely, or at least at the edge. This process can be supported by the fact that the wafer with the material in the
  • the wafer is floodlit, with the top chips shading the penetrated portions of the applied material.
  • the photostructurable polymer is then developed to remove the exposed portions.
  • all areas next to the top chips are exposed again, in particular also the connection contact areas (bond pads) for external electrical connections. Enough.
  • the gap between the chips is sealed and prevents corrosion of the conductor surfaces between the chips.
  • the exposed surfaces can then z. B. be gold-plated without current.
  • the width of the spacer can be controlled by the type of exposure.
  • the exposure dose required for the complete exposure of the layer made of photostructurable polymer or photoresist increases with the layer thickness.
  • a higher unexposed residual portion (“lacquer foot") remains at a low exposure dose, which provides the desired particularly good sealing of the space between the Chips.
  • diffuse exposure e.g. B.
  • the lateral portion of the spacer 7 becomes thicker or higher, since an additional shading effect by the top chip occurs directly next to the edge of the top chip. While the diffuse radiation from a half solid angle (2 ⁇ / 3) is incident on the other surfaces, only the radiation from a quarter solid angle ( ⁇ / 3) hits the edge of the top chip.
  • a spacer can also be used to prevent undercutting of the chip stack in wet chemical etching processes. In this case, it is advantageous to produce the spacer from photoresist, since the photoresist can easily be removed again after the etching.
  • any potting compound or adhesive can be used as the material of the spacers, even without a photosensitive component.
  • the material used only has to have a sufficiently low viscosity in order to be able to penetrate into the gap between the semiconductor chips.
  • the surfaces of the bottom chip not covered by the top chip become exposed by a solvent from the potting compound or the adhesive. A slight penetration of the solvent between the chips of the semiconductor stack can be tolerated, even if this removes the passivation layer in an outer edge area of the intermediate space.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention relates to a semiconductor chip stack, wherein an intermediate gap between the semiconductor chips (1,2) is filled at least along the edge of the top side of the top chip (2) by a spacer (7) made of a photostructurable polymer, a photo-resist of a casting compound or an adhesive and thus outwardly sealed. Terminal contact surfaces (5) for bond wires (6) or other external connections are kept free from the material of said spacer on the top side of the bottom chip (1).

Description

Beschreibungdescription
Halbleiterchipstapel und Verfahren zur Passivierung eines HalbleiterchipstapelsSemiconductor chip stack and method for passivating a semiconductor chip stack
Halbleiterchipstapel können hergestellt werden, indem zwei Halbleiterchips, die jeweils eine mit mindestens einem elektronischen Bauelement und einer Verdrahtungsebene versehene Oberseite aufweisen, mit diesen Oberseiten einander zugewandt dauerhaft miteinander verbunden werden, wobei Anschlusskontakte der jeweiligen Halbleiterchips über eine Umverdrahtung oder eine vertikale elektrisch leitende Verbindung direkt elektrisch miteinander verbunden werden. Diese Anordnung (face to face) hat den Nachteil, dass eine Passivierung des zwischen den Halbleiterchips verbleibenden Zwischenraumes oder Spaltes nur schwer möglich ist. Durch eine solche Passivierung soll der weitere Montageprozess nicht behindert werden; insbesondere sollen auf einem Bottom-Chip vorhandene Anschlusskontaktflächen für externen Anschluss, z. B. mittels Bonddrähten, nicht kontaminiert werden.Semiconductor chip stacks can be produced in that two semiconductor chips, each having an upper side provided with at least one electronic component and a wiring level, are permanently connected to one another with these upper sides, with connection contacts of the respective semiconductor chips being electrically electrically connected via rewiring or a vertical electrically conductive connection be connected to each other. This arrangement (face to face) has the disadvantage that passivation of the space or gap remaining between the semiconductor chips is difficult. The further assembly process should not be hindered by such a passivation; in particular, existing on a bottom chip connection contact surfaces for external connection, for. B. are not contaminated by means of bond wires.
Üblicherweise werden die Chips mit Oxinitrid und Polyimid passiviert. Das erfordert aber eine nachträgliche fotolithographische Öffnung der Anschlusskontaktflächen (Bondpads) . Eine Lithographie ist auf den bestückten Wafern nur schwer möglich, weil sich die Scheiben, die die noch nicht vereinzelten Bottom-Chips enthalten, mit den aufgesetzten Top-Chips schlecht mit Lackschichten versehen und belichten lassen. Die Passivierung ist insbesondere erschwert, wenn Leiterbahnen auf der Oberseite des Bottom-Chips von der freien Oberseite unter die aufgesetzten Top-Chips führen. Die Anschlusskontaktflächen sind außerdem sehr eng neben die Top-Chips platziert (wenige hundert Mikrometer) , so dass eine Versiegelung des Zwischenraumes mit herkömmlichen Gehäusevergussmassen ausscheidet. Aufgabe der vorliegenden Erfindung ist es, eine Möglichkeit zur Passivierung des Zwischenraumes zwischen face-to-face- montierten Halbleiterchips anzugeben.The chips are usually passivated with oxynitride and polyimide. However, this requires a subsequent photolithographic opening of the connection contact surfaces (bond pads). Lithography on the assembled wafers is difficult because the wafers that contain the bottom chips, which have not yet been separated, can hardly be coated with layers of lacquer and exposed using the top chips. Passivation is particularly difficult when conductor tracks on the top of the bottom chip lead from the free top to the top chips placed on top. The connection contact surfaces are also placed very close to the top chips (a few hundred micrometers), so that sealing the space with conventional potting compounds is ruled out. The object of the present invention is to provide a possibility for passivating the intermediate space between face-to-face mounted semiconductor chips.
Diese Aufgabe wird mit dem Halbleiterchipstapel mit den Merkmalen des Anspruches 1 bzw. mit dem Verfahren zur Passivierung von Halbleiterchipstapeln mit den Merkmalen des Anspruches 7 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.This object is achieved with the semiconductor chip stack with the features of claim 1 and with the method for passivation of semiconductor chip stacks with the features of claim 7. Refinements result from the dependent claims.
Bei dem Halbleiterchipstapel ist ein zwischen den Halbleiterchips vorhandener Zwischenraum zumindest längs eines Randes der Oberseite des kleineren oberen Halbleiterchips (Top-Chip) durch einen Spacer aus einem fotostrukturierbaren Polymer, einem Fotolack, einer Vergussmasse oder einem Klebstoff gefüllt und so nach außen verschlossen. Dabei sind die Anschlusskontaktflächen für Bonddrähte oder andere externe Anschlüsse auf der Oberseite des anderen Halbleiterchips (Bottom-Chip) von dem Material dieses Spacers frei gehalten. Statt nur eines Spacers in dem Zwischenraum kann auch ein an den Flanken des oberen Halbleiterchips angebrachter größerer Spacer für eine bessere Abdichtung des Zwischenraumes vorgesehen werden.In the semiconductor chip stack, an intermediate space present between the semiconductor chips is filled at least along an edge of the upper side of the smaller upper semiconductor chip (top chip) by a spacer made of a photostructurable polymer, a photoresist, a sealing compound or an adhesive and is thus sealed off from the outside. The connection contact surfaces for bond wires or other external connections on the top of the other semiconductor chip (bottom chip) are kept free of the material of this spacer. Instead of only one spacer in the intermediate space, a larger spacer attached to the flanks of the upper semiconductor chip can also be provided for better sealing of the intermediate space.
Vorzugsweise wird als Material ein Fotolack verwendet, der nach der Montage des Chipstapels in den Zwischenraum eindringt und den Zwischenraum vorzugsweise vollständig füllt. Der Fotolack kann dann belichtet werden, wobei der in dem Zwischenraum vorhandene Anteil durch den oberen Halbleiter- chip abgeschattet wird. Der belichtete Anteil wird in der von der Lithographietechnik an sich bekannten Weise mit einer Entwicklerflüssigkeit behandelt und entfernt. Im Prinzip ist hierzu ein beliebiges fotostrukturierbares Polymer geeignet, insbesondere Polyimid oder BCB.A photoresist is preferably used as the material, which penetrates into the intermediate space after assembly of the chip stack and preferably completely fills the intermediate space. The photoresist can then be exposed, the portion present in the intermediate space being shadowed by the upper semiconductor chip. The exposed portion is treated and removed with a developer liquid in the manner known per se from lithography technology. In principle, any photostructurable polymer is suitable for this, in particular polyimide or BCB.
Es kann aber auch eine Vergussmasse, insbesondere ein Epoxidharz, oder ein Klebstoff verwendet werden, der auf der freien Oberseite des unteren Halbleiterchips mit einem Lösungsmittel entfernt wird. Ein fotostrukturierbares Material hat demgegenüber den Vorteil, dass die Schicht dieses Materials etwas dicker als der Zwischenraum aufgebracht werden kann, so dass anschließend infolge der seitlichen Abschattung an den Rändern des oberen Halbleiterchips beim Entwickeln und Entfernen dieses Materiales ein größerer Anteil seitlich an den Rändern des oberen Halbleiterchips stehen bleibt als auf der freien Fläche des unteren Halbleiterchips . Es werden so auf einfache Weise an den Flanken des Top-Chips randseitige größere Spacer gebildet, die den Zwischenraum zwischen den Halbleiterchips zuverlässig abdichten.However, it is also possible to use a casting compound, in particular an epoxy resin, or an adhesive based on the free one Top of the lower semiconductor chip is removed with a solvent. In contrast, a photostructurable material has the advantage that the layer of this material can be applied somewhat thicker than the intermediate space, so that subsequently due to the lateral shading at the edges of the upper semiconductor chip, when developing and removing this material, a larger proportion laterally at the edges of the upper Semiconductor chips remain as on the free area of the lower semiconductor chip. In this way, larger spacers are formed on the edges of the top chip in a simple manner, which reliably seal the space between the semiconductor chips.
Es folgt eine genauere Beschreibung von Beispielen des Halb- leiterchipstapels und des Verfahrens anhand der beigefügten Figur. Diese Figur zeigt im Querschnitt eine Anordnung eines Halbleiterchipstapels .A more detailed description of examples of the semiconductor chip stack and the method follows with the aid of the attached figure. This figure shows an arrangement of a semiconductor chip stack in cross section.
In der Figur sind eine Anordnung aus einem größeren unteren Halbleiterchip (Bottom-Chip 1) und einem kleineren oberenIn the figure are an arrangement of a larger lower semiconductor chip (bottom chip 1) and a smaller upper one
Halbleiterchip (Top-Chip 2) im Querschnitt dargestellt. Die mit Bauelementen versehenen Oberseiten der Chips sind einander zugewandt (face to face) und dauerhaft aneinander befestigt. Diese Oberseiten tragen üblicherweise jeweils Verdrah- tungsebenen 11, 12 aus einer oder mehreren Metallisierungsebenen, die entsprechend der Verdrahtung zu Leiterbahnen strukturiert und durch Zwischenmetalldielektrika voneinander getrennt sind.Semiconductor chip (top chip 2) shown in cross section. The component tops of the chips face each other and are permanently attached to each other. These top sides usually each carry wiring levels 11, 12 from one or more metallization levels, which are structured according to the wiring to interconnects and are separated from one another by intermetallic dielectrics.
Zur Herstellung des Chipstapels werden die Top-Chips upside down auf einen Wafer aufgesetzt, der die Bottom-Chips noch im Waferverbund enthält, und auf den jeweiligen Bottom-Chips befestigt. Die jeweils einander zugeordneten Anschlusskontakte der Chips werden durch Umverdrahtungen 3 oder vertikale elek- trisch leitende Verbindungen 4 zwischen direkt übereinander angeordneten Anschlusskontakten dauerhaft elektrisch leitend miteinander verbunden, was mit einem der an sich bekannten Lötverfahren geschehen kann.To produce the chip stack, the top chips are placed upside down on a wafer, which still contains the bottom chips in the wafer assembly, and fastened on the respective bottom chips. The mutually assigned connection contacts of the chips become permanently electrically conductive through rewiring 3 or vertical electrically conductive connections 4 between connection contacts arranged directly one above the other interconnected, which can be done with one of the known soldering methods.
Es befindet sich bei dieser Anordnung zwischen den Chips ein feiner Zwischenraum oder Spalt, der erfindungsgemäß mit einem Spacer 7 aus einem fotostrukturierbaren Polymer, einem Fotolack, einer Vergussmasse oder einem Klebstoff passiviert ist. Mit dem Spacer kann der gesamte Zwischenraum ausgefüllt sein oder, wie in der Figur dargestellt, nur der schmale Bereich längs des Randes des Top-Chips 2. Vorzugsweise werden dieIn this arrangement, there is a fine space or gap between the chips, which according to the invention is passivated with a spacer 7 made of a photostructurable polymer, a photoresist, a potting compound or an adhesive. The entire space can be filled with the spacer or, as shown in the figure, only the narrow area along the edge of the top chip 2
Spacer so ausgebildet, dass, wie in der Figur im Querschnitt erkennbar, auch die seitlichen Kanten des kleineren oberen Halbleiterchips (Top-Chip 2) mit dem Material passiviert sind. Es ist damit eine besonders zuverlässige Abdichtung des Zwischenraumes zwischen den Halbleiterchips nach außen bewirkt. Ein Vorteil dieser Anordnung liegt insbesondere darin, dass die Anschlusskontaktflächen 5 des Bottom-Chips 1 seitlich des Top-Chips 2 von dem Material der Spacer 7 völlig frei gehalten sind, so dass elektrische Anschlüsse, z. B. ein in der Figur eingezeichneter Bonddraht 6, dort angebracht werden können.Spacers are designed such that, as can be seen in the cross-section in the figure, the lateral edges of the smaller upper semiconductor chip (top chip 2) are passivated with the material. A particularly reliable sealing of the space between the semiconductor chips to the outside is thus achieved. An advantage of this arrangement is in particular that the connection contact surfaces 5 of the bottom chip 1 on the side of the top chip 2 are kept completely free of the material of the spacers 7, so that electrical connections, for. B. a bond wire 6 shown in the figure can be attached there.
Zur Herstellung dieser Anordnung werden in einem ersten Aus- führungsbeispiel die mit den Top-Chips bestückten Wafer mit einem fotostrukturierbaren Polymer (z. B. Polyimid, BCB) beschichtet . Es wird ein Material mit einer ausreichend geringen Viskosität ausgewählt, das in den Spalt zwischen den Chips eindringt und den Spalt vorzugsweise vollständig, oder aber zumindest randseitig ausfüllt. Dieser Vorgang kann da- durch unterstützt werden, dass der Wafer mit dem Material imTo produce this arrangement, the wafers equipped with the top chips are coated with a photostructurable polymer (for example polyimide, BCB) in a first exemplary embodiment. A material with a sufficiently low viscosity is selected that penetrates into the gap between the chips and preferably fills the gap completely, or at least at the edge. This process can be supported by the fact that the wafer with the material in the
Vakuum beschichtet wird. Dann wird der Wafer mit Flutlicht bestrahlt, wobei die Top-Chips die eingedrungenen Anteile des aufgebrachten Materiales abschatten. Anschließend wird das fotostrukturierbare Polymer entwickelt, um die belichteten Anteile zu entfernen. Dadurch werden alle Flächen neben den Top-Chips wieder freigelegt, insbesondere auch die Anschlusskontaktflächen (Bondpads) für externen elektrischen An- schluss. Der Spalt zwischen den Chips ist versiegelt und verhindert die Korrosion der zwischen den Chips vorhandenen Leiterflächen. Die freiliegenden Flächen können dann z. B. stromlos vergoldet werden.Vacuum coated. Then the wafer is floodlit, with the top chips shading the penetrated portions of the applied material. The photostructurable polymer is then developed to remove the exposed portions. As a result, all areas next to the top chips are exposed again, in particular also the connection contact areas (bond pads) for external electrical connections. Enough. The gap between the chips is sealed and prevents corrosion of the conductor surfaces between the chips. The exposed surfaces can then z. B. be gold-plated without current.
Die Breite des Spacers kann durch die Art der Belichtung gesteuert werden. Bei einer Belichtung mit kollimiertem Licht wird ausgenutzt, dass die für die vollständige Belichtung der Schicht aus fotostrukturierbarem Polymer oder Fotolack benö- tigte Belichtungsdosis mit der Schichtdicke zunimmt. An den Kanten des Top-Chips, wo sich die Schichtdicke höher ausbildet als auf den offenen Flächen des Bottom-Chips, bleibt daher bei niedriger Belichtungsdosis ein höherer unbelichteter Restanteil ("Lackfuß") stehen, der die erwünschte besonders gute Versiegelung des Zwischenraumes zwischen den Chips bewirkt. Wenn eine diffuse Belichtung angewandt wird, die z. B. durch den Einbau einer Mattscheibe in den Belichtungsautomaten anstelle einer Lithographiemaske erreicht werden kann, wird der seitliche Anteil des Spacers 7 dicker oder höher, da direkt neben der Kante des Top-Chips ein zusätzlicher Ab- schattungseffekt durch den Top-Chip auftritt. Während auf den übrigen Flächen die diffuse Strahlung aus einem halben Raumwinkel (2π/3) einfällt, trifft an der Kante des Top-Chips nur die Strahlung aus einem viertel Raumwinkel (π/3) auf.The width of the spacer can be controlled by the type of exposure. In the case of exposure with collimated light, use is made of the fact that the exposure dose required for the complete exposure of the layer made of photostructurable polymer or photoresist increases with the layer thickness. At the edges of the top chip, where the layer thickness is higher than on the open surfaces of the bottom chip, a higher unexposed residual portion ("lacquer foot") remains at a low exposure dose, which provides the desired particularly good sealing of the space between the Chips. If diffuse exposure is used, e.g. B. can be achieved by installing a focusing screen in the exposure machine instead of a lithography mask, the lateral portion of the spacer 7 becomes thicker or higher, since an additional shading effect by the top chip occurs directly next to the edge of the top chip. While the diffuse radiation from a half solid angle (2π / 3) is incident on the other surfaces, only the radiation from a quarter solid angle (π / 3) hits the edge of the top chip.
Ein Spacer kann auch dazu benutzt werden, bei nasschemischen Ätzprozessen ein Unterätzen des Chipstapels zu verhindern. In diesem Fall ist es vorteilhaft, den Spacer aus Fotolack herzustellen, da der Fotolack nach der Ätzung leicht wieder ent- fernt werden kann.A spacer can also be used to prevent undercutting of the chip stack in wet chemical etching processes. In this case, it is advantageous to produce the spacer from photoresist, since the photoresist can easily be removed again after the etching.
Es können als Material der Spacer grundsätzlich beliebige Vergussmassen oder Kleber, auch ohne fotosensitiven Anteil, benutzt werden. Das verwendete Material muss nur eine ausrei- chend geringe Viskosität aufweisen, um in den Spalt zwischen den Halbleiterchips eindringen zu können. Die von dem Top- Chip nicht bedeckten Oberflächen des Bottom-Chips werden durch ein Lösemittel von der Vergussmasse oder dem Klebstoff freigelegt. Ein geringfügiges Eindringen des Lösemittels zwischen die Chips des Halbleiterstapels kann toleriert werden, auch wenn dadurch die Passivierungsschicht in einem äußeren Randbereich des Zwischenraumes wieder entfernt wird. In principle, any potting compound or adhesive can be used as the material of the spacers, even without a photosensitive component. The material used only has to have a sufficiently low viscosity in order to be able to penetrate into the gap between the semiconductor chips. The surfaces of the bottom chip not covered by the top chip become exposed by a solvent from the potting compound or the adhesive. A slight penetration of the solvent between the chips of the semiconductor stack can be tolerated, even if this removes the passivation layer in an outer edge area of the intermediate space.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
1 Bottom-Chip1 bottom chip
2 Top-Chip 3 Umverdrahtung2 top chip 3 rewiring
4 elektrisch leitende Verbindung4 electrically conductive connection
5 Anschlusskontaktfläche5 connection contact surface
6 Bonddraht6 bond wire
7 Spacer 11 Verdrahtungsebenen 12 Verdrahtungsebenen 7 spacers 11 wiring levels 12 wiring levels

Claims

Patentansprüche claims
1. Halbleiterchipstapel mit mindestens zwei Halbleiterchips (1, 2) , die - jeweils eine mit mindestens einem elektronischen Bauelement und mindestens einem Anschlusskontakt versehene Oberseite aufweisen und1. A semiconductor chip stack with at least two semiconductor chips (1, 2), each having an upper side provided with at least one electronic component and at least one connection contact, and
- in einer Anordnung, bei der die besagten Oberseiten einander zugewandt sind, dauerhaft miteinander verbunden sind, wo- bei mindestens zwei einander zugeordnete Anschlusskontakte der Halbleiterchips (1, 2) elektrisch leitend miteinander verbunden sind, d a d u r c h g e k e n n z e i c h n e t , dass ein zwischen den Halbleiterchips (1, 2) vorhandener Zwischen- räum zumindest in einem Streifen längs eines Randes der Oberseite des einen Halbleiterchips (2) durch einen Spacer (7) aus einem fotostrukturierbaren Polymer, einem Fotolack, einer Vergussmasse oder einem Klebstoff gefüllt und nach außen verschlossen ist, wobei mindestens eine Anschlusskontaktfläche (5) auf der Oberseite des anderen Halbleiterchips (1) von dem Material dieses Spacers (7) frei gehalten ist.- In an arrangement in which the said tops face each other, are permanently connected to one another, with at least two mutually assigned connection contacts of the semiconductor chips (1, 2) being connected to one another in an electrically conductive manner, characterized in that a between the semiconductor chips (1, 2) existing space is filled at least in a strip along an edge of the upper side of the one semiconductor chip (2) by a spacer (7) made of a photostructurable polymer, a photoresist, a potting compound or an adhesive and closed to the outside, at least one Connection contact surface (5) on the top of the other semiconductor chip (1) is kept free of the material of this spacer (7).
2. Halbleiterchipstapel nach Anspruch 1, bei dem das Material des Spacers (7) ein fotostrukturierbares Polymer ist.2. The semiconductor chip stack according to claim 1, wherein the material of the spacer (7) is a photo-structurable polymer.
3. Halbleiterchipstapel nach Anspruch 2, bei dem das Polymer Polyimid oder BCB ist .3. The semiconductor chip stack according to claim 2, wherein the polymer is polyimide or BCB.
4. Halbleiterchipstapel nach Anspruch 1, bei dem das Material des Spacers (7) eine Vergussmasse ist, die ein Epoxidharz enthält .4. The semiconductor chip stack according to claim 1, wherein the material of the spacer (7) is a potting compound that contains an epoxy resin.
5. Halbleiterchipstapel nach Anspruch 1, bei dem das Material des Spacers (7) ein Klebstoff ist. 5. The semiconductor chip stack according to claim 1, wherein the material of the spacer (7) is an adhesive.
6. Halbleiterchipstapel nach einem der Ansprüche 1 bis 5, bei dem der Zwischenraum zwischen den Halbleiterchips (1, 2) mit dem Material des Spacers gefüllt ist.6. The semiconductor chip stack according to one of claims 1 to 5, wherein the space between the semiconductor chips (1, 2) is filled with the material of the spacer.
7. Verfahren zur Passivierung eines Halbleiterchipstapels mit mindestens zwei Halbleiterchips (1, 2) , die7. Method for passivation of a semiconductor chip stack with at least two semiconductor chips (1, 2), the
- jeweils eine mit mindestens einem elektronischen Bauelement und mindestens einem Anschlusskontakt versehene Oberseite aufweisen undeach have an upper side provided with at least one electronic component and at least one connection contact, and
- in einer Anordnung, bei der die besagten Oberseiten einander zugewandt sind, dauerhaft miteinander verbunden sind, wobei mindestens zwei einander zugeordnete Anschlusskontakte der Halbleiterchips (1, 2) elektrisch leitend miteinander verbunden sind, d a d u r c h g e k e n n z e i c h n e t , dass in einem ersten Schritt ein Material ausreichend geringer Viskosität auf die Oberseite des einen Halbleiterchips (1) aufgebracht wird, so dass ein zwischen den Halbleiterchips (1, 2) vorhandener Zwischenraum zumindest längs eines Randes der Oberseite des anderen Halbleiterchips (2) mit diesem Material gefüllt wird, und in einem zweiten Schritt das Material von der Oberseite des ersten Halbleiterchips (1) so weitgehend entfernt wird, dass eine Anschlusskontaktfläche (5) auf dieser Oberseite freigelegt wird und dabei der Zwischenraum zwischen den Halbleiterchips nach außen abgedichtet bleibt.- In an arrangement in which the said tops face each other, are permanently connected to one another, at least two associated contact contacts of the semiconductor chips (1, 2) being connected to one another in an electrically conductive manner, characterized in that in a first step a material of sufficiently low viscosity is applied to the top of the one semiconductor chip (1), so that an intermediate space between the semiconductor chips (1, 2) is filled with this material at least along an edge of the top of the other semiconductor chip (2), and in a second step the material is largely removed from the upper side of the first semiconductor chip (1) in such a way that a connection contact surface (5) is exposed on this upper side and the space between the semiconductor chips remains sealed to the outside.
8. Verfahren nach Anspruch 7, bei dem in dem ersten Schritt ein fotostrukturierbares Polymer oder ein Fotolack auf die Oberseite des ersten Halbleiterchips (1) aufgebracht wird, in einem weiteren Schritt dieses Material belichtet wird, wobei ein Anteil des Materials in dem Zwischenraum unbelichtet bleibt, und in dem zweiten Schritt der belichtete Anteil entfernt wird. 8. The method according to claim 7, in which in the first step a photostructurable polymer or a photoresist is applied to the top of the first semiconductor chip (1), in a further step this material is exposed, a portion of the material remaining unexposed in the intermediate space , and in the second step the exposed portion is removed.
9. Verfahren nach Anspruch 8 , bei dem in dem ersten Schritt das Material dicker als der Zwischenraum aufgebracht wird, in dem weiteren Schritt eine diffuse Belichtung erfolgt, so dass das Material seitlich des zweiten Halbleiterchips (2) geringer belichtet wird, und in dem dritten Schritt das belichtete Material entfernt wird, so dass an seitlichen Kanten des zweiten Halbleiterchips (2) Spacer (7) aus diesem Material stehen bleiben, die den Zwi- schenraum nach außen abdichten.9. The method according to claim 8, in which in the first step the material is applied thicker than the intermediate space, in the further step a diffuse exposure takes place, so that the material on the side of the second semiconductor chip (2) is exposed less, and in the third Step the exposed material is removed so that spacers (7) made of this material remain on the lateral edges of the second semiconductor chip (2) and seal the intermediate space from the outside.
10. Verfahren nach Anspruch 7, bei dem in dem ersten Schritt eine Vergussmasse oder ein Klebstoff ausreichend geringer Viskosität auf die Oberseite des einen Halbleiterchips (1) aufgebracht wird und in dem zweiten Schritt die Nergussmasse oder der Klebstoff unter Verwendung eines Lösungsmittels außerhalb des Zwischenraumes entfernt wird. 10. The method according to claim 7, in which in the first step a casting compound or an adhesive of sufficiently low viscosity is applied to the top of the one semiconductor chip (1) and in the second step the casting compound or adhesive is removed using a solvent outside the intermediate space becomes.
EP03788833A 2003-01-10 2003-12-02 Semiconductor chip stack and method for passivating a semiconductor chip stack Withdrawn EP1581965A2 (en)

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