EP1324392B1

EP1324392B1 - Capacitor for semiconductor integrated devices

Info

Publication number: EP1324392B1
Application number: EP01830821A
Authority: EP
Inventors: Raffaele Zambrano; Cesare Artoni
Original assignee: STMicroelectronics SRL; SGS Thomson Microelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2001-12-28
Filing date: 2001-12-28
Publication date: 2009-12-09
Anticipated expiration: 2021-12-28
Also published as: DE60140757D1; EP1324392A1; US7049646B2; US20030146460A1

Description

The present invention relates to a ferroelectric capacitor for semiconductor integrated devices and to the fabrication process thereof.
More specifically, the invention relates to a capacitor for a ferroelectric memory device integrated in a semiconductor substrate and of the type comprising a control circuitry and an array of ferroelectric memory cells.
As is known and shown in Figure 1, a ferroelectric cell 1 is formed by a MOS transistor 2 and a capacitor 3 which has, as dielectric, a ferroelectric material, for example PZT (PbZr_1-xTi_xO₃), SBT (SrBi₂Ta₂O₉) or BLT (Bi_4-xLa_xTi₃O₁₂) or a paraelectric material, for example BST (BaSr_1-xTi_xO₃). More in particular, in the ferroelectric cell 1, the MOS transistor 2 is an N-channel transistor and has a drain terminal 4 connected to the bit line BL, a gate electrode 5 connected to a word line WL, and a source terminal 6 connected to a first electrode 7 of the capacitor 3. A second electrode 8 of the capacitor 3 is connected to a plate line PL.
The cell can store binary information by virtue of the hysteresis characteristics of the ferroelectric material comprised between the electrodes 7 and 8 and assuming, when no voltage is applied, two biasing states, according to the voltage previously applied to the electrodes of the capacitor 3.
The ferroelectric cells currently known may be in a strapped or in a stacked configuration. In the cells with strapped configuration, an example of which is shown in Figure 2, the capacitor 3 is made on top of a field oxide region 10 delimiting an active area 11 of a substrate 12 which houses conductive regions - source region 14 and drain region 13 - of the MOS transistor 2. In greater detail, the first electrode 7 of the capacitor 3 is arranged at the top and comprises a conductive region (for example of platinum) having a square or rectangular shape, connected to the drain region 13 of the MOS transistor 2 through a metal connection 16. The second electrode 8 of the capacitor 3 is arranged at the bottom and comprises a layer of conductive material (for example, platinum) which extends perpendicular to the sheet plane and forms a plate line PL, connected to the other capacitors of the adjacent cells. A dielectric region 17, of ferroelectric material, is comprised between the first electrode 7 and the second electrode 8. The gate electrode 5 of the MOS transistor 2 is of a polycrystalline silicon layer 18, which extends perpendicular to the sheet plane and forms a word line WL.
In the cells with stacked configuration, an example whereof is shown in Figure 3, the capacitor 3 is formed on top of the active area 11, directly above the source region 14 of the transistor 2. In this case, the first electrode 7 of the capacitor 3 is arranged at the bottom and comprises a conductive region (for example, of platinum) having a square or rectangular shape, connected to the source region 14 through a contact 23 formed in an opening of a protective layer 24 (for example of BPSG), and the second electrode 8, of conductive material, is arranged at the top and is connected to the metal layer 25, thus defining the plate line PL.
Materials having barrier properties against oxygen (such as Ir/IrO₂) 26 extend underneath the first electrode 7 and delimit at the top the contact 23.
Figure 4 shows the architecture of an array 28 of ferroelectric cells in the open bit line configuration. As may be seen, the ferroelectric cells 1 are arranged in rows and columns and are connected so that pairs of cells 27 are arranged parallel to the bit lines BL; the MOS transistors 2 of each pair of cells 27 have common drain regions, which are connected to the same bit line BL; and the capacitors 3 that belong to one pair of cells 27 adjacent in a direction parallel to the bit lines BL are connected to two adjacent plate lines PL.
The ferroelectric cells in stacked configuration are preferred since they satisfy the size scaling requirement of new CMOS technologies.
Various examples of cells in stacked configuration are disclosed in which both the electrodes 7, 8 and the dielectric region 17 are defined using a single mask and forming the plate line PL with a special metal layer. In another embodiment, the bottom electrode 7 comprises a conductive region formed separately, while the dielectric region 17 and the top electrode 8 are mutually aligned and formed with a single mask.
In all the above cases, etching at least one of the electrodes 7 and 8 with the same mask used for etching the ferroelectric material that constitutes the dielectric region 17 is critical. For example, during etching, compounds are formed that may redeposit along the edge of the capacitor and short circuit it. On the other hand, separate definition of the three parts forming the capacitor 3 (the two electrodes 7 and 8 and the dielectric region 17), which should solve the problem due to the fabrication processes, leads to an increase in the overall dimensions, thus going against the current trend of size scaling. In fact, when making the definition mask, it is necessary to take into account both the alignment tolerances and the minimum distances between the bottom electrode and the top electrode (for example, a distance of 0.4 µm). In particular, the bottom electrode 7 must be, on every side, larger than the dielectric region 17 by an amount at least equal to the alignment tolerance (for example, at least 0.2 µm). Likewise, the dielectric region 17 must be larger than the top electrode 8 by the same amount. Consequently, taking into account the minimum distance between the bottom electrodes 7, the overall dimensions of the capacitor 3, and consequently of the ferroelectric cells 1, are excessive.
In US patent No. 6 300 654 granted on 9.10.2001 to the present applicant, the above disadvantages are eliminated in a memory cell in stacked configuration. In practice, the distance between the dielectric regions of at least two ferroelectric memory cells adjacent in the direction of the bit lines is reduced. In particular, the dielectric region 17 is continuous and is shared between the two adjacent capacitors that belong to a pair of adjacent cells. In this way, the layout rules for scaling the capacitor are dictated only by the distance between two adjacent bottom electrodes and by the lateral space between the top and the bottom electrodes. This enables, for a same cell area, maximization of the working area of the capacitor as compared to the layout of the solution using three masks for defining the capacitor, wherein the dielectric region of cells that are adjacent in the direction of the bit lines is separated. Furthermore, the solution described in the above mentioned US patent causes an increase in the amplitude of the signal (proportional to the active area of the capacitor) supplied by each cell to the sense amplifier during reading.
The above known solution moreover affords the following advantages:

1) the ratio between the area of the capacitor and the total area of the cell is maximized; and
2) the critical points in the photolithography step and in the connections of the ferroelectric material are removed.

The current trend is in the direction of further size scaling of the devices.
US-A-5,137,842 discloses a stacked H-cell capacitor according to the preamble of the main claims. Here, in order to increase the storage cell surface area, the first electrode has an H shape including a planar portion and two opposite transverse portions of polysilicon, completely surrounded by a nitride dielectric layer and by a polysilicon second electrode.
WO 01/24237 discloses a ferroelectric memory capacitor wherein the first electrode comprises a barrier layer in electrical contact with a conductive region of a MOS transistor and a conductive region overlying the barrier layer.
US-A-5,605,858 describes a method of forming high-dielectric-constant material electrodes wherein an adhesion layer overlies a substrate and is covered by metal region having spacers on its vertical sides; a stack of a bottom electrode, a dielectric layer and a top electrode extend on top of the metal region and the spacers.
The aim of the present invention is therefore to provide a process that is in line with the above trend, and thus to manufacture a ferroelectric capacitor for a semiconductor device, which has even smaller dimensions and even greater capacitance.
According to the present invention there are provided a stacked type ferroelectric memory cell and the fabrication process thereof, as defined in claims 1 and 17, respectively.
For a better understanding of the present invention, a preferred embodiment thereof is now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

Figure 1 shows the equivalent circuit of a ferroelectric cell;
Figure 2 shows a cross-section of a first type of ferroelectric cell;
Figure 3 shows a cross-section of a second type of ferroelectric cell;
Figure 4 shows the known architecture of an array of memory cells; and
Figure 5 shows a cross-section of one portion of an array of ferroelectric cells according to the invention.

Figure 5 shows the structure of a memory cell 30 comprising a MOS transistor 32 and a ferroelectric capacitor 33, connected in series. The memory cell 30 comprises a substrate 31 of a first conductivity type, for example P, which houses a well 40 with the same conductivity type, i.e., P in the example considered.
MOS transistor 32 comprises a source region 34a and a drain region 34b, of a second conductivity type, namely N, which are formed in the well 40. A thick oxide (field oxide) region 35 is formed on the substrate 30 and defines, in the semiconductor substrate 30, a conduction area (active area), accommodating the well 40 and overlaid by other regions of the MOS transistor 32, including a gate oxide layer 37 and a control electrode 36 (gate region). The control electrode 36 is formed by a double polysilicon and silicide layer and overlies a channel region 41 formed in the well 40 between a source extension region 43a and a drain extension region 43b, which are respectively contiguous to the source region 34a and to the drain region 34b.
In the illustrated embodiment, oxide spacers 38 extend alongside the control electrode 36 on top of the source and drain extension regions 43a, 43b.
The source region 34a and the drain region 34b are connected, via respective contacts 44a, 44b, to the ferroelectric capacitor 33 and to a metal line 53, respectively.
The control gate 36 may possibly be coated with further layers of conductive materials, such as titanium silicide or tungsten silicide.
A first insulating layer 39, for example of oxide doped with boron and phosphorous (BPSG), covers the substrate 30. Openings are formed in the insulating layer 39, over the source region 34a and drain region 34b, and accommodate contacts 44a, 44b. The contacts 44a and 44b comprise, in a known way, not shown in detail, a titanium-nitride layer, which coats the side walls and the bottoms of the openings of the insulating layer 39, and a conductive material, for example tungsten or polysilicon, which fills the space enclosed by the titanium-nitride layer.
The first insulating layer 39 is not planar, but has a projecting portion 39a, arranged at a higher level than the remaining part of the insulating layer 39. The capacitor 33 is formed on top and at the sides of the projecting portion 39a, and comprises a bottom electrode 45, a dielectric region 46 of ferroelectric or paraelectric material, and a top electrode 47.
In detail, the bottom electrode 45 is formed by a stack of layers comprising an adhesion layer 45d, preferably of TiN, at least one barrier layer 45a, preferably of iridium (Ir), a conductive oxide layer 45b, preferably of iridium oxide (IrO₂), and a metal layer 45c, preferably of platinum (Pt). The adhesion layer 45d, barrier layer 45a, conductive oxide layer 45b, and metal layer 45c all have the same width, equal to that of the projecting portion 39a.
The bottom electrode 45, in addition to forming the bottom plate of the capacitor 33, also operates as a protection barrier for tungsten or polysilicon deposited inside the contact 44a. In fact, if no protection were provided, the material of the contact (either W or poly-Si) would undergo oxidation during crystallization of the ferroelectric material (this process must be carried out in an oxidizing environment, and hence the reaction 4W + 5O₂ → 2W₂O₅ could take place, which would insulate the contact 44a from the bottom electrode, besides damaging it from the mechanical standpoint).
An Ir/IrO₂ double layer (formed by the barrier layer 45a and by the conductive oxide layer 45b of the bottom electrode 45) provides, instead, an efficient protection barrier, preventing the oxygen, by diffusing through it, from reaching the contact.
A protection spacer 48 (two portions of which may be seen in Figure 5) is formed on the four vertical sides of the projecting portion 39a and of the bottom electrode 45. The protection spacer 48 is preferably formed by a first spacer layer 48a of iridium and a second spacer layer 48b of iridium oxide, arranged on top of one another.
According to one aspect of the invention, the protection spacer 48 has the function of protecting from oxidation the adhesion layer 45d and the tungsten or the polysilicon deposited inside the contact 44a. In fact, during manufacturing, the oxygen tends to diffuse along the grain edges of the TiN adhesion layer 45d (causing it to lose its electrical conductivity), and could reach as far as tungsten or polysilicon of the contact 44a, oxidizing the latter. In addition, the protection spacer 48 forms a projection of the bottom electrode 45, as will be described hereinafter.
To this aim, a thin platinum (Pt) layer 48c is arranged on top of the first and second spacer layers 48a, 48b.
The dielectric region 46 is formed by a strip of ferroelectric or paraelectric material (for example, SBT, PZT, BLT or BST) which extends in a direction perpendicular to the cross-section of Figure 5, over the bottom electrode 45 and over the protection spacer 48.
The top electrode 47 is formed by a strip of conductive material, preferably platinum, which extends over the dielectric region 46, and thus perpendicular to the sheet plane.
A second insulating layer 51, for example of BPSG, coats the capacitor 33 and the first insulating layer 39 and has a planar top surface. The second insulating layer 51 has an opening, accommodating the top portion of the drain contact 44b, which terminates flush with the top surface of the second insulating layer 51.
A metal line 53 extends on top of the second insulating layer 51 and defines a bit line (Figure 1), and a third insulating layer (not shown) extends on top of the latter and houses further electrical connection lines, contacts, pads, etc., in a per se known manner.
The process for manufacturing the cell 30 of Figure 5 is described hereinafter. After forming the transistor 32, a first insulating layer 39 is deposited, and uniformly coats the underlying structure. After forming the openings in the first insulating layer 39, the first contact 44a and second contact 44b, in a per se known manner, the stack of layers constituting the bottom electrode 45 of the ferroelectric capacitor 33 is deposited.
The stack thus obtained (TiN/Ir/IrO₂/Pt) is defined using a single mask (referred to as "bottom electrode mask") to form the bottom electrode, typically having a square or rectangular shape. Now, it is possible to use a hard mask which ensures greater resistance to chemical etching of the bottom electrode 45 as compared to the resist mask.
According to an aspect of the invention, etching of the bottom electrode 45 proceeds further with an oxide etch which enables partial removal of the first insulating layer 39. Thereby, the projecting portion 39a is formed, which is self aligned to the bottom electrode 45; namely, the vertical walls of the bottom electrode 45 are aligned to the vertical walls of the projecting portion 39a.
Next, the following operations are carried out in sequence:

1) deposition of Ir/IrO₂/Pt (the thickness varies according to the size of the protection spacer 48 that is to be made), followed by a blanket etch with no mask, so as to form the protection spacer 48 and at the same time laterally seal the bottom electrode 45 from the diffusion of the oxygen, as explained previously;
2) deposition of a layer of ferroelectric material (SBT, PZT, or BLT) or paraelectric material (BST or the like);
3) annealing in O₂ for causing transition of the ferroelectric or paraelectric material to the desired crystallographic orientation, and thus to the ferroelectric phase;
4) masking and etching of the layer of ferroelectric or paraelectric material;
5) deposition of platinum or of another metal designed to form the top electrode 47; and
6) masking and etching of the metal just deposited for the definition of the top electrode 47.

Then the following steps are carried out: deposition of the second insulating layer 51, planarization of the structure, opening of vias on top of the bottom portion of the contact 44b, and, wherever necessary, filling of the vias thus obtained, with formation, i.a., of the top portion of the contact 44b, and, finally, deposition and definition of the metal lines, according to known processes.
The structure according to the present invention affords various advantages, the major advantage being that a considerable scaling and densification of the ferroelectric memory array is achieved. In fact, the memory cell 30 presents a considerable increase in the capacitance of the ferroelectric capacitor, due to a larger active surface between the bottom electrode 45 and the top electrode 47, increased by the vertical side walls formed by the protection spacer 48 as regards the bottom electrode 45. This enables, in memory arrays that exploit as elementary information element a ferroelectric capacitor or a pair of ferroelectric capacitors, a considerable reduction in the area occupied by each cell, given the same capacitance, redistributing on the side surfaces part of the facing surfaces of the bottom and top electrodes 45, 47. The structure according to the invention is therefore suited to densification, and consequent increase, of the storage capacity per unit area.
Another advantage lies in the excellent protection barrier for the tungsten or polysilicon contact. In particular, the double Ir/IrO₂ layer formed by the barrier layer 45a and the conductive oxide layer 45b shields the source contact 44a and the adhesion layer 45d from oxidation. Lateral protection of the adhesion layer 45d is ensured by the spacer layers 48a and 48b.
The manufacturing process is extremely simple. In fact, forming the capacitor with the non-planar structure, as described, requires the addition of a few processing steps which are simple and per se known in the art. The resulting morphology is, nonetheless, sturdy and functional.
Finally, according to the invention, there is a considerable saving in consumption of iridium (which is a very precious metal) as compared to solutions in which the increase in capacitance is obtained by using thick Ir/IrO₂ layers.
Finally, it is clear that numerous modifications and variations may be made to the memory cells and fabrication process described and illustrated herein, all falling within the scope of the claims. For example, the protection spacer 48 (which forms side portions of the bottom electrode 45) may be formed, instead of by a single region surrounding all the vertical sides of the projecting portion 39a, by one or more portions that extend on at least one vertical side of the projecting portion 39a, starting from an edge of the planar portion of the bottom electrode 45.

Claims

A memory cell (30) of a stacked type, comprising a MOS transistor (32) formed in an active region (40) of a substrate (30) of semiconductor material and a capacitor (33) formed on top of said active region, said MOS transistor (32) having a conductive region (34a), and said capacitor having non-planar structure including a first electrode (45) and a second electrode (47) separated by a dielectric material region (46);
said conductive region (34a) of said MOS transistor being connected to said first electrode (45) of said capacitor (33) through a contact region (44a) extending through an insulating material layer (39) extending on top of said substrate (30) and having a substantially planar top surface; and
said first electrode (45) comprising a horizontal planar portion (45) in contact with the contact region (44a) and at least one first side portion (48) extending transversely to, and in direct electrical contact with, said planar portion,
characterized in that said memory cell (30) and said capacitor (33) are of a ferroelectric type;
said insulating material layer (39) has a projecting portion (39a) arranged on top of said first conductive region (34a),
said planar portion of said first electrode (45) extends on top of and being aligned with said projecting portion; and
said first side portion (48) of said first electrode (45) is formed on a vertical side of said projecting portion (39a) and extends from said planar portion of said first electrode (45) to said planar top surface of said insulating material layer (39).
The memory cell according to claim 1, characterized in that said first electrode (45) comprises at least one second side portion (48) extending transversely with respect to, and in direct electrical contact with, said planar portion (45), said first and second side portions extending from opposite side ends of said planar portion.
The memory cell according to claim 2, characterized in that said dielectric material region (46) comprises a planar portion, extending on top of and in contact with said horizontal planar portion (45) of said first electrode, and side portions extending on top of and in contact with said side portions (48) of said first electrode.
The memory cell according to claim 3, characterized in that said second electrode (47) comprises a planar portion extending on top of and in contact with said planar portion of said dielectric material region (46), and side portions extending on top of and in contact with said side portions of said dielectric material region (46).
The memory cell according to any of claims 2-4, characterized in that said horizontal planar portion (45) of said first electrode comprises a barrier layer (45a) in electrical contact with said conductive region (34a) of said MOS transistor (32) and a conductive layer (45b) overlying said barrier layer.
The memory cell according to claim 5, characterized in that said first and second side portions (48) of said first electrode (45) comprise a first and a second spacer layer (48a, 48b) arranged on top of one another.
The memory cell according to claim 6, characterized in that said barrier layer (45a) and said first spacer layer (48a) are of iridium.
The memory cell according to claim 6 or 7, characterized in that said conductive layer (45b) of said first electrode (45) and said second spacer layer (48b) are of iridium oxide.
The memory cell according to any one of claims 5 to 8, characterized in that said first electrode further comprises an adhesion layer (45d) arranged between said contact region (44a) and said barrier layer (45a).
The memory cell according to claim 9, characterized in that said adhesion layer (45d) is of titanium nitride.
The memory cell according to any one of claims 5 to 11, characterized in that said first electrode (45) further comprises a metal layer (45c) arranged on top of said conductive layer (45b), and said first and second side portions (48) comprise a top layer (48c) of metal.
The memory cell according to claim 11, wherein said metal layer (45c) and said top layer (48c) are of platinum.
The memory cell according to any one of claims 1 to 12, characterized in that said dielectric material region (46) is of a material chosen from the group comprising SBT, PZT, BLT, and BST.
The memory cell according to any of claims 1 to 13, characterized in that said second electrode (47) is of platinum.
A process for manufacturing a memory cell (30) of a stacked type, comprising the steps of:
forming a MOS transistor (32) having a conductive region (34a) in an active region (40) of a substrate (30) of semiconductor material;

forming an insulating layer (39) on top of said substrate;

forming a contact region (44a) in said insulating layer (39), in contact with the active region (40);

forming, on top of said active region, a capacitor (33) having a non-planar structure, including a first and a second electrodes (45, 47) separated by a dielectric material region (46), the step of forming a capacitor including:
forming an electrode layer (45a, 45b) on top of said insulating layer and in contact with the contact region (44a),

selectively removing said electrode layer (45a, 45b) to form a planar portion (45) of said first electrode;

selectively removing part of said insulating layer (39);

forming at least one first side portion (48) of the first electrode in direct electrical contact with said planar portion;

forming said dielectric material region (46) on top of said planar portion (45) and said first side portion (48) of said first electrode; and

forming said second electrode (47) on top of and in contact with said dielectric material region (46);

characterized in that said capacitor (33) is of a ferroelectric type; and in that the step of selectively removing part of said insulating layer (39) comprises forming a substantially planar top surface of said insulating layer (39) and a projecting portion (39a) having at least one side surface extending transversely to said planar portion of said first electrode;
said first side portion (48) of said first electrode being formed on said side surface of the projecting portion (39a), the at least one side portion (48) extending from the planar portion of the first electrode to the planar top surface of said insulating layer (39).
The process according to claim 15, characterized in that said step of forming an electrode layer (45a, 45b) comprises the steps of forming a barrier layer (45a) on top of said insulating layer (39) and forming a conductive layer (45b) on top of said barrier layer.
The process according to claim 16, characterized in that said step of forming at least one side portion (48) of said first electrode comprises forming a first and a second spacer layers (48a, 48b) arranged on top of one another.
The process according to claim 17, characterized in that said barrier layer (45a) and said first spacer layer (48a) are of iridium.
The process according to claim 17 or 18, characterized in that said conductive layer (45b) of said first electrode (45) and said second spacer layer (48b) are of iridium oxide.
The process according to any one of claims 16 to 19, characterized in that, before forming a barrier layer (45a), the step is carried out of forming an adhesion layer (45d) on top of and in contact with said insulating layer (39).
The process according to claim 20, characterized in that said adhesion layer (45d) is of titanium nitride.
The process according to any of claims 17 to 21, characterized in that, after said step of forming a conductive layer (45b), the step is carried out of forming a metal layer (45c) arranged on top of said conductive layer (45b), and in that, after said step of forming a first and a second spacer layers (48a, 48b), the step is carried out of forming a top layer (48c) of metal material.
The process according to claim 22, characterized in that said metal layer (45c) and said top layer (48c) are of platinum.
The process according to any of claims 15 to 23, characterized in that said step of forming at least one side portion (48) of said first electrode (45) comprises depositing at least a first and a second spacer layer (48a, 48b) on top of said first electrode, and blanket etching said first and second spacer layers.
The process according to any of claims 15 to 24, characterized in that said dielectric material region (46) is of a material chosen from the group comprising SBT, PZT, BLT, and BST.
The process according to any of claims 15 to 24, characterized in that said second electrode (47) is of platinum.