EP1096383A1 - Rekonfigurierbarer Farbkonverter - Google Patents

Rekonfigurierbarer Farbkonverter Download PDF

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Publication number
EP1096383A1
EP1096383A1 EP00410126A EP00410126A EP1096383A1 EP 1096383 A1 EP1096383 A1 EP 1096383A1 EP 00410126 A EP00410126 A EP 00410126A EP 00410126 A EP00410126 A EP 00410126A EP 1096383 A1 EP1096383 A1 EP 1096383A1
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EP
European Patent Office
Prior art keywords
address
code
codes
output
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00410126A
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English (en)
French (fr)
Inventor
Marc Laury
Franck Seignert
Emmanuel Chiaruzzi
Philippe Monnier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
SGS Thomson Microelectronics SA
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Filing date
Publication date
Application filed by STMicroelectronics SA, SGS Thomson Microelectronics SA filed Critical STMicroelectronics SA
Publication of EP1096383A1 publication Critical patent/EP1096383A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction

Definitions

  • the present invention relates to circuits for digital image processing, and in particular a circuit to modify the coding of colors associated with pixels of a digital image.
  • a digital image is conventionally composed of rows and columns of pixels. Each pixel of the image is associated in particular with a color.
  • a common type of color coding is the so-called RGB coding, in which the colors are represented by three components: red (R), green (V) and blue (B), each of which is conventionally coded on the same number of bits.
  • RGB coding in which the colors are represented by three components: red (R), green (V) and blue (B), each of which is conventionally coded on the same number of bits.
  • the number of bits used for the R, G and B co-applicants determines the number of colors possible for each pixel.
  • components R, G and B coded on 8 bits each make it possible to describe 2 3 ⁇ 8, that is to say more than 16 million different colors.
  • all the pixels of the same image are conventionally coded with the same number of bits. We sometimes add to the three components R, G and B, an A component corresponding to transparency information.
  • a known solution for reducing the number of bits encoding an image consists in creating a reference table, or palette of colors (Color Look Up Table, or CLUT) containing a limited number of colors coded as the original colors of the pixels of the image. 'picture.
  • the RGB coding of the original color of each pixel is then replaced by a CLUT code corresponding to an address of a color of the palette, which is closest to the original color of the pixel.
  • the coding of its addresses may include a reduced number of bits compared to that used in the RGB coding of the original colors.
  • the CLUT code of a color can have a reduced number of bits compared to the number of bits of an RGB code.
  • a palette of 256 colors each of which is coded in 24-bit RGB
  • Such a substitution makes it possible to significantly reduce (approximately by three in this example) the amount of information represented by an image.
  • a digital image processing device we find complete color coding (RGB type) and reduced (CLUT type) described above. For example, a image can be created with full color coding and then it can be transformed so as to have a coding of reduced color, which allows rapid transmission by modem or touch it up with software. Finally, such image can be transformed again to have a coding of full color, which allows for example to display it on a computer screen.
  • Some image processing devices are intended to receive multiple images and to assemble into a single image. As an example, we consider thereafter an image composition circuit, better known as its Anglo-Saxon designation "blitter", conventionally used to create an image from several provenances images various.
  • FIG. 1 shows schematically in the form of blocks an example of an image processing device 2, for example a graphics card from a computer.
  • Device 2 includes a memory 4 in which are stored several digital images may have color coding different, complete or reduced.
  • Memory (MEM) 4 is connected to a bus 6 so as to receive write and reading and providing or receiving data.
  • a central unit processor (CPU) 8 is connected to bus 6 so that receive or provide data or orders.
  • Device 2 also includes an image composition circuit 9 provided a calculation circuit (BLITTER CORE) 10 and two memories memory buffers (BUF1) 12 and (BUF2) 14.
  • the circuit 10 includes first and second image inputs connected respectively through the intermediate memories 12 and 14 so as to receive data from bus 6.
  • the circuit 10 includes a data output which constitutes the output of the image composition circuit 9. This output is connected to through an intermediate memory or memory buffer (BUF3) 16 to a display device (DISP) 18.
  • the intermediate memory 16 is also connected to bus 6 so as to receive commands or data from the central processing unit and to
  • the calculation circuit 10 of the image composition 9 is provided for processing images having a given color coding, for example CLUT coding. Images having a different color coding, in this example a coding RGB or similar, must be converted to have this coding CLUT before it can be supplied to the calculation circuit 10. So, images having a color coding not directly usable by the calculation circuit are read in memory 4 by the central unit or processor 8 which converts their coding then control their writing in one of the intermediate memories 12 or 14 of the image composition circuit 9. When both intermediate memories 12 and 14 contain images having a color coding usable by the calculation circuit 10, the circuit 10 reads their respective contents and produces an image that it provides to the intermediate memory 16.
  • a given color coding for example CLUT coding.
  • images having a different color coding in this example a coding RGB or similar, must be converted to have this coding CLUT before it can be supplied to the calculation circuit 10. So, images having a color coding not directly usable by the calculation circuit are read in memory 4 by the central unit or processor 8 which converts their
  • the images produced by circuit 10 may not be in a code directly usable by the display device 18.
  • the image contained in the intermediate memory 16 should be read and its color coding should be converted by processor 8 before it can be delivered to display device 18 via memory intermediate 16.
  • the central processing unit treatment should be used frequently to convert images in the format accepted by the circuit of calculation of the circuit of image composition.
  • Such use of the central unit does not not allow it to be used for other tasks, which is detrimental to performance of the system in which circuit 10 is integrated, for example a microcomputer.
  • the present invention aims to overcome the drawbacks known image composition circuits.
  • the present invention aims, in particular, to propose an image processing circuit making it possible to save working time of the central processing unit of the system in which it is integrated.
  • the present invention also aims to provide such a image processing circuit which comprises a circuit having a color coding conversion function and a function of composition of images.
  • the present invention further aims to provide a particularly economical solution.
  • the present invention provides a digital image processing circuit specific to replace an entry code associated with a pixel of the image by a exit code chosen in a first storage means containing a set of codes, which includes an input bus suitable for receiving the entry code, an output bus suitable for issue the exit code, said first storage means, a means for calculating the address of the first storage means, a address selection means of the first storage means between the entry code and an address code generated by the means address calculation, a second storage means specific to contain an address code generated by the computing means address, and means for selecting the exit code between a code read at the current address of the first storage means and said code contained in the second storage means.
  • the address calculation means comprises an address generator suitable for supplying predetermined address codes by means of addressing, and a data comparison circuit provided for compare the first code and the codes stored at the addresses predetermined in the first storage means, determining that of the compared codes which is closest to the first code, and command, at the second storage means, to store the code the address where the closest compared code is stored in the first storage means.
  • the input and output buses each include a first, a second, third and fourth sub-buses having the same number of bits
  • the address selection means comprises a first, second, third and fourth multiplexers whose first inputs are respectively connected to first, second, third and fourth input sub-bus, the output of the first multiplexer being connected to the second inputs second, third and fourth multiplexers
  • the first storage means comprises a first, a second, a third and fourth identical memory circuits whose addressing inputs are respectively connected to the outputs first, second, third and fourth multiplexers
  • the exit code selection means includes a fifth multiplexer whose first input is connected to the output of data from the first memory circuit and whose output is connected to the first output sub-bus, the second, third and fourth output sub-bus being connected respectively at the data outputs of the second, third and fourth memory circuits.
  • the address generator is made up of a counter suitable for supplying a predetermined series of address codes on the second entry of the first multiplexer
  • the data comparison circuit includes: a computer connected to receive respectively the codes supplied to the first three input sub-buses and the codes provided by the first three memory circuits, and designed to supply a digital signal equal to the difference between these codes, and a memory comparator connected to store the smallest digital difference signal calculated for the predetermined series of address codes and for ordering at second memorization means of storing the address code at which codes corresponding to the smallest difference are stored in the first storage means.
  • the present invention also relates to a method of image processing by means of an image processing circuit digital according to one of the preceding embodiments, which consists of receiving images whose color codes each correspond to an address from a reference table of colors, and replace each address with the color code designated by this address in the reference table.
  • the method consists in receiving images whose colors are coded in a predetermined way, and to replace the code of each color of the image by an address of a table color reference.
  • the method includes the steps of storing, in the first, second, third and fourth circuits of memory, red, green and blue and transparency, to provide a code respectively of red, green and blue color and transparency at first, second, third and fourth input sub-bus, and at controlling the multiplexers of the address selection means and the output selection means for providing first, second, third and fourth memory circuits the codes received on the first, second, third and fourth input sub-bus, and to provide the four output sub-buses with the codes provided by the four memory circuits.
  • the method includes the steps of storing, in the first, second, third and fourth circuits of memory, red, green and blue, and transparent, to provide an address code to the first input sub-bus, and to control the multiplexers by means of address selection and the output selection means for provide the first, second, third and fourth circuits of memory, the code received on the first input sub-bus, and to supply the respective output sub-buses with the respective codes supplied by the four memory circuits.
  • the method includes the steps of storing in the first, second, third and fourth circuits of memory of the red, green and color codes respectively blue, and transparent, to provide an address code to the first input sub-bus, to provide a transparency code to the fourth input sub-bus, and to control the multiplexers by means of address selection and the output selection means for providing the first, second and third memory circuits with the code received on the first input sub-bus, to provide the fourth memory circuit the code received on the fourth sub-bus input, and to provide the four output sub-buses with the respective codes provided by the four memory circuits.
  • the method includes the steps of storing in the first, second, third and fourth circuits of memory of the red, green and color codes respectively blue, and transparent, to provide to the first, second and third input sub-bus respectively color codes red, green and blue, to activate the counter, and to control the multiplexers of the address selection means and the means of output selection to provide, to the first three circuits of stores the address codes supplied by the meter, and for provide the first output sub-bus with the address code supplied by the second storage means.
  • FIG. 2 shows a processing device images such as that of FIG. 1, comprising a circuit for image composition (BLITTER) according to the present invention.
  • the processing device includes, as before, a central processing unit (CPU) 8, memory (MEM) 4, bus 6, display device (DISP) 18 and an intermediate memory (BUF3) 16.
  • Circuit 20 also includes a calculation circuit (BLITTER CORE) 10 classic whose two inputs are connected to the outputs of two intermediate memories (BUF1) 12 and (BUF2) 14.
  • the image composition circuit 20 includes a color converter (CONV) 22 connected from so that you can convert the color coding of the images supplied to intermediate memories 12 and 14, and those of the images provided by circuit 10.
  • CONV color converter
  • the input (IN) of the converter 22 is connected to an input multiplexer (MUX1) 26 so to be able to receive data from bus 6 or from the output of the calculation circuit 10, and the output (OUT) of the converter 22 is connected to a demultiplexer (DEMUX) 28 of so that we can provide data to either intermediate memories 12 and 14, or at a first entry of a output multiplexer (MUX2) 30.
  • a second input from the multiplexer 30 is connected to the output of the calculation circuit 10, and its output is connected to memory input intermediate 16.
  • circuit 10 could, in another embodiment, be connected to bus 6 of so you can write directly to memory 4.
  • the switching elements such as the multiplexers 26 and 30 and the demultiplexer 28, converter 22 and the circuit calculation 10 are all connected so as to be controlled by central processing unit 8. Control connections necessary, as well as their management, are conventional and they do not will not be detailed further.
  • the converter 22 has the function of modifying the coding of colors of the images supplied to the computing circuit 10 or by the computation circuit 10.
  • the color codings of the images intended for the first and second inputs of circuit 10 can be modified by converter 22 before these images are stored in intermediate memories 12 and 14. From even, the color coding of an image produced by the circuit of calculation can be modified so that this image is directly usable by the display circuit 18. In the this example, this image is stored in memory intermediate 16.
  • switching elements 26, 28 and 30 allow to realize an economic circuit which uses only one single converter 22 to convert the format of written images in intermediate memories 12, 14 and 16.
  • three conversion circuits could be used separate, which is less economical but allows to obtain higher working speed.
  • FIG. 3 represents an embodiment of the color converter 22 of FIG. 2.
  • This circuit includes an input bus (IN) 32 capable of receiving an input code which is the color coding of a pixel of an input image, and an output bus (OUT) 34 capable of delivering an output code which is the color coding of the same pixel in an output image.
  • the circuit 22 also includes a first storage means or memory (MEM1) 36 storing a predetermined number of codes output, which constitutes a color reference table, by example a color palette, a second way to memorization or memory (MEM2) 38 whose role will be explained by thereafter, an address calculator (ADC) 40, connected for receive the entry code as well as the codes provided by the memory 36.
  • MEM1 first storage means or memory
  • ADC address calculator
  • the address computer 40 is also connected to provide an address code and a write command to the memory 38.
  • the conversion circuit 22 also includes a address selector (ADR) 42 connected to supply, to the memory 36, an address code received either from input bus 32 or from address calculator 40.
  • the circuit 22 further comprises a exit code selector (SEL) 44 designed to supply the bus 34, an exit code corresponding to either the codes supplied by memory 36 or the codes supplied by memory 38. It should be noted that, for reasons of clarity, we have omitted represent a third input of selector 44, connected directly to bus 32 and allowing to cross circuit 22 when the color coding of the input image should not to be changed.
  • the address calculator 40 includes an address generator (GEN) 46 provided for generating and supplying an address to the selector 42 and to memory 38.
  • the computer 40 also includes a circuit for code comparison (COMP) 47 provided to compare codes received on bus 32 with the codes provided by memory 36, and to provide memory 38 with a write command when the difference between compared codes satisfies conditions predetermined.
  • GEN address generator
  • COMP circuit for code comparison
  • the memory 36 is connected by so that its content can be modified by the central processing unit 8.
  • a feature of the invention is that the circuit 22 conversion is intended to operate in several modes.
  • the selectors 42 and 44, as well as the address calculator 40 are connected so that they can be controlled by the unit control unit 8 according to the operating modes of circuit 22.
  • the connections between the central unit and the elements of the conversion circuit 22 are within the reach of those skilled in the art and will not be described further.
  • circuit 22 of the invention provides complete codes such as RGB codes or reduced codes such as CLUT codes.
  • FIG. 3 shows in more detail a mode of circuit 22 in FIG. 3.
  • This circuit is provided to receive or provide coded color data, for example example, on 32 bits in a format called RGBA, comprising three R, G and B components each coded on 8 bits and one component A transparency coded on 8 bits.
  • this circuit can also receive or provide color data encoded in RGB on 24 bits, comprising three coded R, G and B components on 8 bits each. In such a case, the previous component A will simply be ignored.
  • the circuit 22 can also receive or provide color data in the form of a CLUT code of 8 bits corresponding to an address of a palette of 256 colors.
  • the bus Input 32 includes four 8-bit sub-buses 321 to 324.
  • the selector 42 includes four multiplexers 421 to 424 receiving respectively, on a first input, the sub-buses 321 to 324.
  • the memory 36 includes four memory circuits 361 to 364 having each 256 8-bit memory locations, marked with a address between 0 and 255.
  • the addressing entries of memory circuits 361 to 364, on 8 bits, are respectively connected to the outputs of multiplexers 421 to 424.
  • the output bus 34 comprises four 8-bit sub-buses 341 to 344.
  • the selector 44 comprises a multiplexer 441 of which a first input is connected at the output of memory circuit 361, and the output of which is connected to sub-bus 341.
  • Sub-buses 342 to 344 are connected respectively at the outputs of memory circuits 362 to 364.
  • the output of multiplexer 421 is connected to the second inputs of multiplexers 422 to 424.
  • the address generator 46 is a counter capable of providing a predetermined series of codes 8-bit address at the second input of multiplexer 421 as well at the entry of memory 38.
  • Memory 38 has only one 8-bit memory location. The output of memory 38 is connected to the second input of multiplexer 441.
  • the comparison circuit 47 includes a computer (CAL) 471, including a first, a second and a third inputs, are respectively connected to the sub-buses 321, 322 and 323 and including a fourth, fifth and sixth entry are respectively connected to the outputs of the three circuits memory 361, 362 and 363.
  • the computer 471 is provided for provide a digital signal called "difference" equal to the sum absolute values of the differences, respectively codes received on the first and fourth entry, the second and the fifth entry, and third and sixth entry.
  • the comparison circuit 47 further comprises a comparator with memory (C / M) 472 connected to store the difference signal the weakest difference signal calculated by the computer 471 for the predetermined series of address codes.
  • Comparator 472 is further connected so that, when store this difference signal, command memory 38 to store the address code provided by the counter 46.
  • a first control terminal 500 is connected to the selection terminals of multiplexer 422 and 423 inputs.
  • a second terminal command 501 is connected to the input selection terminal of the multiplexer 424.
  • a third control terminal 502 is connected to the input selection terminals of multiplexers 421 and 441, as well as to a control terminal of the counter 46.
  • These three control terminals are conventionally connected, by example to a control register of the central unit.
  • the memory circuits 361 to 364 are also connected so that the central unit can change their content.
  • Figures 4A to 4D show with the same references the elements of the circuit of figure 4 in different operating modes taken as an example. To facilitate the reading these figures, the unused elements in each of modes are hatched.
  • Figure 4A shows the circuit of Figure 4 in a first mode of operation, called transposition of colors, where the color codes are changed but not the nature of coding.
  • Sub-buses 321 to 323 respectively receive components R, G and B coded on 8 bits of a pixel and the sub-bus 324 receives an A component of transparency coded on 8 bits of this same pixel.
  • Multiplexers 421 to 424 are controlled so as to supply the memory circuits 361 to 364 with the codes received on sub-buses 321 to 324.
  • the components R, G, B and A are thus used directly as addresses by each of the circuits 361 to 364.
  • the output selector 44 is controlled from so that the code supplied by circuit 361 is supplied to the sub-bus 341.
  • the codes supplied to each of the sub-buses 341 to 344 are the codes supplied by the respective circuits 361 to 364.
  • Memory circuits 361 to 364 are respectively loaded with 256 R, G, B and A components coded on 8 bits each, which constitute a palette of colors and transparency.
  • ⁇ gamma
  • ⁇ correction consists of replacing a color which we know will be changed on display by a close color which, modified on display by the tube, will match the original color.
  • the correction ⁇ is carried out by the display device, usually analogically.
  • a drawback is that the entire image to be displayed undergoes the correction, even if this image is composed of several sub-images some of which do not require correction. Indeed, according to their origin, certain images received by the circuit of image composition may already have undergone a ⁇ correction, by example, depending on the website from where they are downloaded.
  • the image composition circuit of this invention makes it possible to harmonize the level of correction ⁇ of images produced. It is indeed possible to store, in the memory 36, a color table with a correction ⁇ or possibly an inverse ⁇ correction table, depending on whether wants to produce at the output of the image composition circuit a image with or without ⁇ correction, from of images already having a ⁇ correction or not. Note that the operating mode selection can be changed by course of composing an image to display so it's possible to affect ⁇ correction only of parts of the image composite.
  • Figure 4B shows the circuit of Figure 4 in a second operating mode for converting an image into reduced code to an image in full code.
  • Multiplexers 422 to 424 are ordered to supply the codes received on their second inputs, and multiplexer 421 is controlled to output the codes received on its first entry. So, in this mode, the memory circuits 361 to 364 receive, as address, the 8 bits of code received on sub-bus 321. Also, the multiplexer 441 is controlled so that the sub-bus 341 is connected to the output of memory circuit 361, from which it results that the output sub-buses 341 to 344 respectively receive the outputs of memory circuits 361 to 364.
  • the circuits of memory 361 to 364 are respectively loaded with 256 R, G, B and A components coded on 8 bits each, which constitute a palette of colors and transparency.
  • an 8-bit CLUT code is supplied to the sub-bus 321, and the circuit associates it with an RGBA color code coded on 32 bits.
  • This operating mode corresponds, for example, to a classic CLUT / RGBA conversion.
  • the colors of the color palette can be modified to integrate ⁇ correction functions such as previously described.
  • Figure 4C shows the circuit of Figure 4 in a variant of the second operating mode of FIG. 4B.
  • multiplexer 424 is controlled from so as to supply the memory circuit 364 with the codes received on sub-bus 324.
  • CLUT code 8 bits received on sub-bus 321 a RGB color code coded on 24 bits
  • transparency information A received on the sub-bus 324 transparency information coded on eight bits supplied on sub-bus 344.
  • This variant allows, for example, use a transparency palette with a number reduced of values which will receive a component A having a number of reduced bit, for example 4 bits, and which will provide a component of transparency coded on 8 bits at sub-bus 344.
  • Figure 4D shows the circuit of Figure 4A in a fourth operating mode for converting an image into full code to a reduced code image.
  • the multiplexers 421 to 424 are controlled so as to provide the memory circuits 361 to 364 the codes received on their seconds respective entries.
  • the counter 46 is ordered to successively generate 256 codes corresponding to addresses 0 to 255. These address codes are supplied to the circuits 361 to 364 via multiplexers 421 to 424, as well as to the memory 38.
  • each circuit 361 to 364 successively provides the codes contained in its 256 memory locations.
  • the computer 471 calculates the differences between the codes received on the input sub-buses and the codes supplied by circuits 361 to 364 in response to 256 address codes produced by counter 46.
  • the comparator 472 stores the difference calculated for the first address code (0) supplied by counter 46. Then, whenever the difference between the codes received on the input bus and the codes supplied by the memory 36 is less than this first stored difference, comparator 472 supplies a write signal to memory 38.
  • the memory 38 also receives the 256 address codes supplied to memory 36. This stores the code of the address at which is stored, in circuits 361 to 364, the color whose code is the closest to the color code received on bus 32. In this operating mode, the multiplexer 441 is controlled from so as to supply the address supplied to the output sub-bus 341 by memory 38.
  • This operating mode allows, for example, to associate with a color coded in RGB on 24 bits, a CLUT code of 8 bits associated with a color palette stored in the memory 36.
  • the data stored in the circuits 361 to 364 are always 8-bit codes, red, green and blue respectively and transparency, these data may vary depending on the modes of operation.
  • the present invention provides that the content of memory 36 can be changed between each mode of operation.
  • the conversion circuit of Figure 4 can be used in other operating modes than those described in connection with FIGS. 4A to 4D for converting images having different color codes from those described, for example RGB codings using less than 24 bits.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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EP00410126A 1999-10-25 2000-10-24 Rekonfigurierbarer Farbkonverter Withdrawn EP1096383A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9913544 1999-10-25
FR9913544A FR2800180B1 (fr) 1999-10-25 1999-10-25 Convertisseur de couleurs reconfigurable

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EP1096383A1 true EP1096383A1 (de) 2001-05-02

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KR100513328B1 (ko) * 2001-12-21 2005-09-07 엘지전자 주식회사 일련의 데이터 워드를 변조신호로 변환하는 장치 및 방법
JP4748077B2 (ja) * 2007-02-14 2011-08-17 セイコーエプソン株式会社 画素データ転送制御装置及び画素データ転送制御方法

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US6744439B1 (en) 2004-06-01
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