EP1093161A1 - Verfahren und Verbundanordnung zur Korrosionshemmung einer Metallschicht nach dem chemisch-mechanischen Polieren - Google Patents

Verfahren und Verbundanordnung zur Korrosionshemmung einer Metallschicht nach dem chemisch-mechanischen Polieren Download PDF

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Publication number
EP1093161A1
EP1093161A1 EP00308926A EP00308926A EP1093161A1 EP 1093161 A1 EP1093161 A1 EP 1093161A1 EP 00308926 A EP00308926 A EP 00308926A EP 00308926 A EP00308926 A EP 00308926A EP 1093161 A1 EP1093161 A1 EP 1093161A1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
metal layer
composition
corrosion inhibiting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00308926A
Other languages
English (en)
French (fr)
Inventor
Kapila Wijekoon
Doyle Edward Bennett
Stan D. Tsai
Brian J. Brown
Madhavi Chandrachood
Fred C. Redeker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of EP1093161A1 publication Critical patent/EP1093161A1/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

Definitions

  • a multi-station CMP polishing apparatus is employed in practicing the invention.
  • the CMP apparatus has at least one carrier head for manipulating a semiconductor substrate and at least one platen for receiving and rotating a polishing pad.
  • a detailed description of a CMP apparatus can be found in U.S. Patent No. 5,738,574 and assigned to the assignee of the present invention, the disclosure of which is hereby incorporated by reference.
  • Figure 2 illustrates a support plate, 200, which is part of substrate backing assembly (not show for illustrative convenience) and a flexible member, 230, surrounding support plate 200.
  • the backing assembly would typically be attached to base and housing respectfully (also not shown for illustrative convenience).
  • Support plate 200 may generally be a disk-shaped rigid member having a generally planar lower surface 210 with a horizontally-projecting lip 220 at its outer edge.
  • Support plate 200 may be formed of aluminum or stainless steel.
  • a plurality of apertures may extend vertically through support plate 200 to allow communication of a vacuum source with lower surface 210 and membrane 230.
  • Membrane 230 can also include an outer flap 236 connecting center portion 232 to perimeter portion 234. As discussed in U.S. Patent Application Serial No. 09/296,935, filed April 22, 1999, incorporated herein by reference, outer flap 236 can form a seal with the backside of the mounted substrate.
  • chamber 240 When chamber 240 is evacuated, the substrate is vacuum chucked to the mounting surface 238, and is pulled away from the polishing pad. This vacuum chucking procedure can be performed without applying a substantial downward pressure on the substrate.
  • a semiconductor substrate having the composite arrangement shown in Figure 1 is mounted on to a carrier head as, for example, a carrier head having the support plate and flexible member shown in Figure 2, of a CMP apparatus.
  • the exposed surface of the substrate is then placed against a rotating polishing pad, which in turn is mounted on a rotating platen driven by an external driving force.
  • the carrier head provides a controllable force, i.e. pressure, urging the substrate against the rotating polishing pad thereby planarizing and/or polishing the exposed layer on the substrate.
  • the substrate can be placed on a different platen having a different polishing pad for subsequent processing. Given the guidance and objectives of the present disclosure, the optimum polishing conditions can be necessarily determined in a particular situation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
EP00308926A 1999-10-12 2000-10-11 Verfahren und Verbundanordnung zur Korrosionshemmung einer Metallschicht nach dem chemisch-mechanischen Polieren Withdrawn EP1093161A1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15837299P 1999-10-12 1999-10-12
US158372P 1999-10-12
US56063400A 2000-04-28 2000-04-28
US560634 2000-04-28

Publications (1)

Publication Number Publication Date
EP1093161A1 true EP1093161A1 (de) 2001-04-18

Family

ID=26854978

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00308926A Withdrawn EP1093161A1 (de) 1999-10-12 2000-10-11 Verfahren und Verbundanordnung zur Korrosionshemmung einer Metallschicht nach dem chemisch-mechanischen Polieren

Country Status (3)

Country Link
EP (1) EP1093161A1 (de)
JP (1) JP2001196379A (de)
KR (1) KR20010040066A (de)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111665A2 (de) * 1999-12-21 2001-06-27 Applied Materials, Inc. Verfahren zum Planarisieren der Oberfläche eines Substrates
WO2003006205A2 (en) * 2001-07-13 2003-01-23 Applied Materials, Inc. Barrier removal at low polish pressure
US6716771B2 (en) * 2002-04-09 2004-04-06 Intel Corporation Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface
WO2004034451A1 (ja) * 2002-10-11 2004-04-22 Wako Pure Chemical Industries, Ltd. 基板洗浄剤
US7008554B2 (en) 2001-07-13 2006-03-07 Applied Materials, Inc. Dual reduced agents for barrier removal in chemical mechanical polishing
US7037174B2 (en) 2002-10-03 2006-05-02 Applied Materials, Inc. Methods for reducing delamination during chemical mechanical polishing
US7060606B2 (en) 2001-07-25 2006-06-13 Applied Materials Inc. Method and apparatus for chemical mechanical polishing of semiconductor substrates
JP2018016827A (ja) * 2016-07-25 2018-02-01 住友金属鉱山株式会社 有機被膜の製造方法、導電性基板の製造方法、有機被膜製造装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060043082A (ko) 2004-02-24 2006-05-15 마츠시타 덴끼 산교 가부시키가이샤 반도체장치의 제조방법
JP5720573B2 (ja) * 2009-10-02 2015-05-20 三菱瓦斯化学株式会社 シリコンエッチング液およびエッチング方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536690A (ja) * 1991-07-26 1993-02-12 Hitachi Ltd 耐食皮膜の形成方法と半導体装置及び光記録媒体
JPH1140526A (ja) * 1997-07-22 1999-02-12 Hitachi Ltd 配線形成方法及び半導体装置の製造方法
JP2000040679A (ja) * 1998-07-24 2000-02-08 Hitachi Ltd 半導体集積回路装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536690A (ja) * 1991-07-26 1993-02-12 Hitachi Ltd 耐食皮膜の形成方法と半導体装置及び光記録媒体
JPH1140526A (ja) * 1997-07-22 1999-02-12 Hitachi Ltd 配線形成方法及び半導体装置の製造方法
JP2000040679A (ja) * 1998-07-24 2000-02-08 Hitachi Ltd 半導体集積回路装置の製造方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 017, no. 325 (E - 1384) 21 June 1993 (1993-06-21) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 05 31 May 1999 (1999-05-31) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 05 14 September 2000 (2000-09-14) *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111665A3 (de) * 1999-12-21 2004-01-02 Applied Materials, Inc. Verfahren zum Planarisieren der Oberfläche eines Substrates
US7041599B1 (en) 1999-12-21 2006-05-09 Applied Materials Inc. High through-put Cu CMP with significantly reduced erosion and dishing
EP1111665A2 (de) * 1999-12-21 2001-06-27 Applied Materials, Inc. Verfahren zum Planarisieren der Oberfläche eines Substrates
US7008554B2 (en) 2001-07-13 2006-03-07 Applied Materials, Inc. Dual reduced agents for barrier removal in chemical mechanical polishing
WO2003006205A3 (en) * 2001-07-13 2003-12-18 Applied Materials Inc Barrier removal at low polish pressure
WO2003006205A2 (en) * 2001-07-13 2003-01-23 Applied Materials, Inc. Barrier removal at low polish pressure
US7104869B2 (en) 2001-07-13 2006-09-12 Applied Materials, Inc. Barrier removal at low polish pressure
US7060606B2 (en) 2001-07-25 2006-06-13 Applied Materials Inc. Method and apparatus for chemical mechanical polishing of semiconductor substrates
US6716771B2 (en) * 2002-04-09 2004-04-06 Intel Corporation Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface
US7037174B2 (en) 2002-10-03 2006-05-02 Applied Materials, Inc. Methods for reducing delamination during chemical mechanical polishing
US7244168B2 (en) 2002-10-03 2007-07-17 Applied Materials, Inc. Methods for reducing delamination during chemical mechanical polishing
WO2004034451A1 (ja) * 2002-10-11 2004-04-22 Wako Pure Chemical Industries, Ltd. 基板洗浄剤
JP2018016827A (ja) * 2016-07-25 2018-02-01 住友金属鉱山株式会社 有機被膜の製造方法、導電性基板の製造方法、有機被膜製造装置

Also Published As

Publication number Publication date
JP2001196379A (ja) 2001-07-19
KR20010040066A (ko) 2001-05-15

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