EP1040574B1 - Artificial line - Google Patents

Artificial line Download PDF

Info

Publication number: EP1040574B1
Authority: EP; European Patent Office
Prior art keywords: artificial line; artificial; line; switching element; frequency
Prior art date: 1997-12-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

EP98954902A

Other languages

German (de)

English (en)

French (fr)

Other versions

EP1040574A1 (en

Inventor

Aziz Ouacha

Börje CARLEGRIM

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

TotalFoersvarets Forskningsinstitut FOI

Original Assignee

TotalFoersvarets Forskningsinstitut FOI

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1997-12-19

Filing date

1998-11-10

Publication date

2005-03-23

1998-11-10 Application filed by TotalFoersvarets Forskningsinstitut FOI filed Critical TotalFoersvarets Forskningsinstitut FOI

2000-10-04 Publication of EP1040574A1 publication Critical patent/EP1040574A1/en

2005-03-23 Application granted granted Critical

2005-03-23 Publication of EP1040574B1 publication Critical patent/EP1040574B1/en

2018-11-10 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

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Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
- H03H11/265—Time-delay networks with adjustable delay

Definitions

the present invention relates to an artificial line, i.e. an artificial electric line, and specifically an artificial line having a constant group delay in a wide frequency range (octave bandwidths)
an artificial line i.e. an artificial electric line
an artificial line having a constant group delay in a wide frequency range e.g. from US 4885562.
the invention originates from delay lines for radar applications and will partly be described starting from this.
the invention can be applied in other contexts where an artificial line having the achieved properties can be used. Therefore the inventor aims at protecting the artificial line by a patent, based on its construction and its properties and independently of the place where it is used.
phased array antennas Since such antennas may have hundreds of modules, monolithic integrated microwaves circuits (MMIC) are necessary to minimise size and weight.
MMIC monolithic integrated microwaves circuits
Most prior-art microwave systems with phased array antennas are provided with binary control devices. In large installations, a great number of control wires will be involved since each element must be controlled individually. If an analog control device could be used, much would be gained since only one control wire or a few control wires would be required.
phase shifters cannot be used since they cause a change in the beam direction, phase squinting, and distortion of the pulses, pulse stretching. Therefore the invention instead uses a special embodiment of a controllable delay element since such elements allow frequency-independent beam steering.
Prior-art controllable delay elements are digital, which causes losses. Besides they are expensive.
Fig. 1 shows a prior-art binary 4-bit delay element using single-pole double-throw switches (SPDT).
SPDT single-pole double-throw switches
Single-pole double-throw switches have considerable losses, which means that the prior-art delay element all in all exhibits great losses. If in Fig. 1 the delay ⁇ t is 8 ps, the maximum delay will be 120 ps.
the present invention solves the above problem by providing an artificial line with controllable delay and low losses and at a, relatively seen, low cost by being designed in the manner that appears from the independent claim.
Advantageous embodiments of the invention are defined in the remaining claims.
the invention concerns basically an artificial line which in a first state has the desired properties in respect of constant group delay in a wide frequency range.
the artificial line can then be accomplished as a continuously tunable artificial line or as a self-switched artificial line.
Fig. 2 illustrates how, in one embodiment, it would be possible to build a composed artificial line which can delay signals by a total of 120 ps, the same as in the previous case of the prior-art artificial line.
a tunable artificial line A as well as self-switched artificial lines B.
the continuously tunable artificial line has, in dependence on a control signal, a delay of up to about 20 ps.
five self-switched artificial lines are cascade-coupled to this artificial line.
the self-switched artificial line can take two distinct states. In one state, it has a small delay, and in the other a large delay, in the example at issue about 20 ps.
the self-switched artificial lines can be controlled by a single control wire, which means a considerable simplification.
Both types of artificial line are based on an all-pass network with a frequency-independent mirror impedance (constant-R all-pass network). In the tunable case, it is more correct to speak of essentially frequency-independent mirror impedance (quasi constant-R ).
Fig. 3a illustrates a known all-pass network. It consists of a bridged T-section consisting of two mutually coupled inductors of equal value L, which form the two arms, a capacitor C 2 to earth, forming the vertical arm, and a capacitor C 1 coupled over the inductors. Under specific conditions, this network becomes an all-pass network having a constant input impedance which is independent of frequency.
the transfer function has a low-pass character.
the normalised circuit elements can now be expressed as functions of a and b. Insertion of the expressions for a and b in (12) results in
the transfer phase must have a linear frequency response.
the group delay GD ( ⁇ ) must be constant with frequency.
the self-switched artificial line can take two states. In one state, the circuit has component values according to equation (18), which results in a large delay. In the second state, the capacitor C 1 is short-circuited, which gives a short delay.
the capacitor C 1 can be implemented as a metal-insulator metal (MIM) capacitor in an MMIC design.
MIM metal-insulator metal
the capacitor C 1 is exchanged for a first switching element which can be described as a small resistor in a first state (on-state) and a capacitor in a second state (off-state), e.g. a PIN diode, a bipolar transistor or a "switch-FET".
the transistor is biased so as to be fully depleted,
the transistor then corresponds to a capacitor. If the transistor parameters are selected such that the capacitance of the transistor is C 1 , the circuit obtains, according to the derivation which results in equation (18), a group delay which is independent of the frequency in a wide frequency range.
the shunt capacitor C 2 is normally not small enough to give a high impedance to the line when the first field effect transistor FET 1 is in the first state. This results in a deterioration of the scattering properties, especially at high frequencies.
a solution to this is to connect a second switching element, of a type similar to the first one, in series with the capacitor C 2 . This second switching element is driven complementarily with the first, i.e. when the first is conductive, the second is fully depleted and vice versa. In this way, the line becomes shunted by a high impedance compared with C 2 only.
Fig. 8 shows a variant of this advantageous embodiment of the invention with a second field effect transistor, FET 2, optimised to take, in dependence on its control voltage, two distinct states, as the second switching element.
Figs 9 and 10 Two examples of a concrete layout for a self-switched artificial line in a planar monolithic circuit technique are shown in Figs 9 and 10.
the cut-off frequency is selected to be 18 GHz and the characteristic impedance to be 50 ⁇ .
the desired element values are the same in the two examples.
the embodiments result in different group delay owing to the different geometric design of the circuits, which will be described below.
the embodiments in the Figures are drawn according to scale for accomplishment on a 100 ⁇ m-thick GaAs substrate having the permitivity 12.8.
Fig. 9 shows an embodiment in which the largest possible difference in group delay between the two states of the circuit is desired.
the circuit has an input 1 and an output 2.
the inductances and the mutual inductance are realised as coupled microstrip lines 3.
the bias of FET 1 and FET 2 is applied to the bonding pads 8a and 8b, respectively, and is supplied to the gate via the respective resistors 9a and 9b which are here designed as doped channels in the substrate with controlled resistivity
Fig. 10 shows an embodiment in which a smaller difference in group delay between the two states of the circuit is desired.
the circuit has an input 1 and an output 2.
the inductances and the mutual inductance are realised as coupled microstrip lines 3.
only one insulating crossover 5 is necessary.
the bias of FET 1 and FET 2 is applied to the bond plates 8a and 8b, respectively, and is supplied to gate via the respective resistors 9a and 9b, which are here designed as doped channels in the substrate with controlled resistivity.
Fig. 11 shows an example of cascade-coupled self-switched artificial lines.
the continuously tunable group delay is achieved by the capacitors C 1 and C 2 in the two-port network according to Fig. 3a being replaced by varactors, see Fig. 13.
the varactors are selected such that their capacitances C 1 and C 2 are variable and follow the curves in Fig. 5 in the range for the desired variation of the group delay.
the inductances L and the mutual inductance M will not follow the relation exactly, and therefore the properties of the circuit are slightly deteriorated.
the deterioration of the input and output impedance is normally acceptable. It is in this case more correct to speak about an essentially frequency-independent mirror impedance (quasi constant-R ).
Fig. 15 illustrates an example of a layout for a tunable artificial line.
the circuit has an input 1 and an output 2.
the inductances and the mutual inductance are realised as coupled microstrip lines 3.
the voltage-controlled capacitance C V 1 is designed as a varactor consisting of a field effect transistor 4a where the drain and source are interconnected and the bias for tuning is applied to its gate.
the voltage-controlled capacitance C V 2 is also designed as a varactor 4b composed in the same manner as the first-mentioned varactor 4a.
the drain and source of this varactor 4b are connected to the ground plane of the circuit with a via hole 7.
the design uses an insulating crossover 5.
the voltage for tuning of C V 1 and C V 2 is applied to the bonding pads 8a and 8b respectively and is supplied to the gate via the respective resistors 9a and 9b which are here designed as doped channels in the substrate with controlled resistivity.
Two MIM capacitors 10a and 10b have been introduced for the varactors to be biased.

Landscapes

Networks Using Active Elements (AREA)
Filters And Equalizers (AREA)
Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Microwave Amplifiers (AREA)
Prostheses (AREA)
External Artificial Organs (AREA)

EP98954902A 1997-12-19 1998-11-10 Artificial line Expired - Lifetime EP1040574B1 (en)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
SE9704758		1997-12-19
SE9704758A SE509839C2 (sv)	1997-12-19	1997-12-19	Konstledning
PCT/SE1998/002021 WO1999035740A1 (sv)	1997-12-19	1998-11-10	Artificial line

Publications (2)

Publication Number	Publication Date
EP1040574A1 EP1040574A1 (en)	2000-10-04
EP1040574B1 true EP1040574B1 (en)	2005-03-23

Family

ID=20409464

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP98954902A Expired - Lifetime EP1040574B1 (en)	1997-12-19	1998-11-10	Artificial line

Country Status (9)

Country	Link
US (1)	US6556096B1 (sv)
EP (1)	EP1040574B1 (sv)
JP (1)	JP2002501318A (sv)
AT (1)	ATE291793T1 (sv)
AU (1)	AU749377B2 (sv)
CA (1)	CA2315075A1 (sv)
DE (1)	DE69829504T2 (sv)
SE (1)	SE509839C2 (sv)
WO (1)	WO1999035740A1 (sv)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US8922315B2 (en) *	2011-05-17	2014-12-30	Bae Systems Information And Electronic Systems Integration Inc.	Flexible ultracapacitor cloth for feeding portable electronic device
KR101269777B1 (ko) *	2011-06-28	2013-05-30	고려대학교 산학협력단	신호 누설을 활용한 테라헤르츠 대역 위상 변화 장치 및 이를 이용한 빔포밍 시스템
TWI536733B (zh) *	2014-05-30	2016-06-01	國立臺灣大學	共模雜訊抑制裝置
US9660605B2 (en) *	2014-06-12	2017-05-23	Honeywell International Inc.	Variable delay line using variable capacitors in a maximally flat time delay filter
US10018716B2 (en) *	2014-06-26	2018-07-10	Honeywell International Inc.	Systems and methods for calibration and optimization of frequency modulated continuous wave radar altimeters using adjustable self-interference cancellation
US11005442B2 (en) *	2019-05-23	2021-05-11	Analog Devices International Unlimited Company	Artificial transmission line using t-coil sections

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4443772A (en) *	1981-12-10	1984-04-17	Rca Corporation	Switching microwave integrated bridge T group delay equalizer
FR2618610B1 (fr)	1987-07-20	1989-12-22	Dassault Electronique	Dispositif de retard hyperfrequence
USH954H (en) *	1990-07-05	1991-08-06	The United States Of America As Represented By The Secretary Of The Air Force	Lumped element digital phase shifter bit

1997
- 1997-12-19 SE SE9704758A patent/SE509839C2/sv not_active IP Right Cessation
1998
- 1998-11-10 CA CA002315075A patent/CA2315075A1/en not_active Abandoned
- 1998-11-10 DE DE69829504T patent/DE69829504T2/de not_active Expired - Lifetime
- 1998-11-10 EP EP98954902A patent/EP1040574B1/en not_active Expired - Lifetime
- 1998-11-10 AT AT98954902T patent/ATE291793T1/de not_active IP Right Cessation
- 1998-11-10 AU AU11832/99A patent/AU749377B2/en not_active Ceased
- 1998-11-10 US US09/581,199 patent/US6556096B1/en not_active Expired - Fee Related
- 1998-11-10 WO PCT/SE1998/002021 patent/WO1999035740A1/sv active IP Right Grant
- 1998-11-10 JP JP2000528013A patent/JP2002501318A/ja active Pending

Also Published As

Publication number	Publication date
DE69829504D1 (de)	2005-04-28
US6556096B1 (en)	2003-04-29
DE69829504T2 (de)	2006-02-09
SE9704758L (sv)	1999-03-15
WO1999035740A1 (sv)	1999-07-15
JP2002501318A (ja)	2002-01-15
AU1183299A (en)	1999-07-26
SE509839C2 (sv)	1999-03-15
SE9704758D0 (sv)	1997-12-19
ATE291793T1 (de)	2005-04-15
CA2315075A1 (en)	1999-07-15
AU749377B2 (en)	2002-06-27
EP1040574A1 (en)	2000-10-04

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